JPH06325186A - One-chip microcomputer and its manufacture - Google Patents

Abstract

PURPOSE:To provide a one-chip microcomputer which has a function for preventing malfunction right after resetting when connected to a peripheral controller and its manufacture. CONSTITUTION:This microcomputer has a central arithmetic unit 101 which initially sets parameters such as polarity information after resetting and outputs a setting end signal, an external output suppression signal generating device 105 which outputs an external output suppression signal after resetting and cancels the external output suppression signal once inputting the setting end signal, an output signal generating device 107 which outputs an internal output signal based upon the set parameters once inputting the parameters such as the polarity information, an initial value storage device 301 which outputs previously set initial value information to the output signal suppressing device 309, and the external output signal suppressing device 309 which outputs the initial value information as an external output signal while inputting the external output suppression signal, but outputs the internal output signal as the external output signal once the external output suppression signal is canceled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to connection of a one-chip microcomputer used for embedded applications with a peripheral control device.

[0002]

2. Description of the Related Art In recent years, a one-chip microcomputer has been incorporated into various devices and widely used for controlling the devices. Usually, the built-in one-chip microcomputer has a device for generating an output signal for controlling an external peripheral device. FIG. 7 is an example of a conventional one-chip microcomputer, and a case where the device that generates the output signal described above generates a PWM (Pulse Width Modulation) signal will be described. In the figure, the inside of the broken line is 1
A central processing unit 701, a reset signal 702, a parameter 703, an output signal generator 704, and an external output signal 705, which constitute a chip microcomputer. Built-in ROM, built-in RAM and others are omitted.

The central processing unit 701 starts its operation when the input reset signal 702 is released, and sets a parameter 703 such as polarity information in the output signal generator 704. The reset signal 702 resets the one-chip microcomputer. Parameter 703 is
It is a parameter representing the output signal to be generated by the output signal generator 704.

When the parameter 703 is input from the central processing unit 701, the output signal generator 704 outputs an external output signal 705 according to the parameter. 706
Is an external peripheral device connected to a one-chip microcomputer controlled by an external output signal 705.
After the reset signal 702 is released, the central processing unit 701 sets the parameter 703 (timing information T1, T2, T3, and polarity information) in the output signal generator 704. In response to this, the output signal generator 704 outputs a waveform corresponding to the parameter 703 as shown in FIG. 8A when the polarity information is positive logic and as shown in FIG. 8B when the polarity information is negative logic.

By setting the parameters in the output signal generator 704 in this way, the external peripheral device 70 is set after the parameters are set.
It is possible to output an arbitrary waveform according to the polarity of 6.

[0006]

However, according to the above-mentioned prior art, the polarity of the external output signal is output as it is, which is peculiar to the output signal generator, until the parameter setting is completed immediately after reset. However, there is a problem that the external peripheral device 706 may malfunction.

Specifically, the TR immediately after the reset is shown in FIG.
9-2 shows an example of a signal in which an external peripheral device having a positive logic operation malfunctions due to an output signal which becomes H during the period of FIG. An example of a signal that causes an external peripheral device to operate incorrectly will be shown. In FIG. 9, the polarity of the output signal generator immediately after the reset is the active level, so that the external peripheral device malfunctions.

In view of the above problems, it is an object of the present invention to provide a one-chip microcomputer having a function of preventing malfunction immediately after reset and a method for manufacturing the same.

[0009]

In order to solve the above problems, a one-chip microcomputer of the present invention outputs a control signal for controlling an external peripheral device based on a parameter set by a CPU in a chip. A computer, a signal generator that generates a control signal according to a parameter set by the CPU, a suppressing unit that suppresses the output of the control signal to the outside, and a reset signal from the outside to the 1-chip microcomputer. And a suppression control unit that starts the suppression operation of the suppression unit when input, and stops the suppression operation of the suppression unit when the parameter setting to the signal generation unit by the CPU is completed.

The one-chip microcomputer further comprises holding means for holding a predetermined logic level to be output during suppression, and the suppression means outputs the logic level signal held in the holding means during suppression. It may be. Further, in the method for manufacturing a one-chip microcomputer of the present invention, the holding means is manufactured by using a circuit element forming the built-in ROM so that the logic level can be written at the same time when the program is written in the built-in ROM.

A method of manufacturing a one-chip microcomputer that outputs a control signal for controlling an external peripheral device based on a value initially set by a CPU in the chip, wherein the one-chip microcomputer is in the chip. The signal generating means for outputting a control signal for controlling the external peripheral device based on the value set by the CPU of the CPU, the signal obtained by inverting the logic polarity of the control signal, or the signal as it is, is selected. Equipped with output polarity matching means,
The polarity matching means may be manufactured by using a circuit element forming the built-in ROM so that which of the signals is selected can be written at the same time when the program is written in the built-in ROM.

The circuit elements that make up the internal ROM may be programmable read-only memory (PROM) memory cells. The circuit elements constituting the internal ROM are erasable and programmable read-only memory (EPR).
OM) storage cell.

[0013]

By the above means, the one-chip microcomputer of the present invention, according to the first aspect of the invention, until the parameter setting by the CPU is completed after the external reset signal is input. The suppression control means controls the suppression means to suppress the control signal of the signal generation means. As a result, after resetting, the suppressing means suppresses the external output until the control signal of the signal generating means becomes the correct value by the parameter setting, so that the control signal to the external peripheral device is inactivated by the external pull-up or pull-down resistor. In addition, the malfunction of the external peripheral device at the time of reset can be prevented.

In addition, according to the invention of claim 2, immediately after resetting, while the control signal of the signal generating means is suppressed,
The suppressing unit outputs the logic level to be output immediately after the reset held by the holding unit. As a result, a pull-up or pull-down resistor is not required, and a malfunction of the external peripheral device at the time of reset can be prevented. According to the invention of claim 3, in the method for manufacturing a one-chip microcomputer of the present invention, the holding means uses a circuit element forming the built-in ROM to write to the built-in ROM and simultaneously write to a logic level to be held. Is manufactured to be possible.

According to the invention of claim 4, the polarity matching means outputs the polarity of the control signal outputted from the signal generating means in accordance with the external device. This polarity matching means has a built-in R
It is manufactured so that the logic level to be held can be written simultaneously with the writing to the built-in ROM by using the circuit element that constitutes the OM. According to the invention of claim 5, the built-in R
The circuit element forming the OM is a PROM memory cell,
According to the invention of claim 6, it is a memory cell of an EPROM.

According to the above-described manufacturing method, since the logic level of the control signal of the external device can be set at the same time when the built-in ROM is written, the external device having any logical polarity can be set immediately after reset until the parameter setting is completed. Can also output an inactive signal.

[0017]

【Example】

(Embodiment 1) FIG. 1 is a block diagram of a one-chip microcomputer in the first embodiment of the present invention. Built-in R
The OM, built-in RAM and others are omitted. In the figure, 101 is a central processing unit, which starts operation when a reset signal 102 input from the outside is released, and outputs parameters (T1, T2, T3, and polarity information) 103.
After setting, the setting end signal 104 is output.

Reference numeral 105 denotes an external output suppression signal generator, which outputs an external output suppression signal 106 when the reset signal 102 input from the outside is released, and the central processing unit 1
When the setting end signal 104 is input from 01, the external output suppression signal 106 is canceled. An output signal generator 107 always outputs an L level when the output parameter 103 is not input, and outputs an internal output signal 108 according to the parameter when the output parameter 103 is input.

Reference numeral 109 denotes an external output signal suppression device, which receives the external output suppression signal 106 and outputs the external output signal 11
The output of 0 is suppressed, and when the external output suppression signal 106 is canceled, the internal output signal 108 is output as the external output signal 110. Reference numeral 111 is a pull-up resistor, which makes the signal inactive high level (hereinafter, H level) when the external output signal 110 is not output.

An external peripheral device 112 operates in negative logic. Details of signal generation of the 1-chip microcomputer configured as described above will be described with reference to the timing chart of FIG. At reset, output signal generator 1
07 sets the internal output signal 108 to the L level and outputs it (FIG. 2-1). However, since the external output suppression signal 106 is output from the external output suppression signal generator 105 at the time of reset, the external output signal suppression device 109 does not output the external output signal 110, and the external output signal 110 is not output due to the pull-up resistor 111. It becomes H level (Fig. 2-2).

After resetting, the central processing unit 101 sets the output parameter 103, whereby the output signal generator 107 outputs a predetermined internal output signal 108 (FIG. 2-3). After that, the central processing unit 101 outputs the setting end signal 104 to the external output suppression signal generation device 105 (Tc timing in FIG. 2), so that the external output suppression signal 106 is canceled and the external output signal suppression device 109 internally operates. By outputting the output signal 108 as the external output signal 110 (FIG. 2-4), the external peripheral device 112 operates normally.

As described above, in the one-chip microcomputer according to the present embodiment, after reset, a device for suppressing the output is added until the output signal becomes the correct output signal by the parameter setting. When enabled, the existing 1-chip microcomputer and the existing external peripheral device can be easily connected while preventing the problem of malfunction of the external peripheral device immediately after resetting due to the polarity.

(Embodiment 2) FIG. 3 is a block diagram showing a one-chip microcomputer in the second embodiment of the present invention. In the same figure, those given the same reference numerals as those in FIG.

An initial value storage device 301 outputs preset initial value information 302. The initial value storage device 301 is configured by using the same circuit element as the built-in ROM, and the initial value is written at the same time when the program is written in the built-in ROM. An external output signal suppression device 309 outputs the initial value information 302 when the external output suppression signal 106 is input, and outputs the internal output signal 108 as the external output signal 110 when the external output suppression signal 106 is canceled.

1 in the present embodiment configured as described above
Details of signal generation of the chip microcomputer will be described with reference to the timing chart of FIG. At reset,
The output signal generator 107 becomes an L level output (Fig. 2-
1). However, since the external output suppression signal generator 105 outputs the external output suppression signal 106 at the time of reset, the external output signal suppression device 109 outputs the external output signal 11
Initial value information 3 output from the initial value storage device 301 as 0
02 is output (FIG. 2-2).

After the reset, the central processing unit 101 sets the output parameter 103 so that the output signal generator 107 outputs the intended internal output signal 108 (FIG. 2-3). Thereafter, the central processing unit 101 outputs the setting end signal 104 to the external output suppression signal generation device 105 (timing of Tc), so that the external output suppression signal 10 is generated.
6 is canceled and the external output signal suppressing device 109 outputs the internal output signal 108 as the external output signal 110 (FIGS. 2-4), whereby the external peripheral device 112 operates normally.

As described above, in the one-chip microcomputer of this embodiment, after resetting, the signal is made effective by adding a device that outputs a preset value until the output signal becomes a correct output signal by parameter setting. By doing so, the existing 1-chip microcomputer and the existing external peripheral device can be easily connected while preventing the problem of malfunction of the external peripheral device immediately after resetting due to the polarity. Further, as compared with the one-chip microcomputer of the first embodiment, an external circuit is unnecessary, and the initial value is set in the initial value storage device when the program is written in the built-in ROM in the one-chip microcomputer. Since it can be done at the same time, it also has the effect that the number of man-hours does not increase.

(Embodiment 3) FIG. 4 is a block diagram showing a one-chip microcomputer in the third embodiment. In the figure, the same reference numerals as those in FIG.
The description is omitted because it is the same as the embodiment described above. An output signal generator 401 outputs an internal output signal 108 of the positive logic according to the set parameter when the output parameter 103 is input when the output parameter 103 is not input.

Reference numeral 402 denotes a polarity matching device, which polarizes the input internal output signal 108 to positive logic or negative logic in accordance with a peripheral device to be connected in advance, and then outputs it as an external output signal 110. This polarity matching device 40
Reference numeral 2 includes a logical NOT circuit and a changeover switch, and selectively outputs whether to invert the logic of the internal output signal 108 or to leave it as it is. The changeover switch is configured by using the same circuit element as the built-in ROM, and has a built-in R
Which is selected at the same time as the OM writing is set.

Details of signal generation of the one-chip microcomputer in the above configuration will be described with reference to the timing chart of FIG. At reset, output signal generator 4
01 becomes an L level output. Then, the central processing unit 10
1 sets the output parameter 103, the output signal generator 401 outputs the positive logic internal output signal 108 (FIG. 5-1).

The internal output signal 108 input to the polarity matching device 402 is converted into a preset logic and output as an external output signal 110. In this embodiment, the logic is inverted (FIG. 5-2),
The external output signal 110 is output to the external peripheral device 112, and the external peripheral device 112 operates normally. As described above, in the one-chip microcomputer of the third embodiment, by adding a device for preliminarily matching the polarities to the one-chip microcomputer according to the polarity of the external peripheral device, the parameters can be set after the reset. By outputting an inactive signal until the output signal becomes a correct output signal, it is possible to easily connect while preventing the malfunction of the external peripheral device immediately after resetting due to the polarity of the existing 1-chip microcomputer and the existing external peripheral device. can do. Further, the load of hardware / software is less than that of the 1-chip microcomputer of the first and second embodiments, and the polarity setting for the polarity matching device is performed by the built-in program in the 1-chip microcomputer. Since it can be performed simultaneously when writing to the ROM, it also has an effect that the number of steps does not increase.

In the first to third embodiments, the external peripheral device has been described as operating in negative logic, but may be in positive logic and PWM is taken as an example of the output signal generating device, but other devices may be used. Absent. In addition, in the first and second embodiments,
The external output signal is a negative logic signal and is configured to be inactive until the parameter setting is completed immediately after reset. However, the external output signal is not limited to this, and positive logic / inactive at reset as shown in FIG. (Figure 6-1), positive logic / reset active (Figure 6-2), negative logic / reset inactive (Figure 6-3), negative logic / reset active (Figure 6-4). It is possible to generate a signal of Similarly, in the third embodiment, it is possible to generate two patterns of signals: positive logic / inactive at reset (FIG. 5-2) and negative logic / inactive at reset (FIG. 5-3). These patterns can be selected according to the specifications of the external peripheral device when the 1-chip microcomputer is incorporated in the device.

Further, in the third embodiment, the output signal generator outputs the signal of positive logic, but it may be of negative logic.

[0034]

As described above, according to the one-chip microcomputer of the present invention and the manufacturing method thereof, it is possible to prevent the malfunction of the external peripheral device immediately after the reset by suppressing the output of the external output signal immediately after the reset. Even an external peripheral device having such a polarity can be connected with matching.

Further, according to the one-chip microcomputer of the second embodiment and the method of manufacturing the same, in addition to the above effects, (1) an external circuit such as a pull-up / pull-down resistor is unnecessary externally. ) Writing the initial value to the initial value storage device is done by the built-in RO
Since the programming can be performed at the same time as writing the program into M, the design man-hours do not increase. There is an effect.

Further, in the one-chip microcomputer and the manufacturing method thereof according to the third embodiment, (1) the polarity can be easily set freely in the pin unit or the bus unit, so that the system adaptability is improved. high. (2) Compared to the first and second embodiments, the increase in hardware and software is small.

(3) Since the polarity matching device can be set at the same time when the program is written in the built-in ROM, the number of design steps does not increase. You can see that there is an effect.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a one-chip microcomputer according to a first embodiment of the present invention.

FIG. 2 is an output waveform of the one-chip microcomputer according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a one-chip microcomputer according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a one-chip microcomputer according to a third embodiment of the present invention.

FIG. 5 is an output waveform of the one-chip microcomputer according to the third embodiment of the present invention.

FIG. 6 is an output waveform of the one-chip microcomputer in the first and second embodiments of the present invention.

FIG. 7 is a block diagram of a conventional one-chip microcomputer.

FIG. 8 is an output waveform of a conventional 1-chip microcomputer.

FIG. 9 is an output waveform of a conventional one-chip microcomputer.

[Explanation of symbols]

 101 central processing unit 102 reset signal 103 output parameter 104 setting end signal 105 external output suppression signal generator 106 external output suppression signal 107 output signal generator 108 internal output signal 109 external output signal suppression device 110 external output signal 111 pull-up resistor 112 External peripheral device 301 Initial value storage device 302 Initial value information

Claims (7)

[Claims] 1. A one-chip microcomputer comprising a CPU and a control signal output means for outputting a control signal of an external peripheral device according to a parameter set by the CPU, wherein the control signal is set to a predetermined logic level. Logic level maintaining means for maintaining, logic level switching means for switching the predetermined logic level, and logic level maintaining operation of the logic level maintaining means is started at the time of reset operation of the one-chip microcomputer,
A one-chip microcomputer comprising: a logic level control means for stopping the control signal generation means when the setting of the parameter is completed. 2. The logic level switching means includes a logic level inversion circuit, a detour circuit that bypasses the logic level inversion circuit, and a selection circuit that selects the determination circuit or the detour circuit. 1. The one-chip microcomputer according to 1. 3. The one-chip microcomputer according to claim 1, wherein the logic level switching means has a resettable memory in which information indicating a predetermined logic level is set. 4. The one-chip microcomputer according to claim 1, wherein the logic level switching means has a switching circuit capable of switching the logic level only once. 5. The one-chip microcomputer according to claim 4, wherein the switching circuit has a memory capable of setting information indicating a predetermined logic level only once. 6. The one-chip microcomputer according to claim 4, wherein the switching circuit is a circuit capable of switching a logic level by cutting off a part of a circuit portion. 7. By switching the logic level switching means in the one-chip microcomputer according to claim 4, from the time of the reset operation of the one-chip microcomputer to the time of completing the setting of the parameters in the control signal generating means. A manufacturing method for manufacturing a one-chip microcomputer in which a level of a control signal to be output is set to a predetermined level.