JPH06324350A - Thin-film field effect transistor array - Google Patents

Abstract

PURPOSE:To decrease the coupling capacities between a counter electrode and signal lines and to suppress crosstalks by forming the signal lines on the same layer as the layer of gate electrodes and forming scanning lines on the same layer as the layer of source and drain electrodes. CONSTITUTION:The scanning lines 1 and the signal lines 2 are intersected and are arranged like a grid on a light transparent insulating substrate 7, such as glass plate. A TFT array having the gate electrodes 4 formed on an insulating substrate 7 near the respective intersected points of these scanning lines 1 and signal lines 2, island-shaped amorphous silicon films 10 formed via insulating films 8 on the gate electrodes 4 and the source electrodes 9 and drain electrodes 3 formed on the surface inclusive of the amorphous silicon films 10 is constituted. The TFT substrate is constituted by connecting the drain electrodes 3 of the TFTs to the signal lines 2 formed on the same layer as the layer of the gate electrodes 4 via contact holes 6 formed in the insulating films 2, connecting the gate electrodes 4 to the scanning line 1 formed on the same layer as the layer of the source electrodes 9 and the drain electrodes 3 and connecting the source electrodes 9 to pixel electrodes 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film field effect transistor array used in a matrix liquid crystal display device or the like.

[0002]

2. Description of the Related Art A technique for forming a thin film transistor (hereinafter referred to as TFT) using a silicon thin film on an insulating substrate such as glass is important as a central technique for forming an active matrix liquid crystal display device (hereinafter referred to as AMLCD). is there.

The AMLCD generally has a liquid crystal between a TFT substrate having a structure in which a pixel electrode connected to a scanning line / signal line and a thin film transistor arranged in the vicinity of an intersection thereof is provided and a counter substrate having a transparent electrode formed on the entire surface. A voltage is applied between the pixel electrode and the counter electrode which are sandwiched between them to control the light transmission state in the liquid crystal.

At this time, the pixel electrode controlled by the thin film transistor connected to the same scanning line writes the signal line supplying this writing voltage in order to write at the same time, slightly before the timing when the scanning line is turned on. Must be set to working voltage.

The liquid crystal generally deteriorates when a direct current is continuously applied. For this reason, the potential of each pixel electrode is alternately applied to the potential of the counter electrode. At this time, since the transistor operation becomes asymmetric between the case of applying the positive voltage and the case of applying the negative voltage, the completely same potential is not applied. If this positive / negative switching is performed in a wide area, this asymmetry is recognized and flicker occurs, which hinders the recognition of the display.

In order to prevent this, it has been considered to apply positive and negative voltages to adjacent pixel electrodes, but generally, the driving method is divided into several types depending on the combination of the parities between the pixels. A method of applying a potential to pixel electrodes controlled by the same signal line with the same parity and a potential applied to pixel electrodes controlled by adjacent signal lines with the opposite parity is called a drain line inversion method. On the other hand, a method of applying a voltage to pixel electrodes controlled by the same scanning line with the same parity and a pixel electrode controlled with adjacent scanning lines with the reversed parity is called a gate line inversion method. A method of driving adjacent pixel electrodes with reverse parity is called a pixel inversion method.

Normally, the voltage applied to the signal line is serially transferred from the outside during one scanning period. In order to drive by drain line inversion and pixel inversion, a drive IC that switches positive and negative at high speed is required. Therefore, normally, this method is rarely used in terms of voltage consumption and cost. Generally, the gate line inversion method is most often used.

[0008]

When the gate line inversion method is used, the pixel electrodes controlled by the same scan line are supplied with the same parity potential, and the pixel electrodes controlled by the next scan line are supplied with the opposite parity potential. Supplied. At this time, all the signal lines switch between positive and negative at the same time at the same time.

Normally, as the switching element, a thin film field effect transistor having an inverted staggered structure is often selected from the viewpoint of the cost and stability of the process. In this TFT, a gate electrode, a gate insulating film, an island-shaped amorphous silicon layer, and source / drain electrodes are arranged from the insulating substrate side. In this structure, the scanning line connected to the gate electrode is usually arranged on the substrate side, and the signal line connected to the drain electrode is arranged on the upper side.

However, when the signal line is arranged on the upper side, the signal line is capacitively coupled to the counter electrode in all regions. This capacitance increases almost in proportion to the wiring length when the wiring width is constant. In order to keep the potential of the corresponding electrode stable, it is necessary to have a conductance of the counter electrode that can sufficiently cope with this capacitance. However, as the screen size increases, the distance between the periphery and the central part increases, and the conductance of the counter electrode also decreases.

Due to such a relationship, when the electric potential of the counter electrode cannot be made constant, the amount of vibration differs depending on the electric potential of the signal line. Therefore, as shown in FIG. 4, the black display portion on the display is shown. Window white display section 12 in 11
Is displayed, a so-called crosstalk phenomenon generating section 13 whose brightness is different from the other side of the window white display section 12 is displayed [for example, 1992, S.
ID International Symposium Digest of Technical Papers (1992)
SID INTERNATIONAL SYMPOS
IUM DIGEST OF TECHNICAL P
APERS) 23, pp. 59-62].

In order to prevent this, conventionally, a method of reducing the sheet resistance of the counter electrode has been used. However, at present, transparent electrodes having stable characteristics and low resistance materials are limited, and it becomes difficult to keep the potential of the counter electrode constant when the area is further increased.

An object of the present invention is to provide AMLC over a large area.
In order to stabilize the display performance of D, it is an object of the present invention to provide a thin film field effect transistor array in which the cross-talk is suppressed by reducing the coupling capacitance between the counter electrode and the signal line.

[0014]

A thin film field effect transistor array according to the present invention comprises a scanning line and a signal line which are arranged in a lattice on an insulating substrate and intersect each other, and an intersection of the scanning line and the signal line. A gate electrode provided on the insulating substrate in the vicinity and connected to the scanning line, an island-shaped semiconductor film provided on the gate electrode via a gate insulating film, and the signal line provided on the semiconductor film. In an inverted staggered thin film field effect transistor array having a source electrode (or drain electrode) connected to it and a drain electrode (or source electrode) connected to a pixel electrode, the signal line is formed in the same layer as the gate electrode, Scan lines are formed in the same layer as the source / drain electrodes.

[0015]

In order to stabilize the potential of the counter electrode, it is necessary to reduce the capacitive coupling between the signal line and the counter electrode, which changes the largest at the same time. The area of the signal line cannot be made smaller than a certain value mainly due to the delay of the signal line and the reliability of the connection. In order to reduce the coupling capacitance while keeping the area of the signal line constant, it is effective to provide an electrode having a stable potential between the signal line and the counter electrode.

By arranging the signal line on the substrate side and the scanning line on this, the signal line is covered with the scanning line at the intersection of the signal line and the scanning line. This has the effect of reducing capacitive coupling with.

In order to realize this structure, the signal line and the gate electrode are formed in the same layer, the scanning line and the source / drain electrode are formed in the same layer, and the signal line and the drain electrode and the scanning line and the gate electrode are formed. This can be realized by connecting and using a contact hole.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 (a) is a plan view showing a first embodiment of the present invention, FIG. 1 (b) is a sectional view taken along the line AA 'in FIG. 1 (a),
FIG. 1C is a sectional view taken along the line BB ′ of FIG.

As shown in FIGS. 1 (a) to 1 (c), scanning lines 1 and signal lines 2 are arranged in a grid pattern on a translucent insulating substrate 7 such as a glass plate, and these scanning lines are arranged. Line 1 and signal line 2
Of the gate electrode 4 provided on the insulating substrate 7 near each intersection of
And a TFT array having an island-shaped amorphous silicon film 10 provided on the gate electrode 4 with an insulating film 8 interposed therebetween, and a source electrode 9 and a drain electrode 3 provided on the surface including the amorphous silicon film 10. Are configured. Here, the drain electrode 3 of the TFT is connected to the signal line 2 provided in the same layer as the gate electrode 4 through the contact hole 6 provided in the insulating film 8,
The gate electrode 4 is connected to the scanning line 1 provided in the same layer as the source electrode 9 and the drain electrode 3, and the source electrode 9 is connected to the pixel electrode 5 to form a TFT substrate.

2 (a) to 2 (c) are plan views showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 2A, a chromium film having a thickness of 150 nm is deposited on a translucent insulating substrate by a sputtering method and patterned, and an assumed virtual lattice line is formed on the insulating substrate. The signal line 2 and the gate electrode 4 arranged along the signal line 2 are formed on the signal line 14. Next, signal line 2
After depositing a silicon nitride film to be a gate insulating film to a thickness of 400 nm on the surface including the gate electrode 4 and a thickness of 3 nm.
50 nm non-doped amorphous silicon film and thickness 50
nm n-type amorphous silicon film is sequentially deposited and patterned to form an island-shaped amorphous silicon film 10 on the gate electrode 4.
To form.

Next, as shown in FIG. 2B, the silicon nitride film is selectively etched to form contact holes 6 on the signal lines 2 and the gate electrodes 4, and then on the surface including the contact holes 6. A chromium film is deposited and patterned to form each of the drain electrode 3 and the source electrode 9 connected to the signal line 2 through the contact hole 6. Next, an aluminium film is deposited on the entire surface, patterned, and laminated with the chromium film of the scanning line 1 to form a scanning line having a two-layer structure.

Next, as shown in FIG. 2C, the n-type amorphous silicon film on the channel region of the amorphous silicon film 10 is removed by plasma etching using the source electrode 9 and the drain electrode 3 as a mask. After selectively forming the pixel electrode 5 connected to the source electrode 9 with the ITO film, a silicon nitride film is deposited as a passivation film by the plasma CVD method to form a TFT substrate.

FIG. 3 is a plan view showing a second embodiment of the present invention.

As shown in FIG. 3, the scanning line 1 is formed by extending the scanning line 1 on the signal line 2 from the intersection of the scanning line 1 and the signal line 2 to the vicinity of the adjacent TFT. It has the same structure as that of the first embodiment except that most of it is covered, and has an advantage that the capacitive coupling between the signal line 2 and the counter electrode can be further suppressed.

[0027]

According to the present invention, by arranging the scanning lines on the signal lines provided on the insulating substrate, the signal lines are covered with the scanning lines at the intersections of the signal lines, so that the counter electrode is provided. The capacitive coupling between the signal line and the signal line can be reduced, and crosstalk can be suppressed.

[Brief description of drawings]

FIG. 1 is a plan view and A- showing a first embodiment of the present invention.
A sectional view taken along the line A ′ and a sectional view taken along the line BB ′.

2A to 2D are plan views showing the order of steps for explaining the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a second embodiment of the present invention.

FIG. 4 is a schematic diagram for explaining a problem of a liquid crystal display device using a conventional thin film field effect transistor array.

[Explanation of symbols]

 1 Scan Line 2 Signal Line 3 Drain Electrode 4 Gate Electrode 5 Pixel Electrode 6 Contact Hole 7 Insulating Substrate 8 Insulating Film 9 Source Electrode 10 Amorphous Silicon Film 11 Black Display 12 White Window Display 13 Crosstalk Phenomenon 14 Virtual Grid line

Claims (2)

[Claims] 1. A scanning line and a signal line which are arranged and crossed in a grid pattern on an insulating substrate, and are provided on the insulating substrate in the vicinity of intersections of the scanning line and the signal line and are connected to the scanning line. A gate electrode, an island-shaped semiconductor film provided on the gate electrode via a gate insulating film, and a source electrode (or drain electrode) provided on the semiconductor film and connected to the signal line
And a drain electrode (or source electrode) connected to the pixel electrode, the signal line is formed in the same layer as the gate electrode, and the scanning line is formed as the source / drain electrode. A thin film field effect transistor array, which is formed in the same layer. 2. The thin film field effect transistor array according to claim 1, wherein the scanning line extends from the intersection of the scanning line and the signal line and covers the signal line other than the vicinity of the thin film field effect transistor.