JPH06319221A - Operation type digital protection relay apparatus - Google Patents

Abstract

PURPOSE:To make it possible to judge the error in settling of a frequency in use. CONSTITUTION:An input waveform is sampled with a sampling frequency corresponding to the frequency of the waveform with a sample hold circuit 3, and the sample value is so stored into a RAM 11. The frequency of the input waveform is operated in a frequency operating part 31 by using the sample value. The agreement and the disagreement of the computed frequency and the frequency, which is settled with a settling panel 8, are compared and judged with a frequency judging part 32. When the error of the frequency settling occurs, the operated frequency does not agree with the settled frequency. Thus, the error can be found.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic type in which a relay is operated by converting a voltage / current or the like input from a power system to be protected into a digital signal and processing the digital signal. The present invention relates to a digital protective relay device, and more particularly to an arithmetic type digital protective relay device which is used by switching and setting a used frequency.

[0002]

2. Description of the Related Art FIG. 5 shows, for example, "Electric Cooperative Research Vol. 41, No. 4" (Japan Electric Cooperative Research Society, January 21, 1986).
FIG. 29 is a block diagram showing a conventional arithmetic type digital protective relay device described on page 29 of the Japanese issue).
1 is an input converter for converting the voltage / current of a plurality of channels input from a power system (not shown) to be protected into an appropriate voltage (about several volts), and 2 is obtained from the input converter 1. A filter 3 that removes high-frequency components such as noise from the voltage of each channel is a sample-hold circuit that samples and holds the output of the filter 2 at a sampling cycle determined according to the frequency of the power system.

Reference numeral 4 is a multiplexer for sequentially switching and outputting the output of each sample and hold circuit 3, 5 is an A / D converter for converting the output of the multiplexer 4 into a digital signal, and 6 is for temporarily holding the output of the A / D converter 5. The buffer memory 7 is a digital input interface to which a digital signal from the outside is input.

Reference numeral 8 is an operating value or a used frequency (for example, 50H).
z, 60 Hz), a settling panel in which an operator operates a switch to set the settling data, 9 is a settling interface for inputting operation values and operating frequencies set in the settling panel 8, 10 is a buffer memory 6, digital input interface 7 and a CPU that receives inputs from the settling interface 9 and the like and performs predetermined arithmetic processing, 11 is a CPU 1
A RAM for writing and reading data used for calculation of 0, and a ROM 12 for storing a calculation program and data necessary for calculation.

Reference numeral 13 is a digital output interface for outputting the calculation result of the CPU 10 to the outside, 14 is a relay operated by the output of the digital output interface 13, and 15 is a bus line for transmitting data used for the calculation processing.

Next, the operation will be described. Inputs such as voltage and current input from the power system to be protected are converted into appropriate voltages by the input converter 1, and then high-frequency components such as noise are removed by the filter 2. The output of the filter 2 is applied to the sample and hold circuit 3, where it is sampled and held at a predetermined sampling cycle determined according to the frequency of the power system (for example, 50 Hz, 60 Hz). In this case, the sample and hold circuits 3 of the respective channels are operated in synchronization with each other, and are controlled by the sampling control circuit described later so as to sample the instantaneous value of the input at the same time.

The sample value of the sample and hold circuit 3 is switched by the multiplexer 4 for each channel and A /
It is added to the D converter 5 and converted into a digital signal. This digital signal is temporarily stored in the buffer memory 6 and held until it is read from the CPU 10. C
When the previous arithmetic processing is completed, the PU 10 sequentially reads the data in the buffer memory 6 and stores the sample values of the respective channels at the same time in the RAM 11.

The CPU 10 executes digital filter calculation, peak value calculation, frequency calculation, etc. using the sample values of each channel stored in the RAM 11 at the same time. The operating value and the operating frequency (50 Hz or 60 Hz) input from the setting panel 8 through the setting interface 9 are set.
It is determined whether or not the relay 14 is operated by comparing the settling data such as Hz) with the above calculation result. When the relay 14 is operated, the relay 14 is operated by outputting the instruction signal via the digital output interface 13.

Next, the sampling control circuit will be described. Sampling in the sample hold circuit 3 is determined by the protection method of the protective relay, the calculation principle, etc., but generally 12 times for one cycle of the frequency of the power system to be protected, that is, the electrical angle is 30 °. It is customary to sample every time.

When the sampling period is set to an electrical angle of 30 °, a 1.67 ms interval (600 Hz) in the 50 Hz system,
In the 60 Hz system, the sampling cycle is 1.39 ms (720 Hz). Since the sampling cycle is different between the 50 Hz system and the 60 Hz system, a sampling control circuit as shown in FIG. 6 is used. The settling panel 8, the settling interface 9 and the sample hold circuit 3 in FIG. 6 are the same as those in FIG.

In FIG. 6, reference numeral 21 is a frequency settling storage section for storing the used frequency set by the settling panel 8 via the settling interface 9, and 22 is a sampling for the sample and hold circuit 3 according to the stored frequency. It is a sampling signal generator that outputs a signal.

Next, the operation will be described. Now 50
If used in the Hz system, the setting panel 8 to 50
The settling data indicating Hz is stored in the frequency settling storage unit 21 via the settling interface 9. On the basis of the stored settling data, the sampling signal generating section 22
A sampling signal instructing sampling at 39 ms intervals (720 Hz) is applied to the sample hold circuit 3.

[0013]

Since the conventional arithmetic type digital protective relay device is constructed as described above, a set operating frequency and an operating frequency set by an erroneous operation of the setting panel 8 are generated.
When the frequency of the protected power system is different. For example, when the one used in the 50 Hz system is settled to 60 Hz, the one that must be sampled at an electrical angle of 30 ° results in sampling at an electrical angle of 25 °, and various values are used by using the sampled values. When the calculation is executed, there is a problem that the calculation result may be greatly deviated and the protective relay may malfunction.

The invention of claim 1 has been made to solve the above problems, and it is possible to determine whether or not the frequency of the power system and the arbitrarily set frequency coincide with each other. The purpose of the invention is to obtain a protective relay for arithmetic digital.

According to the second and third aspects of the present invention, it is possible to determine whether or not the frequency of the power system matches the arbitrarily set frequency, and at the same time, reduce the processing of the CPU and the capacity of the ROM. It is an object to obtain an arithmetic type digital protective relay device capable of performing.

[0016]

According to a first aspect of the present invention, there is provided a calculation type digital protective relay device which is provided with a frequency calculation section for calculating a frequency of an input waveform using stored sample value data. The frequency is compared with the set frequency.

According to another aspect of the present invention, there is provided an arithmetic digital protective relay device which uses stored sample value data and calculates a crest value of an input waveform for each sampling frequency by a calculation formula in which an amplification factor changes according to a frequency. Is provided with the peak value calculating means, the peak values are compared with each other to obtain the frequency, and the frequency is compared with the set frequency.

According to another aspect of the present invention, there is provided an arithmetic digital protective relay device, which uses stored sample value data and uses a calculation formula that causes a variation in a calculation result depending on a frequency, to calculate a variation amount of a crest value of an input waveform. Is provided for each sampling frequency to calculate the peak value variation amount, compare the variation values of the peak values to obtain the frequency, and compare with the set frequency.

[0019]

According to the first aspect of the digital protective relay device of the present invention, when an erroneous frequency is settled, when the frequency calculation is performed using the sampled value data, the calculated frequency is the settling frequency. Therefore, it is determined that there is an error in settling.

In the digital protective relay device of the second aspect of the present invention, the crest value is different for each sampling frequency. Therefore, the frequency of the normal input waveform is obtained by comparing the crest values and settling with this. By comparing with the frequency, the settling error can be determined.

In the arithmetic type digital protective relay device according to the third aspect of the present invention, the variation amount of the crest value is different for each sampling frequency. Therefore, the frequency of the normal input waveform is obtained by comparing the variation amounts. By comparing this with the settled frequency, the settling error can be determined.

[0022]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. In FIG. 1, parts corresponding to those in FIGS. 5 and 6 are designated by the same reference numerals, and overlapping description will be omitted. In FIG. 1, 31 is a frequency calculation unit that calculates the frequency of the power system by using the sampled value data stored in the RAM 11, 32 is the frequency calculated by the frequency calculation unit 31 and is stored and set in the frequency setting storage unit 21. And a reference numeral 33 is an external output unit that outputs the determination result of the frequency determination unit 32 to the outside. The RAM 11 is a sample value storage unit. Further, the settling panel 8 and the settling interface 9 constitute settling means.

Next, the operation will be described. The frequency calculation unit 31 calculates the frequency of the power system by using the sample value data stored in the RAM 11 (sample value storage unit). Calculation for obtaining this frequency is shown in FIG. 4 and Table 1.
This will be described using the specific example shown in.

[0024]

[Table 1]

FIG. 4 shows the position of each sample value in the waveform of voltage and current (hereinafter referred to as input waveform) input from the power system.
In other words, the figure shows the case of sampling 12 times for one cycle of the input waveform. In FIG. 4, T is a sampling period, T ₀ is an input waveform period, and f is an input waveform frequency.

Further, the current sample value is v (t),
The sample value one sampling period (T) before is v (t
-T), the sample value before 2 sampling periods (2T) is expressed as v (t-2T), and the sample value before 3 sampling periods (3T) is expressed as v (t-3T) ....

Table 1 shows sample values v (t) and v (t in FIG.
-2T), v (t-3T) ... Here, 50 Hz is set as an actual input waveform, each sample value sampled at a correct sampling frequency (hereinafter, indicated by f _s ) is shown when the maximum peak value V _{pp is set} to 1 V, and the input waveform is erroneously set to 60.
Each sample value when sampling is performed at a sampling frequency f _s (= 720 Hz) of the Hz system is shown.

Next, an example of calculating each sample value will be described. When v (t) = 0 is the current sample value when sampling is performed at the regular sampling frequency of 600 Hz, and t is 0, for example, v (t−3T) is calculated as follows. v (t-3T) = _Vpp * sin (-3 * 30 [deg.]) = 1 * sin (-90 [deg.]) =-1 [V]

Further, v (t-3T) when erroneously sampled at f _s = 720 Hz is as follows. v (t-3T) = V pp × sin (-3 × 24 °) = 1 × sin (-72 °) = -0.951 [V], and the sample value at the same time by the sampling frequency are different I understand. Other v (t-T), v (t
--2T), v (t-4T) ... Similarly to the above, from the current sample value v (t) to (-T), (-2
T), (-4T).

Also in the case after one sampling period, v (t) may be (+ T), that is, f _s = 60.
In the case of 0 Hz, v (t + T) = V _pp × sin (+ 30 °) = 1 × sin 30 ° = 0.5 [V] f _s = In the case of 720 Hz, v (t + T) = V _pp × sin (+ 24 °) = 1 × sin24 ° = 0.407 [V].

Next, as an example of the arithmetic operation performed in the frequency arithmetic unit 31, Equation 1 described on page 43 of the above-mentioned "Electrical Cooperation Research" is used.

[0032]

[Equation 1]

Using the above equation 1, a regular 50 Hz system (f _s
= 600 Hz), T ₀ = 2 × 1/600 × [(0 / (0.5 + 0)) + 5
+ 0.5 / 0.5] = 0.02 (second) ∴f = 1 / T ₀ = 50 (Hz). Also, if sampled at f _s = 720 Hz for 60Hz systems _{accidentally, T 0 = 2 × 1/} 720 × [(0.588 / (0.208
+0.588)) +5+ (0.407 / (0.407+
0))] = 0.1797 (seconds) ∴f = 1 / 0.1797 = 55.65 (Hz).

On the other hand, the frequency settling storage section 21 stores 50 Hz if the operating frequency settling by the settling panel 8 is set correctly, and 60 Hz if it is set incorrectly. Therefore, when the actual input waveform frequency f is 50 Hz and it is erroneously settled at 60 Hz, the frequency calculation unit 31 adds 55.65 Hz to the frequency determination unit 32 as the calculation result. Further, the frequency settling storage unit 21 adds the erroneously settled 60 Hz to the frequency determination unit 32. Therefore, the frequency determination unit 32 determines that the two inputs do not match and outputs the determination result through the external output unit 33. As a result, it is possible to display that the frequency setting is incorrect by a buzzer, a lamp or the like.

Further, if the frequency is correctly settled at 50 Hz, the two inputs of the frequency determination unit 32 will match.
Therefore, it may be displayed when it is set by mistake,
You may make it display, when it is settled correctly.
Alternatively, both cases may be displayed separately.

Example 2. Next, an embodiment of the invention of claim 2 will be described. In the above-described first embodiment, the method of calculating the frequency of the input waveform has been described. However, in this method, when the protection relay determines the operation only based on the size of the input waveform, for example, in the case of an overvoltage detection relay or the like, it is related to the operation determination. It is necessary to perform a frequency calculation that does not exist, which may waste the processing time of the CPU and the ROM capacity.

In the second embodiment, the calculation formula of the crest value calculation for obtaining the magnitude of the input waveform, which is performed in most protection relays, is used, and the sample value obtained at the regular sampling frequency is used for the input waveform. By determining whether the frequency is 50 Hz or 60 Hz from the difference in magnitude between the peak value calculation result calculated by the above and the peak value calculation result calculated using the sample value obtained at an incorrect sampling frequency, This is a method for performing efficient processing, which will be described below with reference to FIG. In FIG. 2, portions corresponding to those in FIG.

In FIG. 2, reference numeral 41 is a peak value calculating section for calculating the peak value from the data of the RAM 11 by using a calculation formula in which the amplification degree changes according to the input waveform frequency f, and 42 is the frequency settling storage section 21 for the sampling frequency f _s. Sampling frequency switching unit for switching regardless of the data, and 43 is a peak value comparison and determination unit for comparing the peak values calculated for each sampling frequency, and adds the determination result to the frequency determination unit 32.
The peak value calculation unit 41 and the sampling frequency switching unit 4
2 and crest value calculating means are configured.

Next, the operation will be described. The sampled value data of the input waveform stored in the RAM 11 is added to the peak value calculation unit 41 using a calculation formula in which the amplification degree of the calculation changes according to the frequency of the input waveform, and the peak value is obtained. As a specific example of this peak value calculation, the applicant of the present invention (case number AP-X
8832) V ² (t) = v (t−2T) × v (t−3T) −v (t) × v (t−5T) shown in “arithmetic digital relay” …………………… A calculation example using (2) will be described with reference to FIG. 4 and Table 1.

For example, when the frequency settling is set to a normal 50 Hz (f _s = 600 Hz) with an input waveform of 50 Hz, the calculated values at the present time and after one sampling period are V ² (t) = (- 0.866) x (-1) -0 x (-
0.5) = 0.866 [V] Even after one sampling period, V ² (t) = (− 0.5) × (−0.866) −0.5 × (−0.866) = 0. 866 [V] and the calculation result V ² (t) are 0.866 [V], and there is no variation in the calculation result for each sampling period.

Next, the frequency setting is erroneously performed at 60 Hz (f _s
= 750 Hz), the same calculated value as above is V ² (t) = (− 0.743) × (−0.951) −0 × (−0.866) = 0.707 [ V] Even after one sampling cycle, V ² (t) = (− 0.407) × (−0.743) −0.407 × (−0.995) = 0.707 [V] The calculation result of is the regular frequency 5
As in the case of 0 Hz, there is no variation, but the value is small, and it can be seen that the amplification factor of the crest value calculation changes depending on the frequency.

Next, if the frequency other than the frequency arbitrarily selected from the outside by the setting panel 8 is set to 50 Hz, for example, the sampling frequency switching section 42.
To switch to 60 Hz (f _s = 720). Then, the crest value calculation is executed again to obtain the crest value data at 50 Hz and 60 Hz, and then the original sampling frequency (600 Hz) is restored.

The magnitude comparison of the crest value data in the two frequency settings thus obtained is performed by the crest value comparison / determination unit 43, and the frequency at which a large crest value is obtained is determined to be a normal frequency and the frequency is determined. It outputs to the determination unit 32. The frequency determination unit 32 compares the data with the data in the frequency settling storage unit 21, and determines that the settling is correct if the two match, and determines that the setting is incorrect if the two do not match.

According to the second embodiment, in addition to the effect of the first embodiment, it is possible to reduce waste of CPU processing time, ROM capacity, etc. for a model that does not require frequency calculation in detecting the protective relay. it can.

Example 3. Next, an embodiment of the invention of claim 3 will be described. In the second embodiment, the calculation formula in which the amplification degree changes according to the frequency of the input waveform is used for the peak value calculation.
This cannot be applied when the calculation results for each sampling period vary. The third embodiment is a method of calculating the variation amount of the calculation result for each sampling period based on the frequency of the input waveform and obtaining the frequency with the smaller variation amount, which will be described below with reference to FIG. In FIG. 3, FIG.
The parts corresponding to are given the same reference numerals and the description thereof will be omitted.

In FIG. 3, reference numeral 50 is a peak value calculator for calculating peak values from the data in the RAM 11 by using a calculation formula in which the calculation results for each sampling cycle vary depending on the frequency of the input waveform, and 51 is the calculated peak value. The reference value 52 is a crest value variation comparison unit that compares and determines the calculated variation amount at each frequency, and adds the determination result to the frequency determination unit 32.
The peak value calculator 50 and the peak value variation amount calculator 51
The sampling frequency switching unit 42 constitutes a crest value variation amount calculating means.

Next, the operation will be described. The sampled value data of the input waveform stored in the RAM 11 is added to the peak value calculation unit 50 that uses a calculation formula in which the calculation result for each sampling period varies depending on the frequency of the input waveform, and the peak value is obtained. As a concrete example of this crest value calculation, the calculation formula described on page 44 of “Electrical Cooperation Research” V ² (t) = v ² (t) + v ² (t−3T) ………………………… A calculation example using (3) will be described with reference to FIG. 4 and Table 1.

For example, with an input waveform of 50 Hz, when the frequency settling is set to normal 50 Hz (f _s 600 Hz), the current value and the calculated value after one sampling period are V ² (t) = 0 ² + (-1 ) ² = 1 [V] Even after one sampling period, V ² (t) = (0.5) ² + (− 0.866) ² ≈1
[V] and the calculation result V ² (t) are 1 V, and there is no variation in the calculation result for each sampling period.

Next, when the frequency setting is erroneously set to 60 Hz (sampling frequency 750 Hz), the same calculated value as above is V ² (t) = 0 ² + (− 0.951) ² ≈0. 904
[V] After one sampling period, V ² (t) = (0.407) ² + (− 0.743) ² ≈
The calculation result V ² (t) is 0.718 [V], and the calculation result for each sampling period is different from that in the normal frequency settling.

The crest value variation amount calculation unit 51 calculates the difference between the crest value calculation result and the crest value calculation result after the next sampling period to obtain the variation amount. As a specific example, when the current peak value calculation result is V ₁ ² (t) and the peak value calculation result after one sampling period is V ₂ ² (t), the variation amount ΔV ² is ΔV ² = V ₁ ² (t ) -V ₂ ² (t).

Taking a calculation example, the peak value calculation result shown in the second embodiment is taken as an example, and a normal value of 5 is obtained with a 50 Hz input waveform.
At the time of 0 Hz settling, V ₁ ² (t) = 1 [V], V ₂ ² (t)
Since = 1 [V], ΔV ² is 0 [V], but by mistake, 60
If the Hz ^{_{settling, V 1 2 (t) =}} 0.904 [V],
From V ₂ ² (t) = 0.718 [V], ΔV ² is 0.1
The variation amount can be calculated as 86 [V].

Further, the sampling frequency switching unit 42 obtains variations of 50 Hz and 60 Hz, respectively. Next, the peak value variation comparison determination unit 52 causes 50 Hz
At the time of 60 Hz, the smaller frequency of the variation amount calculation result is determined to be a normal frequency and output to the frequency determination unit 32.

According to this embodiment, the same effect as that of the second embodiment is obtained, and there is an advantage that it can be used in the case of the crest value calculation algorithm in which the calculation result for each sampling period varies depending on the frequency of the input waveform.

[0054]

As described above, according to the first aspect of the present invention, the frequency of the input waveform is calculated from the stored sampling value data, and the frequency and the settling frequency are compared and determined. Therefore, there is an effect that it is possible to surely determine the frequency setting error and prevent the malfunction of the protective relay due to the setting error.

According to the second aspect of the present invention, the stored sample value data is used to calculate the crest value for each sampling frequency according to a calculation formula in which the amplification factor changes depending on the frequency, and the calculated crest values are compared. To find the frequency,
Since it is configured to make a comparison judgment with the settling frequency,
It is possible to reliably determine an error in frequency setting, prevent a malfunction of the protective relay due to an error in setting, and reduce CPU processing and ROM capacity.

According to the third aspect of the present invention, the peak value is calculated for each sampling frequency by using the stored sample value data and the calculation formula that causes the dispersion of the calculation result depending on the frequency, and the variation amount of each calculated peak value. Since it is configured to determine the frequency by comparing with the settling frequency, it is possible to reliably determine the error in the frequency settling, and prevent the malfunction of the protective relay due to the setting error in advance. At the same time, there is an effect that the processing of the CPU and the capacity of the ROM can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an arithmetic digital protection relay device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an arithmetic digital protection relay device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing an arithmetic digital protection relay device according to an embodiment of the present invention.

FIG. 4 is a waveform diagram showing how an input waveform is sampled.

FIG. 5 is a block diagram showing a conventional arithmetic digital protection relay device.

FIG. 6 is a block diagram showing a sampling control circuit of the device.

[Explanation of symbols]

3 Sample and Hold Circuit 8 Settling Panel (Settling Means) 9 Settling Interface (Settling Means) 11 RAM (Sample Value Storage Section) 31 Frequency Calculation Section 32 Frequency Judgment Section 41 Crest Value Calculation Section (Crest Value Calculation Section) 42 Sampling Frequency Switching Section (Peak value calculation means, peak value variation amount calculation means) 43 Crest value comparison / determination section 50 Crest value calculation section (peak value variation amount calculation means) 51 Crest value variation amount calculation section (peak value variation amount calculation means) 52 Crest value Variation comparison judgment unit

Claims (3)

[Claims] 1. A settling means for setting and inputting a used frequency, a sample hold circuit for sampling an input waveform at a sampling frequency determined according to the frequency settled by the settling means, and a sample value of the sample hold circuit. , A frequency value calculating section for obtaining the frequency of the input waveform by using the sample value data stored in the sample value storing section, the frequency calculated by the frequency calculating section and the settling means. An arithmetic type digital protective relay device having a frequency judging unit for judging whether or not the frequency settled in step 3 is matched. 2. A settling means for setting and inputting a used frequency, a sample hold circuit for sampling an input waveform at a sampling frequency determined according to the frequency settled by the settling means, and a sample value of the sample hold circuit. By using a sample value storage unit that sequentially stores the sample value data stored in the sample value storage unit and a calculation formula in which the amplification degree changes according to the frequency of the input waveform, for each of a plurality of different sampling frequencies. The peak value calculating means for calculating the peak value of the input waveform is compared with a plurality of peak values found by the peak value calculating means, and the frequency corresponding to the sampling frequency at which the peak value is larger or smaller is output. And a matching / unmatch between the frequency determined by the peak value comparison / determination unit and the frequency set by the settling means. An arithmetic type digital protective relay device having a frequency judging unit for judging whether or not there is a match. 3. A settling means for setting and inputting a used frequency, a sample hold circuit for sampling an input waveform at a sampling frequency determined according to the frequency settled by the settling means, and a sample value of the sample hold circuit. And a sample value storage unit that sequentially stores the sample value data stored in the sample value storage unit, and a calculation formula that causes variations in the calculation result depending on the frequency of the input waveform. A person who obtains a large or small variation amount by comparing the variation amount of the peak value variation amount calculating means for performing the calculation for obtaining the variation amount of the crest value of the waveform with the variation amount of the plurality of peak values obtained by the above-mentioned variation value of the crest value A crest value variation comparison determination unit that outputs a frequency corresponding to the sampling frequency of
An arithmetic type digital protective relay device comprising: a frequency determination unit that determines whether or not the frequency obtained by the peak value variation comparison and determination unit and the frequency set by the setting unit are coincident or not.