SU680057A1 - Analog memory - Google Patents

Description

The invention relates to the field of digital and computer technology and can be used in monitoring and measuring systems for various purposes. A memory device containing a comparator, a key, is charged with a discharge circuit with a storage capacity, which is capable of storing instantaneous values of a function at a given moment in time I1. It is also known an analog storage device containing a main storage element, for example, a capacitor, one of the plates of which is connected to a parallel key connected in parallel to the first key and a non-linear element, as well as to one of the comparator inputs, a capacitor plate connected to another input signal and bus signal error 2. However, the storage devices described, have limited capabilities, do not allow for the implementation of effective methods for eliminating redundancy in input circuits of instrumentation and telemetry devices. To eliminate redundancy, when representing controlled processes with parameters of approximating polynomials, the smallest amount of data is provided if the best approximation polynomial parameters are transmitted. The aim of the invention is to expand the field of application of the device by storing the zero-order signals extracted from the polynomial. To do this, delayed elements, adders, an auxiliary accumulation element, such as a capacitor, keys, a second nonlinear element and a fixing element connected to the device output and through a second key to one of the comparator inputs, the other input of which is connected to one of the auxiliary the capacitor and with the third key connected in parallel and the second nonlinear element, the comparator output is connected to the control input of the second key and through the delay element to the control inputs of the first and the third key, the outputs of the adders are connected to the first key connected in parallel and the first nonlinear; Element and to the pair.

the third key and the second nonlinear element respectively, the input signal bus is connected to one of the inputs of the adders, the other inputs of which are connected to the signal busses from the jack, respectively.

FIG. 1 shows the proposed device, the functional diagram of FIG. 2 - time diagram.

The device contains adders 1 and 2, keys 3 and 4, nonlinear elements 5 and 6, the main and auxiliary elements 7 and 8, the delay element 9, the comparator 10, the key 11, the locking element 12, the input signal bus 13, the error signal bus 14, bus 15 signal oybki, locking element 12 is made on the capacitor.

Diodes are used as nonlinear elements 5. and 6, and capacitors are used as storage elements 7 and 8.

The signal is approximated by a step polynomial, best approximation with some allowable error Vf ,. To determine the coordinates of the ends of the segments; a polynomial forms a so-called error corridor, equal to 2vf, and narrowing to zero at the reference point. The current values of the upper boundary of the corridor are equal to the minimum value of V (t) + + Vf in the interval t, t, and the lower limit is equal to the maximum value of Vc (t) - v in the same interval. Thus, at the initial time t of operation, the values of the upper and lower boundaries of the error corridor are Vc (t) + v and Vj. () -Vj ,. As the signal changes, new values of the boundaries of the corridor are formed. At the time of their coincidence. the value of) + Vf, or Vj. (t) - v is the ordinate, and is the base of the end of a segment of the best-approximation polynomial of order 1 in the interval It, t.

The proposed device works as follows.

From input 13, the input signal in analog form is fed to the inputs of adders 1 and 2, which are also supplied with error voltages + v, to adder 1, –y to adder 2. At the output, sum-5ators 1, 2. signals corresponding to v (t) are generated

 yj. (t) -) Vc, (t) + Vf ,.

At the initial moment t. switches 3 and 4 are open and capacitors 7 and 8 are charged to voltages Vc7 (t) v (t), (t) VgCt). After this, the keys 3, 4 are closed. If the output value of adder 1 is the current value of v (t) 7 (t), then the capacitor 7 through the nonlinear element 5 is charged to the value v (t) and Vf-f (t) v (t) if v (t) i Vg (t), TO Vg (t) does not change.

If the output of the adder 2 is the current value of Vg (t) (t), then the capacitor 8 is through a nonlinear element;

6 is discharged to the value of V2 (t) and Vce (t) Vgtt) if VjCt) -y / Vce (t), TO Vj, g (t) does not change.

The current voltages (t) and Vpg (t) are compared to the comparator 10. At the same time the voltage on the capacitors 7, 8, the comparator 10 is activated, the key 11 is opened, and the fixing element 12 remembers the ordinate value of the best approximation polynomial at the interval t, t . The input signal of the comparator 10 through the delay element 9 opens the keys 3 and 4, the capacitors

7 and 8 are charged to v (t ..) and V2 (), the process is repeated from the beginning.

Thus, the proposed storage device allows the selection and storage of the parameters of the best order zero order polynomial.

Using this device at the input of angular-to-digital converters allows for adaptive sampling of the signal, while significantly reducing the amount of data necessary for the subsequent reconstruction of the signal with a given accuracy. In addition, in the absence of a latch at the output of the device, it can be used independently as an adaptive sampler.

Claims (2)

Invention Formula An analog storage device containing a main storage element, for example, a capacitor, one of the plates of which is connected to the first key and the first nonlinear element connected in parallel, as well as to one of the comparator inputs, the other capacitor plate is connected to the zero potential bus, the input signal bus and error signals, characterized in that, in order to expand the field of application of the device by storing the zero-order signals extracted from the polynomial, rzhki, adders, auxiliary storage element, such as a capacitor, keys, a second nonlinear element and a locking element connected to the output of the device and through the second key to one of the inputs of the comparator, the other input of which is connected to one of the plates of the auxiliary capacitor and with a third connected in parallel the key and the second nonlinear element, the output of the comparator is connected to the control input of the second key and through the delay element to the control inputs of the first and third keys, the outputs of the sumers Connected to the first key and the first nonlinear element connected in parallel and to the third key and the second nonlinear element connected in parallel, respectively; the input signal bus is connected to one of the inputs sum 800576 tori, the other inputs of which.x are connected to the error signal buses, respectively. Sources of information taken into account during the examination 5 1. USSR author's certificate No. 394855, cl. G 11 C 27/00, 1973. 2. USSR author's certificate 354421, cl. G 11 C 27/00, 1972. -ABOUT, Riga.1 ig.2