JPH06318934A - Burst clock reproducing circuit - Google Patents

Abstract

PURPOSE:To improve transmission efficiency by canceling a DC component in a short time, performing unipolar/bipolar conversion and shortening a preamble length added to a burst signal by using this circuit for the burst multiplex transmission/reception circuit of a PDS(passive double star) system. CONSTITUTION:By providing a phase circuit 3 to apply phase transition to a received signal and calculating difference between the received signal and a phaser output signal by using a differential amplifier 4, a bipolar signal canceled the DC component is provided. Concerning the bipolar signal, a forward pulse is identified by a first comparator 5, a backward pulse is identified by a second comparator 6, the outputs of both the comparators 5 and 6 are ORed by an OR circuit 7, and a double frequency component is provided. The output of the OR circuit 7 is inputted to a tank circuit 8, and continuous clock components are extracted from the output.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a PDS (Passive Doub)
The present invention relates to a receiving circuit in a burst multiplex transmission system such as a le Star) system, and particularly to a burst clock reproducing circuit for reproducing a clock.

[0002]

2. Description of the Related Art The PDS transmission system shown in FIG. 3 is one system that constitutes an optical subscriber system, and is an SLT (Subs)
O installed from the criber line terminal)
A multiplexing node such as a star coupler is provided on the way to the NU (Optical Network Unit) to connect a plurality of ONUs and SLTs. A plurality of ONUs share the same optical fiber between the SLT and the multiplexing node. As shown in FIG. 3, the signal from the SLT to the ONU is transmitted in a broadcast form as a time division multiplexed signal.

On the other hand, a burst signal is transmitted from the ONU to the SLT, and at the SLT receiving point, the burst signals from a plurality of ONUs are aligned so as not to overlap each other. Therefore, the ONU controls and transmits its own burst transmission timing so as not to collide with burst signals from other ONUs at the SLT reception point. Further, a preamble as shown in FIG. 4 is added to the signal from the ONU to the SLT to identify the start position of the burst, and in addition to controlling the burst transmission timing, a guard time is provided in order to prevent collision of each burst. Has been. Since the PDS transmission method is a transmission method using light, signal transmission from the ONU and SLT is performed using a light emitting element such as an LD (Laser Diode). A scrambled NRZ code is used as the transmission code from the viewpoint of transmission efficiency.

On the other hand, on the receiving side (SLT), PD (Photo
A light receiving element such as a diode) performs optical / electrical conversion to obtain an electric signal, and an amplifier amplifies it to a level required for subsequent processing. At present, between the optical element and the amplifier, there is no choice but to couple them with a capacitor, because the DC drift of the light receiving element is large, and if they are directly connected, the operating point of the amplifier exceeds the allowable range. Therefore, the zero potential point of the amplifier output waveform varies depending on the number of multiplexed burst signals and the amplitude.

[0005]

The received waveform at the SLT is as shown in FIG. 4, where the A section shows the case where the distance to the ONU is short, and the B section shows the case where the distance to the ONU is long. In order to reproduce the clock component from this signal waveform, first a double frequency signal is generated from the signal, and then a continuous clock signal is extracted by the tank circuit. Since it is burst transmission, the circuit must be constructed so that the phase of the recovered clock is stable within an extremely short time after the arrival of the burst.

Specifically, it is necessary to detect the average DC component of each burst from the DC blocked unipolar burst signal (FIG. 4) and convert it to a bipolar burst signal by means such as subtracting it from the received burst signal. There is. The reason is that the difference in the amplitude of each burst signal is 30 dB to 40 dB depending on the distance to the ONU, and in order to process the unipolar signal with the DC cut off, the dynamic range of the amplifier used must be extremely widened. For example, if the minimum level signal is amplified to 1V, the maximum level signal becomes 30 to 100V, and 30 to 100V is also required as the saturation point of the amplifier. If saturation occurs in the amplifier, the minimum level signal disappears with a limiter applied (FIG. 5 (a)). In contrast,
If it can be converted into a bipolar signal, the saturation point of the amplifier should be able to output a minimum level signal. The signal of the maximum level is naturally subject to a large amplitude limitation, but the information near the zero crossing of the waveform is not lost, so there is no problem in clock extraction (FIG. 5 (b)).

Next, there is a method of using a full-wave rectification circuit for generating the double frequency, but it is difficult to apply it to a high-speed transmission system because it requires a transformer, and it is not suitable for IC. Therefore, it is desired to mainly configure the semiconductor. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a burst clock recovery circuit that extracts a clock from a burst signal that includes a DC component and has a different amplitude for each ONU. To do.

[0008]

In order to solve the above-mentioned problems, in the burst clock recovery circuit of the present invention, a phase circuit for giving a predetermined phase transition to the received signal is provided, and the received signal is converted by the differential amplifier. By taking the difference between the phaser output signals, a bipolar signal in which the DC component is canceled is obtained. The first comparator identifies the positive-going pulse of the bipolar signal, the second comparator identifies the negative-going pulse, and the OR circuit ORs both comparators to obtain a double frequency component. The output of the OR circuit is input to the tank circuit, and continuous clock components are extracted from the output.

[0009]

According to the burst clock regenerating circuit configured as described above, it becomes possible to cancel the DC component in a short time and perform unipolar / bipolar conversion, and shorten the preamble length added to the burst signal to improve the transmission efficiency. Can be done.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram, and FIG. 2 shows the time chart. The NRZ burst signal a, which is the output of the optical receiver 1, is blocked by the capacitor 2 for direct current and becomes a signal b. The signal b is input to the phase circuit 3, and a signal c whose phase has shifted by a predetermined amount is obtained from the output. The differential amplifier 4 receives the signal b and the signal c at its inputs, and extracts the bipolar signals d and e from which the DC components have been canceled out. The signal d is a positive phase output, and the signal e is a negative phase output. The signal d is connected to the positive phase input of the first comparator 5 and the negative phase input of the second comparator 6, and the signal e is connected to the negative phase input of the first comparator 5 and the second phase input.
Is connected to the positive phase input of the comparator 6.

As a result, the signal f which identifies the positive polarity pulse in the signal d appears at the output of the first comparator 5, and the second
At the output of the comparator 6, the signal g that identifies the negative polarity pulse in the signal d appears. The signal g and the signal f are respectively input to the OR circuit 7, and the double frequency signal h obtained by combining the signals g and f is taken out from the output thereof. Since the signal h is in a state where the pulse is interrupted when "0" or "1" is continuous as transmission information, it cannot be used as a reproduction clock as it is. Therefore, the signal h is input to the tank circuit 8 and the clock frequency signal i continuous from its output
To get The third comparator 9 converts the clock frequency signal i into a signal j having a predetermined level, for example, a TTL level. Although the tank circuit 8 is used in this embodiment, it is not limited to this. That is, any means may be used as long as it can convert the signal h into a continuous clock frequency signal i.
It can also be realized by using a circuit or the like.

[0012]

As described above, according to the present invention, the difference between the received signal and the phase-shifted received signal is obtained, and then the double frequency is obtained by the comparator having the positive and negative threshold values, and the tank circuit is obtained. The continuous clock is extracted by. Therefore, processing such as direct current regeneration, unipolar / bipolar conversion, and double frequency division can be realized with an extremely simple configuration. Further, a double frequency signal in which the direct current component is canceled can be obtained in an extremely short time. As a result, the preamble length added to the burst signal can be shortened and the transmission efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the waveform of each point in the embodiment of FIG.

FIG. 3 is a configuration diagram showing an outline of a PDS system.

FIG. 4 is a waveform diagram of a received burst signal output from a PDS optical receiver.

5A shows an operation example when a unipolar burst signal is amplified, and FIG. 5B shows an operation example when a bipolar burst signal is amplified.

[Explanation of symbols]

 Three-phase circuit. 4 Differential amplifier. 5 First comparator. 6 Second comparator. 7 OR circuit. 8 tank circuit.

Claims (1)

[Claims] 1. A phase circuit (3) for giving a predetermined phase transition to a received signal, an output of the phase circuit, and a signal in which a DC component is canceled by receiving the received signal at each input terminal. A differential amplifier (4), a first comparator (5) to which an output of the differential amplifier is connected to its input terminal and which discriminates and outputs a positive polarity signal, and an output of the differential amplifier, A second comparator (6) connected to the input terminal for discriminating and outputting the negative signal, and receiving the outputs of the first and second comparators and receiving a pulse interval of half of the received signal. A burst clock recovery circuit comprising an OR circuit (7) for outputting a signal and a tank circuit (8) connected to the output of the OR circuit for extracting a continuous clock signal.