JPH06318908A - Burst signal detecting circuit - Google Patents

Burst signal detecting circuit

Info

Publication number
JPH06318908A
JPH06318908A JP5132682A JP13268293A JPH06318908A JP H06318908 A JPH06318908 A JP H06318908A JP 5132682 A JP5132682 A JP 5132682A JP 13268293 A JP13268293 A JP 13268293A JP H06318908 A JPH06318908 A JP H06318908A
Authority
JP
Japan
Prior art keywords
signal
burst
circuit
output
burst signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5132682A
Other languages
Japanese (ja)
Inventor
Ko Okubo
皎 大窪
Shinichi Aoyanagi
愼一 青柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Anritsu Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp, Nippon Telegraph and Telephone Corp filed Critical Anritsu Corp
Priority to JP5132682A priority Critical patent/JPH06318908A/en
Publication of JPH06318908A publication Critical patent/JPH06318908A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

PURPOSE:To detect the arrival of a burst signal with a different amplitude for each ONU(optical network unit) provided with a DC component in the burst multiplex transmission system of a PDS(passive double star) system in a short time. CONSTITUTION:An NRZ burst signal (a) outputted from an optical receiver 1 is turned to a signal (b) by performing DC cut-off at a capacitor 2. By providing a phase circuit 3 to apply phase transition to the signal (b) and calculating difference between the signal (b) and a phaser output signal (c) by using a differential amplifier 4, a bipolar signal (d) canceled the DC component is provided. A counter circuit 8 is operated by the bipolar signal (a) and after the prescribed number of pulses are counted, a burst detect signal (k) is outputted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、PDS(Passive Doub
le Star )方式等のバースト多重伝送系における受信回
路、特にバースト信号の到着を検出するバースト信号検
出回路に関する。
The present invention relates to a PDS (Passive Doub)
The present invention relates to a receiving circuit in a burst multiplex transmission system such as a le Star) system, and particularly to a burst signal detecting circuit for detecting arrival of a burst signal.

【0002】[0002]

【従来の技術】図3に示すPDS伝送方式は、光加入者
系を構成する一方式であり、局設備であるSLT(Subs
criber Line Terminal)から加入者宅内に設置されたO
NU(Optical Network Unit)までの途中にスターカプ
ラ等の多重化ノードを設け、複数のONUとSLTを接
続する。SLTと多重化ノードの間は複数のONUが同
一の光ファイバを共有する。図3に示すようにSLTか
らONUへの信号は時分割多重信号として放送形態で送
出される。
2. Description of the Related Art The PDS transmission system shown in FIG. 3 is one system that constitutes an optical subscriber system, and is an SLT (Subs)
O installed from the criber line terminal)
A multiplexing node such as a star coupler is provided on the way to the NU (Optical Network Unit) to connect a plurality of ONUs and SLTs. A plurality of ONUs share the same optical fiber between the SLT and the multiplexing node. As shown in FIG. 3, the signal from the SLT to the ONU is transmitted in a broadcast form as a time division multiplexed signal.

【0003】一方ONUからSLTへの信号はバースト
信号が送出されSLT受信点では、複数のONUからの
バースト信号が重なり合わないよう整列される。そのた
め、ONUでは、SLT受信点で他のONUからのバー
スト信号と衝突しないよう自己のバースト送出タイミン
グを制御して送出する。また、ONUからSLTへの信
号にはバーストの先頭位置の識別のため図4に示すよう
なプリアンブルが付加され、さらに各バーストの衝突を
防ぐため、バースト送出タイミングの制御に加え、ガー
ドタイムが設けられている。PDS伝送方式は光を用い
た伝送方式であるので、ONUおよびSLTからの信号
送出はLD(Laser Diode )等の発光素子を用いて行わ
れる。伝送符号としては、伝送効率の観点から、スクラ
ンブルドNRZ符号が使用される。
On the other hand, a burst signal is transmitted from the ONU to the SLT, and at the SLT receiving point, the burst signals from a plurality of ONUs are aligned so as not to overlap each other. Therefore, the ONU controls and transmits its own burst transmission timing so as not to collide with burst signals from other ONUs at the SLT reception point. Further, a preamble as shown in FIG. 4 is added to the signal from the ONU to the SLT to identify the start position of the burst, and in addition to controlling the burst transmission timing, a guard time is provided in order to prevent collision of each burst. Has been. Since the PDS transmission method is a transmission method using light, signal transmission from the ONU and SLT is performed using a light emitting element such as an LD (Laser Diode). A scrambled NRZ code is used as the transmission code from the viewpoint of transmission efficiency.

【0004】一方受信側(SLT)では、PD(Photo
Diode )等の受光素子により、光・電気変換を行い電気
信号を得、増幅器により後の処理に必要なレベルまで増
幅する。光素子と増幅器の間は現状では、コンデンサに
より結合せざるを得ない、その理由は受光素子の直流ド
リフトが大きく、直結したのでは増幅器の動作点が許容
範囲を越えてしまうためである。そのため、増幅器出力
波形の零電位点はバースト信号の多重数や、振幅の大小
により変動する。
On the other hand, on the receiving side (SLT), PD (Photo
A light receiving element such as a diode) performs optical / electrical conversion to obtain an electric signal, and an amplifier amplifies it to a level required for subsequent processing. At present, between the optical element and the amplifier, there is no choice but to couple them with a capacitor, because the DC drift of the light receiving element is large, and if they are directly connected, the operating point of the amplifier exceeds the allowable range. Therefore, the zero potential point of the amplifier output waveform varies depending on the number of multiplexed burst signals and the amplitude.

【0005】[0005]

【発明が解決しようとする課題】SLTでの受信波形は
図4のようになり、A部はONUまでの距離が短い場合
を示し、B部はONUまでの距離が長い場合を示す。こ
の信号波形を受信してバーストの先頭を検出するには、
直流遮断されたユニポーラバースト信号(図4)から各
バーストの平均直流成分を検出して、それを受信バース
ト信号に減算する等の手段によりバイポーラバースト信
号に変換する必要がある。
The received waveform at the SLT is as shown in FIG. 4, where the A section shows the case where the distance to the ONU is short, and the B section shows the case where the distance to the ONU is long. To receive this signal waveform and detect the beginning of the burst,
It is necessary to detect the average DC component of each burst from the DC blocked unipolar burst signal (FIG. 4) and convert it to a received burst signal and convert it to a bipolar burst signal.

【0006】その理由は、各バースト信号の振幅の違い
はONUまでの距離により30dB〜40dBあり、直
流遮断されたユニポーラ信号のまま処理しようとする
と、使用する増幅器のダイナミックレンジを極端に広げ
なければならない。例えば、最小レベルの信号を1Vま
で増幅すると最大レベルの信号は30〜100Vとな
り、増幅器の飽和点として30〜100Vも必要とな
る。もし、増幅器で飽和が生じると最小レベルの信号は
リミッタがかかったかたちで消失してしまう(図5
(a))。これに対し、バイポーラ信号に変換できれ
ば、増幅器の飽和点としては、最小レベル信号を出力で
きれば良い。最大レベルの信号は当然大きな振幅制限を
受けるが波形の零クロス付近の情報は失われないので、
バースト信号の検出には差し支えない(図5(b))。
The reason is that the difference between the amplitudes of the burst signals is 30 dB to 40 dB depending on the distance to the ONU, and if it is attempted to process the unipolar signal with the DC cut off, the dynamic range of the amplifier used must be extremely widened. I won't. For example, if the minimum level signal is amplified to 1V, the maximum level signal becomes 30 to 100V, and 30 to 100V is also required as the saturation point of the amplifier. If saturation occurs in the amplifier, the minimum level signal disappears with a limiter applied (Fig. 5).
(A)). On the other hand, if it can be converted into a bipolar signal, it is sufficient that the minimum level signal can be output as the saturation point of the amplifier. The signal of maximum level is naturally subject to large amplitude limitation, but the information near the zero crossing of the waveform is not lost, so
There is no problem in detecting a burst signal (FIG. 5 (b)).

【0007】次に、PDS方式では通常、バーストの終
了位置および開始位置はタイムスロット上の所定位置に
固定されているが、ONUインストール時には本格運用
に先だって、短いバースト長の「測定用バースト」をO
NUより送出して伝送路遅延時間を測定する。この場合
タイムスロット上のどの位置に「測定用バースト」が現
れるかかは不定であり、なんらかの方法でバースト先頭
位置を検出しなければならない。検出器は、回線雑音に
より誤検出しないことが必要である。本発明は、このよ
うな事情に鑑みてなされたものであり、直流成分を含ん
だ、各ONU毎に振幅の異なるバースト信号の到着を短
時間で検出する、バースト信号検出回路を提供すること
を課題とする。
Next, in the PDS method, the end position and the start position of the burst are usually fixed at predetermined positions on the time slot. However, when the ONU is installed, a "burst for measurement" having a short burst length is set prior to full-scale operation. O
It is sent from the NU and the transmission line delay time is measured. In this case, it is uncertain at which position on the time slot the "measurement burst" appears, and the burst start position must be detected by some method. It is necessary that the detector does not erroneously detect due to line noise. The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a burst signal detection circuit that detects arrival of burst signals including a DC component and having different amplitudes for each ONU in a short time. It is an issue.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に本発明のバースト信号検出回路においては、受信信号
に対して、所定の位相推移を与える位相回路を設け、差
動増幅器により受信信号と位相器出力信号の差分をとる
ことにより、直流成分を打ち消したバイポーラ信号を得
る。そのバイポーラ信号により、カウンタ回路を動作さ
せ、所定数のパルスを計数したらバースト検出信号を出
力する。
In order to solve the above-mentioned problems, in a burst signal detection circuit of the present invention, a phase circuit for giving a predetermined phase transition to a received signal is provided, and a received signal is generated by a differential amplifier. By taking the difference between the phaser output signals, a bipolar signal in which the DC component is canceled is obtained. The bipolar circuit operates the counter circuit to output a burst detection signal after counting a predetermined number of pulses.

【0009】[0009]

【作用】このように構成された、バースト信号検出回路
によれば、確実に、しかも短時間でバースト信号の先頭
を検出することが可能となる。
According to the burst signal detecting circuit constructed as described above, the head of the burst signal can be detected reliably and in a short time.

【0010】[0010]

【実施例】以下本発明の一実施例を図面を用いて説明す
る。 (第1の実施例)図1(a)はブロック図、図1(b)
はそのタイムチャートを示す。光受信器1の出力である
NRZバースト信号aはコンデンサ2で直流遮断され、
信号bとなる。信号bは位相回路3に入力され、その出
力から所定量だけ位相推移した信号cが得られる。差動
増幅器4は信号bおよび信号cを各々の入力に受けその
出力から直流成分の打ち消されたバースト信号dが取り
出される。カウンタ回路8は信号dをカウント入力とし
て動作し、所定数のカウントが終了したらカンウタ回路
8よりの出力信号kをハイレベルにする。図1(b)で
は信号dの正極パルス4個をカウントしたら検出とする
場合の例を示した。なお、カウンタ回路8は、別の手段
(図示せず)により検出されるバースト信号終了信号に
よりリセットされる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 (a) is a block diagram, FIG. 1 (b).
Shows the time chart. The NRZ burst signal a, which is the output of the optical receiver 1, is DC blocked by the capacitor 2,
It becomes the signal b. The signal b is input to the phase circuit 3, and a signal c whose phase has shifted by a predetermined amount is obtained from the output. The differential amplifier 4 receives the signal b and the signal c at its inputs, and the burst signal d in which the DC component is canceled is taken out from the output. The counter circuit 8 operates by using the signal d as a count input, and sets the output signal k from the counter circuit 8 to a high level when the counting of a predetermined number is completed. FIG. 1B shows an example in which four positive pulse pulses of the signal d are counted and detected. The counter circuit 8 is reset by the burst signal end signal detected by another means (not shown).

【0011】(第2の実施例)図2(a)はブロック
図、図2(b)はそのタイムチャートを示す。光受信器
1の出力であるNRZバースト信号aはコンデンサ2で
直流遮断され、信号bとなる。信号bは位相回路3に入
力され、その出力から所定量だけ位相推移した信号cが
得られる。差動増幅器4は信号bおよび信号cを各々の
入力に受けその出力から直流成分の打ち消されたバイポ
ーラ信号d,eが取り出される。信号dは正相出力、信
号eは逆相出力である。信号dは第1の比較器5の正相
入力および第2の比較器6の逆相入力に接続され、信号
eは第1の比較器5の逆相入力および第2の比較器6の
正相入力に接続される。
(Second Embodiment) FIG. 2A shows a block diagram and FIG. 2B shows a time chart thereof. The NRZ burst signal a, which is the output of the optical receiver 1, is blocked by the capacitor 2 for direct current and becomes a signal b. The signal b is input to the phase circuit 3, and a signal c whose phase has shifted by a predetermined amount is obtained from the output. The differential amplifier 4 receives the signal b and the signal c at its inputs, and extracts the bipolar signals d and e from which the DC components have been canceled out. The signal d is a positive phase output, and the signal e is a negative phase output. The signal d is connected to the positive phase input of the first comparator 5 and the negative phase input of the second comparator 6, and the signal e is the negative phase input of the first comparator 5 and the positive phase input of the second comparator 6. Connected to phase input.

【0012】その結果、第1の比較器5の出力には信号
dにおける正極性パルスを識別した信号fが現れ、第2
の比較器6の出力には信号dにおける負極性パルスを識
別した信号gが現れる。信号gおよび信号fはオア回路
7にそれぞれ入力され、その出力から信号g,fが合成
された2倍周波信号hが取り出される。カウンタ回路8
は2倍周波信号hをカウント入力として動作し、所定数
のカウントが終了したらカンウタ回路8よりの出力信号
kをハイレベルにする。図2(b)では2倍周波信号h
のパルス4個をカウントしたら検出とする場合の例を示
した。そのため、第2の実施例は、第1の実施例に比
べ、より短い時間でバースト信号の到着を検知可能とな
る。
As a result, the signal f which identifies the positive polarity pulse in the signal d appears at the output of the first comparator 5, and the second
At the output of the comparator 6, the signal g that identifies the negative polarity pulse in the signal d appears. The signal g and the signal f are respectively input to the OR circuit 7, and the double frequency signal h obtained by combining the signals g and f is taken out from the output thereof. Counter circuit 8
Operates with the double frequency signal h as a count input, and sets the output signal k from the counter circuit 8 to a high level when the counting of a predetermined number is completed. In FIG. 2B, the double frequency signal h
An example is shown in which the detection is performed by counting the four pulses of. Therefore, the second embodiment can detect the arrival of the burst signal in a shorter time than the first embodiment.

【0013】[0013]

【発明の効果】以上説明したように本発明のバースト信
号検出回路では、受信信号位相シフトする位相回路3
と、その出力と受信信号とを受領し直流分をキャンセル
したパルスを出力する差動増幅器4と、その出力パルス
を所定数カウントするカウンタ5とを備えた。そのた
め、極めて短時間でバースト信号の到着を検知可能であ
る。
As described above, in the burst signal detecting circuit of the present invention, the phase circuit 3 for phase shifting the received signal is used.
A differential amplifier 4 which receives the output and the received signal and outputs a pulse in which the DC component is canceled, and a counter 5 which counts the output pulse by a predetermined number. Therefore, the arrival of the burst signal can be detected in an extremely short time.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は、本発明の第1の実施例を示すブロッ
ク図、(b)は、その各点のタイムチャートを示す。
FIG. 1A is a block diagram showing a first embodiment of the present invention, and FIG. 1B is a time chart of each point.

【図2】(a)は、本発明の第2の実施例を示すブロッ
ク図、(b)は、その各点のタイムチャートを示す。
FIG. 2A is a block diagram showing a second embodiment of the present invention, and FIG. 2B is a time chart of each point.

【図3】PDS方式の概要を示す構成図である。FIG. 3 is a configuration diagram showing an outline of a PDS system.

【図4】PDS方式の光受信器の出力である受信バース
ト信号の波形図である。
FIG. 4 is a waveform diagram of a received burst signal output from a PDS optical receiver.

【図5】(a)は、ユニポーラバースト信号を増幅した
動作例、(b)は、バイポーラバースト信号を増幅した
動作例を示す。
5A shows an operation example in which a unipolar burst signal is amplified, and FIG. 5B shows an operation example in which a bipolar burst signal is amplified.

【符号の説明】[Explanation of symbols]

3 位相回路。 4 差動増幅器。 8 カウンタ。 Three-phase circuit. 4 Differential amplifier. 8 counters.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 受信信号に対して位相推移を与える位相
回路(3)と、 位相回路の出力と前記受信信号を各々の入力端子に受領
して直流成分の打ち消された信号を出力する差動増幅器
(4)と、 該差動増幅器出力を受領し、所定パルス数をカウント
し、バースト信号検出出力を発生するカウンタ(8)と
で構成されるバースト信号検出回路。
1. A phase circuit (3) for giving a phase shift to a received signal, and a differential circuit which receives the output of the phase circuit and the received signal at each input terminal and outputs a signal in which a DC component is canceled. A burst signal detection circuit comprising an amplifier (4) and a counter (8) which receives the differential amplifier output, counts a predetermined number of pulses, and generates a burst signal detection output.
JP5132682A 1993-05-10 1993-05-10 Burst signal detecting circuit Pending JPH06318908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5132682A JPH06318908A (en) 1993-05-10 1993-05-10 Burst signal detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5132682A JPH06318908A (en) 1993-05-10 1993-05-10 Burst signal detecting circuit

Publications (1)

Publication Number Publication Date
JPH06318908A true JPH06318908A (en) 1994-11-15

Family

ID=15087059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5132682A Pending JPH06318908A (en) 1993-05-10 1993-05-10 Burst signal detecting circuit

Country Status (1)

Country Link
JP (1) JPH06318908A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7962047B2 (en) 2007-02-28 2011-06-14 Hitachi, Ltd. Preamplifier and optical receiving apparatus using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7962047B2 (en) 2007-02-28 2011-06-14 Hitachi, Ltd. Preamplifier and optical receiving apparatus using the same

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