JPH06318392A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory such as a dual port memory and the like which realizes high speed clear operation and reducing power consumption by performing writing operation with a word line unit by a minute writing signal. CONSTITUTION:All data lines D of a memory array M-ARY are simultaneously made to be in a selecting state, A clear operation mode is performed with a word line unit. At the time, a level of a writing signal supplied from a write amplifier WA is made to be at a minute level same as a read out signal level outputted from a memory cell until selecting operation of a word line W is started after data lines D are made to be in all selecting state. Thereby, writing operation with a word line unit can be performed by a minute writing signal.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique effectively used for a dual port memory or the like.

2. Description of the Related Art There is a dual port memory having both a random access port and a serial access port. This dual port memory is often used as an image frame buffer memory for displaying, for example, characters or figures on the screen of a CRT (cathode ray tube). For this reason, dual port
The random access port and serial access port of the memory are provided with a plurality of data input / output terminals and an input / output circuit for inputting / outputting stored data in units of 4 bits or 8 bits, and each bit is displayed. It is associated with each color factor of the image. Dual like this
The port memory is described, for example, in "Nikkei Electronics", pages 243-264, published by Nikkei McGraw-Hill, Inc., March 24, 1986.

As described above, when the dual port memory is used as the image frame buffer memory, for example, the background color of the displayed image is changed, so that the specific color factor of the stored image is changed. The so-called clear function is required to rewrite the stored data of all the memory cells corresponding to the same data at high speed. Further, it is desirable that this clear function can be executed while displaying an image, in other words, without interrupting the serial output operation in the serial access port. The dual port memory described above includes:
A random access port is provided that can be randomly accessed regardless of the operating state of the serial access port. Further, the random access port is provided with a write bar bit function for performing maskable writing according to mask data supplied from the outside in advance. However, since the write cycle using the write bar bit function is performed in units of 4 bits or 8 bits, for example, it takes a considerable time to rewrite a series of image data.
As one method of realizing this clear function at high speed, all the data lines of the memory array are simultaneously selected, and the same image data is simultaneously written to a plurality of memory cells connected to the selected word line. Is proposed. However, like the normal write operation, this simultaneous write operation is performed after the word line selection operation is completed and the read signal of the selected memory cell is amplified by the sense amplifier. Therefore, the write amplifier which supplies the write signal must forcibly invert the level of a considerable number of complementary data lines of the memory array according to the write data during the write operation. Therefore, the write current supplied from the write amplifier becomes large, which is difficult to realize especially in a large capacity dual port memory or the like. An object of the present invention is to provide a semiconductor memory device such as a dual port memory which has a high speed clear operation and low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

A brief description will be given to the outline of typical ones of the embodiments disclosed in the present application.
It is as follows. That is, the clear operation mode is executed in units of word lines with all the data lines of the memory array being in the selected state all at once, and at this time, until the selection operation of the word lines is started after the data lines are all selected. In the meantime, the write amplifier is temporarily set to the selected state, and the level of the write signal supplied from the write amplifier is set to a minute level equivalent to the read signal level output from the memory cell.

According to the above-mentioned means, since the write operation in word line units can be performed by a minute write signal that can invert the read signal output from the memory cell, a semiconductor such as a dual port memory can be performed. The speed of the clear operation mode of the memory device can be increased, and the write current in the clear operation mode can be significantly reduced to achieve low power consumption.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a dual type to which the present invention is applied.
A block diagram of one embodiment of port memory is shown.
It Each circuit block in the figure is a conventional semiconductor integrated circuit.
Although not particularly limited by the manufacturing technique, single crystal silicon
It is formed on a single semiconductor substrate such as a semiconductor substrate. This
The dual-port memory of the embodiment of FIG.
A dynamic RAM including a rear array is used as its basic configuration.
Normally, random input operation of stored data is performed in units of 4 bits.
Random access port and word line unit
A serial interface that performs serial input / output operations for stored data
Access port will be established. Of these, Random
Access port, dual port memory
All complementary data when in a given clear mode of operation.
Data lines are selected all at once and the same memory data is written all at once.
It has a clear function. At this time, random access
From each write amplifier of the random port input / output circuit
The write signal supplied to each complementary data line is
Read and its level is output from the memory cell
It is set to a minute level equal to or higher than that of the signal. Also each light
The amplifier selectively operates according to the mask data supplied in advance.
The clear operation is performed, for example, for each color flag.
It can be executed in a maskable manner for each bit corresponding to the actor.
You can This allows for dual port memory
Is serial input / output via serial access port
4 bits by random access port in parallel with operation
Random access in bit units and clear in word line units
Has a function to perform an operation. Dual Po in this example
Memory memory random access ports
Without limitation, four memory arrays M-ARY1 to M-
ARY4 is provided to support each memory array
Sense amplifiers SA1 to SA4, column switch CSW
1 to CSW4 are provided. In addition, the memory array MA
Random access, common to RY1 to M-ARY4
Port column address decoder RCD and row address
A decoder RD is provided. These address decor
Depending on the layout of the memory array on the semiconductor substrate,
Several may be provided. In FIG. 2, the memory array M
-ARY1 and its corresponding peripheral circuits are exemplarily shown.
ing. In FIG. 2, the memory array M-ARY1 is
M + 1 word lines W0-W0 arranged in the vertical direction in FIG.
Wm and n + 1 sets of complementary data arranged horizontally in the same figure.
Data lines D0 / D0B to Dn / DnB and these word lines
And (m + 1) × (n +) arranged at the intersection of
1) Comprised of dynamic memory cells.
Here, regarding low-active signal lines and signals
Is shown with a bar (B) attached, and so on.
And Each memory cell has a
Information storage capacitor Cs and N-channel type address
It is composed of a selection MOSFET Qm. Memorial
B. n + 1 memos arranged in the same row of M-ARY1
The gate of the address selection MOSFET Qm of the recell is
It is coupled to corresponding word lines W0-Wm. Also note
M + 1 pieces arranged in the same column of rear array M-ARY1
Of the MOSFET Qm for address selection of the memory cell of
IN is the input / output node of the memory cell and corresponds to
Predetermined regularity for the complementary data lines D0 / D0B to Dn / DnB
Are joined alternately. Memory array M-ARY1
Each word line constituting the
Of the X address signals AX0 to AXi.
One word line designated by
Be done. The row address decoder RD is a row address buffer.
Complementary internal address signal supplied from the RARADBax
0 toaxi (here, for example, the non-inverted internal address signal a
x0 and inverted internal address signal ax0B together
Department address signalaIt is expressed as x0. The same below)
Select a single word line at high level
State. Word line by row address decoder RD
Selection operation is supplied from the timing control circuit TC.
In synchronization with the high level of the word line selection timing signal φx
Will be performed. The row address buffer RADB is an add
Row address supplied from Resmux AMX
Receiving a signal, the above complementary internal address signalax0axi
Are formed and supplied to the row address decoder RD. this
The dual port memory of the embodiment has a row address
X address signals AX0 to AXi to be designated and column address.
The Y address signals AY0 to AYi that specify the
It is supplied in a time-sharing manner via the partial terminals A0 to Ai.
It adopts the loose address multiplex method. Tsuma
The external terminals A0 to Ai are connected to the row address strobe.
X address signal A in synchronization with the fall of signal RASB
X0 to AXi are supplied, and the column address strobe C
Y address signals AY0 to AY0 are synchronized with the fall of ASB.
AYi is supplied. In addition, the dual port of this embodiment is
The data stored in the memory cells is stored in the
Automatic refresh for reading and rewriting in time
Mode is provided, and this automatic refresh mode is
For sequentially specifying the word lines to be refreshed
A refresh address counter REFC is provided.
In addition, the refresh address counter REFC
Refresh address signals rx0 to rx formed by
i and the X address signals AX0 to AXi are selectively set to low.
The address matrix for transmission to the address buffer RADB
A luplexer AMX is provided. Address multiple
The wedge AMX is supplied from the timing control circuit TC.
Normal memory in which the internal control signal ref is at low level
In access mode, via external terminals A0-Ai
Select the supplied X address signals AX0 to AXi and
(3) Row address buffer RADB as an address signal
introduce. Further, the internal control signal ref is at a high level.
In the automatic refresh mode, which is considered
Refresh output from the address counter REFC
Address address signals rx0 to rxi to select the row address
The signal is transmitted to the row address buffer RADB as a signal.
As described above, the X address signals AX0 to AXi are low
In synchronization with the falling edge of the dress strobe signal RASB
Supplied. Therefore, the row address buffer RADB
Timing control of row address signal fetching by
Row address strobe signal RASB in circuit TC
Formed by detecting the falling edge of
According to the ringing signal φar. Meanwhile, the memory array
B Complementary data lines D0 and D0B constituting M-ARY1
Dn / DnB has a column switch C on one side.
Coupled to the corresponding switch MOSFET in SW1,
In addition, these switch MOSFETs are used to selectively
Complementary common data lineCD1 (here, for example, the non-inverted signal line C
Complementary common data for D1 and inverted signal line CD1B
lineCIt is expressed as D1. The same shall apply hereinafter). Kara
The switch CSW1 is an n + 1 switch MOSFE.
It is composed of T. These switch mosfets
One of the terminals is connected to the corresponding complementary data line.
And the other terminal is a non-inverted signal that forms a complementary common data line.
Common connection to signal line CD1 or inverted signal line CD1B
To be done. As a result, the column switch CSW1 becomes
Data lines D0 / D0B to Dn / DnB and common complementary data line
CSelectively connect to D1. Column switch CSW
The gates of each pair of switch MOSFETs that make up
Each is commonly connected and used for random access port
Select corresponding data line from RAM address decoder RCD
The signals Y0 to Yn are respectively supplied. Random ac
The column address decoder RCD for access ports is
RAM address buffer CADB to complementary internal address signal
issueay0-ayi is supplied to the timing control circuit TC
From which timing signals φyr and φad are supplied. This
Of these, the timing signal φyr is the dual port
Selected as low level when the memory is not selected
Status, the dual port memory selects the data line.
It is set to the high level when the selection operation can be started. Also,
The timing signal φad is used by the dual port memory.
Low level when in non-selected state and normal operation mode
And the dual port memory is cleared.
Until the selection operation of the word line is started.
In the meantime, it is temporarily set to a high level. Random access
・ Port column address decoder RCD is dual
• When the port memory is put into normal operating mode,
Complementary internal supplied from RAM address buffer CADB
Address signalay0-aDecode yi and
Corresponding data line selection signal Y0
~ Yn is alternatively set to the high level. Also, dual
When the port memory is set to clear operation mode,
Select all data lines according to the timing signal φad
The signals Y0 to Yn are temporarily set to the high level all at once. this
All complementary data lines D0.D0B to Dn.D
nB remains unchanged until the word line selection operation is started.
Common data lines that are complementary all at onceCConnected to D1 and run
Clear from the corresponding write amplifier of the dam input / output circuit RIO.
A predetermined write signal according to the data is supplied. Mosquito
The RAM address buffer CADB has a timing control circuit.
The timing signal φac is supplied from the path TC. This tab
The imming signal φac is a column address strobe signal.
When CASB changes from high level to low level
It is temporarily set to high level. Column address buffer
CADB is an external terminal A according to the timing signal φac.
Y address signals AY0 to AY supplied via 0 to Ai
Capture Yi and hold it. Also, these Y addresses
The complementary internal address signal based on AY0 to AYiay
0 toaforming a yi, above random access port
For column address decoder RCD. Memoria
Ray M-ARY1 complementary data lines D0, D0B to Dn,
DnB is a pair of sense amplifier SA1 on the other side.
Coupled to the corresponding unit amplifier circuit,
Correspondence of the data register DR1 provided in the access port
Is connected to the unit circuit. The sense amplifier SA1 has a phase
Provided corresponding to the complementary data lines D0 / D0B to Dn / DnB
N + 1 unit amplifier circuits and precharge circuits
Including. Of these, each unit amplifier circuit of the sense amplifier SA1
Are two sets of cross-connected CMOS devices, as will be described later.
The basic structure is a latch composed of an inverter circuit. This
These unit amplifier circuits are supplied from the timing control circuit TC.
Operated simultaneously according to the supplied timing signal φpa
And output to the corresponding complementary data line
High level / low level
Is a binary signal. On the other hand, the sense amplifier SA1
The charge circuit includes complementary data lines D0, D0B to Dn, D.
N provided between the non-inverted signal line of nB and the inverted signal line
Channel type short-circuit switch MOSFET
Is made. The gates of these switch MOSFETs are
Through the timing control circuit TC.
No. φpc is supplied. This timing signal φpc is
When the dual port memory is deselected
Level and dual port memory selected
Is set to a low level. Sensuan
A switch MO that constitutes each precharge circuit of the SA1
For SFET, dual port memory is not selected
When the timing signal φpc is set to the high level,
It is turned on all at once. Thereby, the complementary data line D
Both signal lines of 0 ・ D0B to Dn ・ DnB are short-circuited
The level is half-preset, which is about 1/2 of the power supply voltage Vcc.
Charge level. Dual port memory
When the timing signal φpc is selected and the low level
Switch MOS that constitutes the precharge circuit when
The FETs are turned off all at once. Column switch CS
Depending on W, the complementary data lines D0 / D0B to Dn / DnB
Selectively connected complementary common data linesCD1 is Randa
Memory I / O circuit RIO. This random input / output
The circuit RIO includes memory arrays M-ARY2 to M-AR.
Complementary common data line provided corresponding to Y4CD2-C
D4 is similarly linked. Random input / output circuit RIO
As described later, each complementary common data lineCD1CD
4 write amplifiers WA1 to WA provided corresponding to 4
A4 and read amplifiers RA1 to RA4 and their writing
Input bags provided for amplifiers and read amplifiers
The buffers IB1 to IB4 and the output buffers OB1 to OB4
Including. In addition, the random input / output circuit RIO is
Mass to selectively put WA1 to WA4 into operation state
Mask register MR that holds the data
Data lineCD1C4 pre-installed corresponding to D4
Including charge circuit. For the write amplifiers WA1 to WA4
The timing signal φrw is output from the timing control circuit TC.
It is selectively supplied according to the output signal of the register MR.
Timing signals φ are output to the output buffers OB1 to OB4.
rr is supplied. In addition, the mask register MR has
Timing signal φmw is supplied from the imming control circuit TC
The timing signal φpc is supplied to the precharge circuit.
Is supplied. Write input / output of random input / output circuit RIO
WA1-WA4 are normal dual port memory
In the write operation mode and the clear operation mode of
The operating state is selectively changed according to the timing signal φrw.
From the corresponding input / output terminals IO1 to IO4
Write data supplied via the data IB1 to IB4
Corresponding complementary common data line as complementary write signalC
D1CSupply to D4. Similarly, the output buffer OB1
~ OB4 is a dual port memory read operation
Mode, selectable according to timing signal φrr
And corresponding read amplifiers RA1 to RA
Input / output terminal corresponding to read data output from 4
It is sent from IO1 to IO4 to an external device. Also, the mass
C register MR clears dual port memory
In operation mode, input from I / O terminals IO1 to IO4
The mask data supplied via the force buffers IB1 to IB4.
Data according to the timing signal φmw and hold
It The precharge circuit is a complementary common data lineCD1C
N provided between the non-inverted signal line and the inverted signal line of D4
Channel type short-circuit switch MOSFET
Is made. These switch MOSFETs are dual
・ Timing signal φ when port memory is not selected
When pc is set to high level, it is turned on at the same time,
Complementary common data lineCD1CShort both signal lines of D4
The same as the complementary data lines D0 / D0B to Dn / DnB.
Go to the pre-charge level. Random input / output circuit R
IO write amplifiers WA1 to WA4, read amplifier RA
1-RA4, input buffers IB1-IB4 and output buffer
Fas OB1 to OB4, mask register MR and precharger
The charge circuit will be described in detail later. dual·
The random input / output circuit RIO of the port memory is
Includes arithmetic logic circuits with various arithmetic functions such as raster operation
Mu. Arithmetic mode performed by this arithmetic logic circuit
Is a calculation mode signal a supplied from the function control circuit FC.
It is alternatively designated by m0 to am15. Function control
The circuit FC is a performance that is supplied via the external terminals A0 to A3.
A register that captures and holds arithmetic codes and these operations
The code is decoded and the operation mode signals am0 to am1
5 includes a decoder that selectively forms 5. The operation code is
The column address strobe signal C is not particularly limited.
ASB precedes row address strobe signal RASB
To the low level, and at the same time, the write enable signal WE
In the operation mode setting cycle where B is at low level
Through the external terminals A0-A3.
Supplied to Mori. On the other hand, the dual port of this embodiment
The serial memory serial access port
It is provided corresponding to Rays M-ARY1 to M-ARY4.
Data registers DR1 to DR4 and data selector DSL
1 to DSL4 and these data registers and data selectors
The pointer PNT and the address
Column address for serial access port
Decoder SCD and serial input / output circuit SIO
Composed. The pointer PNT and the address latch A
Column address data for L and serial access port
The coder SCD is a memory array on a semiconductor substrate.
Depending on the arrangement, a plurality may be provided. In Figure 2,
Memory array M-ARY1 and corresponding data register
The star DR1 and the data selector DSL1 are exemplarily shown.
Has been. In FIG. 2, the data register DR1 is
Memory array M-ARY1 complementary data lines D0 and D0B
N + 1 latches provided corresponding to Dn and DnB
Including. I / O nodes for these latches and corresponding complementary
N + 1 pairs of switches for data transfer with the data line
Each MOSFET is provided. These switches
The MOSFET is a high level signal from the timing control circuit TC.
A bell data transfer timing signal φtr is supplied.
By doing so, all of them are turned on at the same time. Data register
The input / output node of each latch constituting the data DR1 is
Switch MOSFE corresponding to the data selector DSL1
Complementary common data line for serial input / output via TCDS
1 is selectively connected. The data selector DSL1 is
Similar to the column switch CSW1 described above, n + 1 pairs of switches are used.
Switch MOSFET. Data selector
One of each pair of switch MOSFETs in DSL1
It is connected to the corresponding bit of the data register DR1.
And the other is the complementary common data line for serial input / output.CD
Commonly connected to S1. Also, each pair of switch MOSF
The gates of ET are commonly connected, and the pointer PNT is connected.
The corresponding data register selection signals S0 to Sn are supplied from
To be done. The pointer PNT has complementary data lines D0 and D0B.
To Dn and DnB are provided (n +
1) The basic structure is a bit shift register. Point
The output signal sb of the last bit of the PNT is
It is supplied to the input terminal. For the pointer PNT,
Timing signal for shift clock from control circuit TC
φc is supplied. The pointer PNT has the above timing.
A loop-shaped shift operation is performed according to the signal φc, and
The data register selection signals S0 to Sn are sequentially formed. This
These data register selection signals S0 to Sn are data
Common to the corresponding switch MOSFETs of the rector DSL1
Supplied to the connected gate. Each pointer PNT
Via the corresponding switch MOSFET
It is connected to the corresponding bit of address latch AL.
Be done. The gates of these switch MOSFETs are all
Commonly connected, timing from timing control circuit TC
The signal φps is supplied. This timing signal φps
Is a dual-port memory read data transfer
Cycle or write data transfer cycle.
Column address deco for serial access port
Decoding operation of column address by reader SCD is completed
Then, the data transfer control signal DTB / OEB returns to high level.
It is temporarily set to a high level at the time of being. Pointer P
These switch MOSFETs in NT are
When the signal φps is temporarily set to the high level,
It is turned on at the same time. The address latch AL is
It is provided corresponding to each bit of the inter PNT (n +
1) Consists of a bit latch. These racks
I / O node is the corresponding switch MOSF
Column access for serial access port via ET
Connect to the corresponding output terminals of the dress decoder SCD.
Will be continued. The gates of these switch MOSFETs
All of them are commonly connected, and timing control circuit TC
Ing signal φas is supplied. This timing signal φa
s is a dual port memory read data transfer
Cycle or write data transfer cycle
Column address data for the serial access port.
The decoding operation of the column address by the coder SCD is completed.
At the time of completion, it is temporarily set to a high level. Address
These switch MOSFETs from Chutch AL are
Signal is set to high level,
It is turned on. Color for serial access port
The column address buffer is included in the system address decoder SCD.
Comparator internal address signal from CADBay0-ayi
Is supplied. Column access for serial access port
The dress decoder SCD receives these complementary internal address signals.
issueay0-ayi is decoded and Y address signal AY1
~ Corresponds to one set of complementary data lines specified by AYi
The output signal to be set is alternatively set to the high level. This hight
The bell output signal is the timing signal φa as described above.
By setting s to the high level, the address latch A
Captured in the corresponding bit of L, and also the timing signal
By setting φps to the high level, the pointer PN
The corresponding bit of T is set as a shift signal of logic "1".
Is set. Set in shift register of pointer PNT
The shift signal generated is the falling edge of the timing signal φc.
The pointer PNT is shifted in a loop in synchronization with the edge.
To be done. That is, dual port memory serial
・ Serial I / O operation mode by access port
In addition, the column address of the read data to be output first
Address, that is, the first column address is the Y address signal A
Y0 to AYi, that is, complementary internal address signalsay0-a
Specified by yi. These complementary internal address signals
issueay0-ayi is the color for serial access port
Type address decoder SCD
According to the minging signal φas, the leading address of the address latch AL is
High-level select signal for the bit corresponding to the RAM address
Is entered. This selection signal is a timing signal φps
The pointer PNT to the corresponding bit.
Is applied to generate a shift signal of logic "1". Memory data
When the serial input / output operation is started, the pointer PNT
Is supplied with a timing signal φc for shifting. Poi
Logic set to the specified bit of the PNT
The shift signal of 1 "has a falling edge of this timing signal φc.
Shift in a loop in the pointer PNT in synchronization with the edge
Data register selection signals S0 to Sn are sequentially formed.
To be done. As a result, the switch of the data selector DSL1
H MOSFETs are sequentially turned on and the data register
Each bit of DR1 corresponds to the top column address
Serial common input / output complementary common data lineCDS1
Is connected alternatively. Therefore, the du
Al port memory can be read from any column address.
Starts serial I / O operation of real access port
can do. Complementary common data line for serial I / O
CDS1 is coupled to the serial input / output circuit SIO.
The serial input / output circuit SIO includes a memory array M-
Serial provided corresponding to ARY2 to M-ARY4
Complementary common data line for input / outputCDS2CDS4 as well
Be combined. The serial input / output circuit SIO is
Complementary common data line for outputCDS1CDS4 and Syria
Provided corresponding to the input / output terminals SIO1 to SIO4
4 sets of main amplifier, data input buffer and data output
Including force buffer. Of these, the data output buffer is
Dual port memory serial output mode
The timing supplied from the timing control circuit TC
Operated by the high level of signal φsr
Serial I / O Complementary common data lineCDS1CDS
Read out from 4 via corresponding main amplifier
Then, the data is transferred to the corresponding serial line according to the timing signal φc.
It is sent to the I / O terminals SIO1 to SIO4. on the other hand,
The data input buffer of the serial input / output circuit SIO is
The serial port mode of the dual port memory
The timing supplied from the timing control circuit TC
Operated by the high level of the signal φsw
Via serial I / O terminals SIO1 to SIO4
Write data supplied from the device
Signal and the corresponding serial signal according to the timing signal φc.
Al Complementary common data line for input / outputCDS1CReached to DS4
Reach The timing control circuit TC is a control signal from the outside.
Address strobe signal RAS supplied as
B, column address strobe CASB, write enable
Bull WEB, data transfer control signal DTB / OEB and serial
Based on the real output control signal SOEB
And the internal control signal is generated and supplied to each circuit.
It Also, the timing control circuit TC is supplied from the outside.
Timing signal based on serial clock signal SC
φc is formed, pointer PNT and serial input / output circuit
Supply to SIO. 1, the dual port of FIG.
.Memory random input / output circuit RIO and its peripheral circuits
A circuit diagram of one embodiment is shown. In the figure,
MOSF with an arrow added to the channel (back gate) part
ET is a P-channel type and N channel without an arrow
It is distinguished from a channel MOSFET. In the figure, Randa
This invention is directly related to the arithmetic logic circuit of the input / output circuit RIO.
Unrelated circuit blocks are omitted. Figure 1 Smell
Each memory cell of the memory array M-ARY1 is
Storage capacitor Cs and address selection MOSFET
Each is composed of Qm. Memory array M-A
Of n + 1 memory cells arranged in the same row of RY1
The gate of the address selecting MOSFET Qm corresponds to
The word lines W0 to Wm are commonly connected. these
The word lines W0 to Wm of
Complementary internal address signal coupled to RDax0axi
In accordance with the above, the high-level selection state is alternatively set. one
On the other hand, they are arranged in the same column of the memory array M-ARY1.
Address selection MOSFETQ of m + 1 memory cells
The drains of m are corresponding complementary data lines D0 and D0B ...
Dn / DnB non-inverted signal line or inverted signal line must be
They are connected alternately with regularity. These complementary data lines
D0 / D0B to Dn / DnB are
Pre-charge MOSFE corresponding to the sense amplifier SA1
Through TQ3 to Q4, the corresponding unit amplifier circuits USA1 to USA1
Bound to USA2. Precharge MOSFETQ
Gates 3 to Q4 are all connected in common, timing control
The timing control signal φpc is supplied from the control circuit TC.
It The precharge MOSFETs Q3 to Q4 are dual
Port port memory is not selected and timing signal
When φpc is set to high level, it is turned on all at once.
The corresponding non-inverted signal line and complementary
The signal line is short-circuited and both signal lines are harply charged.
And The sense amplifier SA1 includes unit amplifier circuits USA1 to USA1.
The input terminal and the output terminal of USA2 are connected to each other.
Consists of two sets of CMOS inverter circuits
Be done. These CMOS inverter circuits have P-channel
Via the channel MOSFET Q1 and the common source line PS
The power supply voltage Vcc of the circuit is supplied. Also, these C
N-channel MOSFET is used for the MOS inverter circuit.
The ground potential of the circuit goes through Q2 and the common source line NS.
Supplied. Timing for the gate of MOSFET Q2
The timing signal φpa is supplied from the control circuit TC, and M
The timing signal φpa is applied to the gate of the OSFET Q1.
The inverted signal from the inverter circuit N1 is supplied. This
As a result, the unit amplifier circuit USA1 of the sense amplifier SA1
~ USA2 is when the timing signal φpa is high level.
Are activated all at once. This behavior
In the state, each unit amplifier circuit US of the sense amplifier SA1
A1 to USA2 are connected to the selected word lines W0 to Wm.
Corresponding complementary data from n + 1 memory cells to be combined
Minutes output via lines D0 / D0B to Dn / DnB
Amplifies the read signal and outputs high level / low level binary
It is a read signal. Complementary data lines D0 / D0B to Dn
・ DnB is column switch CSW
1 corresponding switch MOSFET Q5 · Q6 to Q7 ·
Select the complementary common data lines CD1 and CD1B via Q8
Connected selectively. Each pair of column switches CSW1
Run gates are connected to the commonly connected gates of the switch MOSFETs.
Column address decoder RC for dam access port
The corresponding data line selection signals Y0 to Yn from D respectively
Supplied. Random access, but not limited to
・ The port column address decoder RCD is shown in Fig. 1 as an example.
As shown, n + 1 NAND gates NAG
1 to NAG2 and NAG3 to NAG4. Nandoge
NAG1 to NAG2 are not particularly limited, but i +
It has two input terminals. Of these, the 1st to the i + 1st
The input terminal of each is connected to the column address of the corresponding complementary data line.
Complementary internal address signalay0-awhere yi is
Supplied in a fixed combination. Also, the i + 2nd
Timing from the timing control circuit TC to the input terminal
The signal φyr is commonly supplied. This allows each nando
The output signals of the gate circuits NAG1 and NAG2 are normally high level.
And the timing signal φyr is set to high level.
Complementary internal address signalay0-aThe combination to which yi corresponds
Is set to an alternative low level. Nandoge
The output signals of the gates NAG1 and NAG2 are NAND gate NA.
It is supplied to one of the input terminals of G3 to NAG4. these
To the other input terminals of the NAND gates NAG3 to NAG4 of
Is the timing supplied from the timing control circuit TC
Inverted signal of inverter circuit N3 of signal φad is input
To be done. Output signals of NAND gates NAG3 to NAG4
Is a column scan as the data line selection signals Y0 to Yn.
Switch CSW1 corresponding switch MOSFET game
Be supplied to As described above, the timing signal φad
Indicates that the dual port memory has a clear operating mode.
Are temporarily set high before the word line selection operation.
It is a level. Therefore, the NAND gate circuit NAG
3 to NAG4 output signal, that is, data line selection signal Y0
To Yn are corresponding NAND gate circuits NAG1 to NAG.
When the output signal of 2 is set to low level,
And the timing signal φad goes high
When it is done, it is simultaneously set to high level. That is, data
The line selection signals Y0 to Yn are used by the dual port memory.
When the normal operation mode is set, the timing signal φyr
Are set to a high level and Y address signals AY0 to AYi
Are selected as the corresponding combinations.
Is put in a state. Also clear dual port memory
When in operation mode, prior to word line selection operation
The timing signal φad is set to the high level.
Then they are all selected. Data line selection signal Y0
When Yn is in the high-level selected state, the column scan
Switch MOSFET Q5 corresponding to switch CSW1
Q6 to Q7 and Q8 are turned on and the corresponding complementary data
Data lines and complementary common data lines CD1 and CD1B are selectively connected.
To continue. The complementary common data lines CD1 and CD1B are especially controlled.
The random I / O circuit RIO supports
Corresponding light via MOSFET Q9 for recharge
Output terminal of amplifier WA1 and input of read amplifier RA1
It is connected to the terminal. Similarly, memory array M-ARY2
Complementary common data line C provided corresponding to M-ARY4
Random input / output for D2 / CD2B to CD4 / CD4B
Precharge MOSFET Q1 corresponding to the circuit RIO
The corresponding write amplifiers WA2 to WA through 0 to Q12
4 output terminal and input terminals of read amplifiers RA2 to RA4
Respectively bound to the children. Precharge MOSFET
The gates of Q9 to Q12 are commonly connected, and timing control
The timing signal φpc is supplied from the circuit TC.
As a result, the precharge MOSFETs Q9 to Q12 are
Indicates that the dual port memory has been deselected and
By setting the imming signal φpc to the high level
It is turned on all at once, and the corresponding complementary common data line CD
1-CD1B to CD4-CD4B non-inverted signal line and reverse
Short the signal line and set it to the specified half precharge level.
To do. In other words, the dual port memory of this embodiment
Is complementary to the complementary data lines D0 / D0B to Dn / DnB.
Common data lines CD1, CD1B to CD4, CD4B
Recharge level is about 1/2 of power supply voltage Vcc
It is set to the half precharge level. For this reason,
Dual-port memory clear operation mode.
Mode and write amplifiers WA1 to WA4 set mask data.
When performing a maskable write operation according to
Complementary data line of the memory array corresponding to the bit
D0 / D0B to Dn / DnB levels correspond to each other
Prevents fluctuations by connecting to the communication data line
It has stopped. Random input / output circuit RIO write amplifier
The input terminals of WA1 to WA4 correspond to the corresponding input buffer I
They are respectively coupled to the output terminals of B1 to IB4. these
The input terminals of the input buffers IB1 to IB4 of
It is coupled to corresponding input / output terminals IO1-IO4. Input bar
Buffers IB1 to IB4 are corresponding input / output terminals IO1 to I
Write data etc. supplied from outside via O4
The corresponding write amplifiers WA1 to WA4 are used as complementary signals.
introduce. Non-inverted output signals of input buffers IB1 to IB4
The number of bits is the input of the corresponding bit of the mask register MR.
Power terminal. This mask register MR has a
Timing signal φmw is supplied from the imming control circuit TC
To be done. The dual port memory of this embodiment is
As described above, the row address strobe signal RASB
Caused by changing from high level to low level
Be moved. Standing of this row address strobe RASB
The write enable signal WEB and
The data transfer control signal DTB / OEB is set to low level
Dual port memory is in clear operating mode
It is said that In this clear operation mode, there are no particular restrictions.
However, the fall of the row address strobe signal RASB
X address signal that specifies the word line in synchronization with the edge
AX0 to AXi are supplied to the external terminals A0 to Ai, and at the same time
The mask data to be loaded into the mask register MR.
It is supplied via the output terminals IO1 to IO4. In addition,
Falling edge of RAM address strobe signal CASB
Write data in synchronization with the input / output terminals IO1 to IO
4 is supplied. The timing signal φmw is a dual
In the port port memory clear operation mode.
Detect the falling edge of the dress strobe signal RASB.
It is temporarily set to a high level when issued. timing
Since the signal φmw is temporarily set to high level, the mass
The register MR corresponds from the input / output terminals IO1 to IO4.
4 supplied via the input buffers IB1 to IB4
Captures and holds bit mask data. Especially limited
These mask data are not
When the write operation of is executed without masking,
And mask the write operation of the corresponding bit
Selectively set to high level. Each of the mask registers MR
The output signal of the bit is the corresponding NOR gate circuit NOG1.
~ Is supplied to one input terminal of NOG4. These no
To the other input terminal of the agate circuits NOG1 to NOG4
Is the timing supplied from the timing control circuit TC
Input the inverted signal of the signal φrw by the inverter circuit N2
To be done. As a result, the NOR gate circuits NOG1 to NOG
For the output signal of 4, both corresponding two input signals are low.
When the level is set, that is, the timing signal φrw is
High level and corresponding non-correspondence of mask register MR
Selects high level when the inverted output signal is low level.
It is considered a bell. In other words, write amplifiers WA1 to WA4
The timing signal φrw for setting the operating state is the mask
Mask data held in corresponding bit of register MR
Data is set to low level, that is, the corresponding bit
Selective support when write operations are not masked
Are transmitted to the write amplifiers WA1 to WA4. Noage
The output signals of the output circuits NOG1 to NOG4 correspond to the corresponding line signals.
Supply to the operation control terminals of the amplifiers WA1 to WA4 respectively
To be done. Level control terminals of the write amplifiers WA1 to WA4
From the timing control circuit TC.
No. φad is supplied. Write amplifiers WA1 to WA4
Through the corresponding NOR gate circuits NOG1 to NOG4
Selectively operates according to the timing signal φrw supplied by
It is in a working state. In this operating state, the write amplifier
WA1 to WA4 are corresponding input / output terminals IO1 to IO4
From the corresponding input buffers IB1 to IB4
The complementary write signal according to the write data
Corresponding complementary common data CD1, CD1B to CD4, CD
It is supplied to the selected memory cell via 4B. this
Complementary writing output from these write amplifiers
The level of the only signal is the level supplied as the level control signal.
It is controlled according to the imming signal φad. That is,
Normal writing in which the imming signal φad is at low level
Only the write amplifiers WA1 to WA4 in the operation mode
The complementary write signal output from the
Such as high level and low level like circuit ground potential
The room is full swing. Also, the timing signal φa
In the clear operation mode where d is high level,
Complementary write signals output from the amplifiers WA1 to WA4
Signal level is the read signal output from the memory cell
It is considered to be a micro level equal to or higher than. That is, as mentioned above
And the input / output node of the memory cell of the memory array M-ARY1.
The corresponding complementary data lines D0 / D0B to Dn / D
nB non-inverted signal line or inverted signal line also has a certain regularity
Are joined alternately. The data stored in each memory cell is
Presence or absence of electric charges accumulated in the information storage capacitor Cs
According to the above, it is set to the logic "0" or the logic "1". Sanawa
, For example, its input / output node is
For memory cells coupled to a signal line, the corresponding word line
Is for high-level selection and address selection
The MOSFET Qm is turned on. At this time, correspondence
Logic "0" is applied to the non-inverted signal line of the complementary data line
When a low-level write signal is supplied, it is used for information storage
The electric charge of the capacitor Cs is discharged. Also the corresponding phase
A logic "1", that is, a high
When the bell write signal is supplied, the information storage capacity
Charge is injected into the shutter Cs, and the address selection MO
The potential of the electrode on the SFETQm side is almost the power supply voltage Vcc.
It This memory cell is selected in the read operation mode
Then, the non-inverted signal line of the corresponding complementary data line
For example, about 2 depending on the accumulated charge of the information storage capacitor Cs.
A minute read signal of 00 mV is output and its level is
About 200 mV higher than the precharge level
It At this time, the inversion signal line of the corresponding complementary data line is
It remains at the precharge level. Check the complementary data line
The bell difference is the unit amplifier circuit corresponding to the sense amplifier SA1.
Amplified by high level or low level binary reading
It is regarded as a projected signal. Dual port memory is normal
Write operation mode when the write operation mode is set to
1 to WA4 are selected after the word line selection operation is completed.
Read out n + 1 memory cells coupled to a word line
When the signal is established by the corresponding sense amplifier
Is activated. Therefore, the selected memory
In order to rewrite the stored data of the
A write signal with a level that can invert the output signal is required.
I need it. Therefore, the normal write operation mode
Writing from the write amplifiers WA1 to WA4
Signal is between full and low levels.
Be used. Meanwhile, dual port memory is clear
When the operation mode is set, the write amplifiers WA1 to WA4
Is temporarily activated prior to the word line selection operation.
At this time, output from the write amplifiers WA1 to WA4
The write signal centered around the half precharge level
And their positive and negative signal amplitudes are
For example, about 200 mV, which is the same as the read signal of the memory cell,
It is considered to be a minute level. When the writing operation is completed,
Memory cell is selected and
By being held in the memory cell until then
When a minute read signal according to the stored data is output,
The level of the non-inverted signal line of the corresponding complementary data line is changed.
Be done. That is, it was held in the memory cell until then
Stored data is logical "0", and new writing
If the data is logic "0", the level of the non-inverted signal line
The read signal level of the memory cell is superimposed on the
-The pre-charge level has dropped by about 400 mV, for example.
It becomes a level. In addition, the level of the inverted signal line is read
Half precharge level without being affected by signals
From this, for example, the level is increased by about 200 mV. This and
If the new write data is logic "1",
The level of the inverted signal line depends on the read signal of the memory cell.
Are canceled out and returned to the half precharge level. Well
Also, the level of the inverted signal line affects the readout signal as well.
From the half precharge level without being
The level is about 200 mV lower. On the other hand, until then
The storage data of logic "1" is held in the memory cell,
A new write operation of storage data of logic "0" is performed.
If the level of the non-inverted signal line is
Signal is canceled by the signal to reach the half precharge level
Will be returned. The level of the inverted signal line is the read signal
From the half precharge level without being affected by
For example, the level is increased by about 200 mV. At this time,
Non-inverted when new write data is logic "1"
The read signal of the memory cell is superimposed on the signal line level.
400 mV above the half precharge level
It will be an elevated level. The level of the inverted signal line is the same.
Like half pre-printing without being affected by the read signal.
Level that is about 200 mV lower than the charge level
Becomes In other words, clearing the dual port memory
In the production mode, output from the write amplifiers WA1 to WA4.
The complementary write signal is output from the memory cell
Even though the level is as low as the output signal
The complementary data line is output from the memory cell after writing
The level difference remains about the same as the read signal that is input.
It The level difference between the complementary data lines is
High level or low level binary expanded by
Signaled. This allows information on the selected memory cell to be
The full-swing write signal is stored in the information storage capacitor Cs.
A charge equivalent to that of the write operation by the signal is injected.
FIG. 3 shows the clear operation of the dual port memory of FIG.
A timing diagram for one embodiment of a working mode is shown. same
In the illustrated embodiment, the input / output terminals IO1 and IO2 are paired.
Do not mask the clearing operation of the corresponding bit.
Of the bits corresponding to the input / output terminals IO3 and IO4
The clear operation is masked. In addition, the selected memory
Connected to the non-inverted signal line of the corresponding complementary data line.
The memory cell has a memory "0" storage data by that time.
If the data is held, it is indicated by the solid line and the logical "1"
The dotted line shows the case where the stored data is held.
There is. Writes written in clear operation mode
The data d1 and d2 are both set to logic "1". book
Other combinations of imprinted data and stored data
Should be inferred by this example. According to FIG. 3 below,
The clear operation mode of the dual port memory of this embodiment is
Outline the mode. In Figure 3, dual po
The row memory strobe signal RASB
Caused by changing from high level to low level
Be moved. This row address strobe signal RASB
Prior to the falling transition, the write enable signal WE
B and data transfer control signal DTB / OEB are low level
It is said that This allows the dual port memory to
Determine that this memory cycle is in clear operation mode
Set. Fall of row address strobe signal RASB
Select external terminals A0 to Ai prior to the change in sharpness
The row address ra of the word line is supplied. In and out
A logic "0", that is, a low
Bell mask data is supplied, and input / output terminals IO3 and
IO4 has logic "1", that is, high-level mask data
Data is supplied. In dual port memory,
Address strobe signal RASB is set to low level
As a result, the timing signal φpc is set to the low level,
Sometimes the timing signals φar and φmw temporarily go high.
It is considered a bell. If the timing signal φpc is low level
The complementary data lines D0 / D0B to Dn / DnB
And complementary common data lines CD1, CD1B to CD4, CD
The precharge operation of 4B is stopped. Also, thymin
If the driving signal φar is temporarily set to high level,
C Address is stored in row address buffer RADB
Timing signal φmw temporarily goes high.
By doing so, 4-bit mask data is randomly input / output.
It is taken into the mask register MR of the input circuit RIO. Next
After a predetermined time has passed, the data transfer control signal DTB / OE
B is returned to high level and the column address strobe signal
The signal CASB is set to low level. This column address
Prior to the falling transition of the strobe signal CASB,
Input / output terminals IO1 and IO2 are both written with logic "1"
Embedded data d1 and d2 are supplied. At this time,
Force terminals IO3 and IO4 are don't cares. book
The imprint data d1 and d2 are the random input / output circuit RI.
O input buffers IB1 and IB2 provide complementary signals
The corresponding write amplifiers WA1 and WA2.
Supplied. In dual port memory, column
Dress Strobe CASB goes low
Therefore, the timing signal φad is temporarily set to high level.
The timing signal φad to be included in the timing signal φad.
The minging signal φrw is temporarily set to the high level. Well
Also, the timing signals φad and φrw are both low level.
When the timing signal φx goes high,
And the timing signal φpa goes high after a short delay.
To be done. Timing signal φad temporarily goes high
The random access port column
The dress decoder RCD is activated and all data
Data line selection signals Y0 to Yn are synchronized with timing signal φad
Then, the selected state of the high level is temporarily set. By this
All the column switches CSW1 to CSW4.
MOSFETs Q5, Q6 to Q7, Q8 are in the ON state.
All complementary data lines D0.D of each memory array
0B to Dn / DnB correspond to complementary common data CD1 /
Random input / output times via CD1B to CD4 / CD4B
Connected to the corresponding write amplifiers WA1 to WA4 of the path RIO
To be done. Temporarily delayed after timing signal φad
The timing signal φrw that is set to the level I is
Write-out according to the mask data taken in
Selectively transmitted to the pumps WA1 and WA2. By this
The write amplifiers WA1 and WA2 are activated,
Complementary common data lines CD1, CD1B and CD2, CD2
B has a logic "1" according to the write data d1 and d2.
Complementary write signals are supplied. At this time,
Pump WA1 and WA2 have high level of timing at the same time.
Since the write signal φad is supplied, the write amplifier WA1 and
And the complementary write signals output from WA2 are memory cells.
The read level is set to a level as small as the read signal. Sanawa
The level of the non-inverted signal lines CD1 and CD2 is half
For example, about 200 mV higher than the recharge level
The levels of the inverted signal lines CD1B and CD2B are
Level of about 200 mV lower than the precharge level
It is considered to be Le. The write amplifiers WA3 and WA4 are compatible
The mask data to be set to the low level of logic "0"
Therefore, it is not activated. Write amplifiers WA1 and W
A minute level complementary write signal is supplied from A2.
And the memory arrays M-ARY1 and M-ARY
2 complementary data lines D0 / D0B to Dn / DnB
Of the corresponding complementary common data line CD1
-Phase supplied via CD1B and CD2-CD2B
It is set to the level of the supplementary write signal. This allows the memory
All complementary data of arrays M-ARY1 and M-ARY2
The level of the non-inverted signal line is half precharge
Inverted, for example, about 200 mV higher than the level
The signal line level is lower than the half precharge level, for example
The level is about 200 mV lower. At this time, the mask
Complementary common data lines CD3 and CD3 corresponding to the selected bits
B and CD4 / CD4B and memory array M-ARY3 and
And all complementary data lines D of the memory array M-ARY4
The level of 0D0B to DnDnB is half
Be left at the high level. Timing signal φad and
Both φrw are returned to low level and timing is changed
By setting the signal φx to the high level, the row address
The word line selection operation by the coder RD is started, and the memory
Row address ra of arrays M-ARY1 to M-ARY4
One word line corresponding to the
Is selected. This allows for each memory array
This complementary data line D0 / D0B to Dn / DnB
From n + 1 memory cells coupled to the word line
According to the data stored and stored in the
A minute read signal having a width is output. this
At this time, as shown by the solid line in FIG.
Read logic "0" from the memory cell connected to the inverted signal line.
When the protruding signal is output, the non-inverted signal of the complementary data line
Line levels were canceled out and almost half precharge level
Returned to Vcc / 2. In contrast, complementary data lines
The level of the corresponding inversion signal line of
Than half precharge level without being
It remains at about 200 mV lower level. On the other hand, with this
Then, as shown by the dotted line in FIG.
Read logic "1" from memory cell connected to signal line
When output signal is output, non-inverted signal of complementary data line
The read signal level is superimposed on the line level,
About 400 mV higher than the precharge level
To be done. Level of corresponding inverted signal line of complementary data line
Is also half-pressed without being affected by the read signal.
Remains about 200mV lower than the recharge level
It is said that That is, after the word line selection operation is completed
The non-inverted signal line and inverted signal line of each complementary data line
Has a level difference depending on the corresponding write data.
Be done. This level difference has a maximum value of about 600 m, for example.
V and its minimum value is about 200 mV. Taimi
Timing signal φpa goes high, slightly behind the timing signal φx.
When set to level, all sense amplifiers SA1 to SA4
All the unit amplifier circuits are activated simultaneously. By this
Each word line in each memory array
The level difference on the complementary data lines is rapidly magnified and goes high.
It is a binary signal of level or low level. Complementary data
The level difference between the non-inverted signal line and the inverted signal line
Memory array M-AR
Selected n + 1 memory cells of Y1 and M-ARY2
Stored data is new write data d1 and d2.
Will be rewritten all at once. By the way, clear operation
Array M-ARY3 and M-AR in which mask is masked
Each complementary data line of Y4 outputs from each memory cell.
A level difference occurs according to the minute read signal. these
Of the sense amplifiers SA3 and SA4
Each unit amplifier circuit of
The stored data stored in the memory cell is refreshed. that's all
The dual port memory of this embodiment is
Rewrite data stored in memory cells in units of word lines
With clear function. Smell in this clear operation mode
The complementary data lines D0, D0B to Dn of each memory array.
・ DnB temporarily selects all before selecting word lines.
Is selected and output from the write amplifiers WA1 to WA4.
The level of the complementary write signal applied is output from the memory cell.
It is considered as a minute level equal to or higher than the read signal
It The write amplifiers WA1 to WA4 are provided with a previously supplied master.
Since it is selectively activated according to the
Perform maskable clear processing according to the desired color display.
I can. Also, at this time, the masked memory
To prevent fluctuations in the level of complementary data lines in the array,
Precharge level of complementary data line and complementary common data line
Both are half pre-charge like power supply voltage Vcc / 2
It is considered as a page level. This allows the dual of this example
In the case of the port memory, for example, an image frame buffer
Realizes a high-speed and stable clear function that matches the memory function
It is possible. Needless to say, these features
It can also be used for simultaneous write operations other than rear
It As shown in the above embodiment, the present invention is
When applied to semiconductor memory devices such as Al port memory
In this case, the following effects can be obtained. That is, (1) Set the clear operation mode to the data line all selected state.
The write amplifier in units of word lines.
Select all word lines and then open word line
By temporarily putting it in the operating state until it is started,
Clearing of semiconductor memory devices such as dual port memory
The operation mode can be accelerated and the level of the write signal can be increased.
It is possible to obtain the effect that the rule can be set arbitrarily. (2) In the above clear operation mode, write amplifier
Level of the complementary write signal output from the memory cell
By setting the level to be equal to or higher than the read signal,
Clearing of semiconductor memory devices such as dual port memory
The write current in the working mode is significantly reduced, and the low
An effect that power consumption can be achieved can be obtained. (3) Multiple input terminals in the clear operation mode
A plurality of write amplifiers provided corresponding to
Selective operation according to the mask data
For example, a maskable mask corresponding to the color factor.
(A) The effect that the operation can be executed is obtained. (4) Set the above clear operation mode to dual port memo
Via a random access port
With dual port memory serial access
Example in parallel with serial input / output operation by port
For example, do not clear the memory cell while displaying an image.
That is, for example, you can change the background color of the displayed image at the same time.
The effect that can be obtained is obtained. (5) Each memory array in the above clear operation mode
The same precharge level for the data line and common data line
Corresponding to the bits to be masked.
Prevents fluctuations in the level of the data lines in the memory array and stabilizes
The effect that the clear operation mode can be realized is obtained.
It (6) The image frame according to the above items (1) to (5)
Suitable for buffer memory etc., high speed and stable clear function
Memory device such as dual port memory having
The effect that can be realized is obtained. The invention made by the present inventors has been described based on the embodiments.
Although described physically, the present invention is limited to the above embodiment
It is not a matter of course, and various changes can be made without departing from the gist of the matter.
Needless to say. For example, the du
In the al port memory, the write enable signal WE
B and data transfer control signal DTB / OEB are low level
After that, the row address strobe signal RASB goes low.
The clear operation mode is identified by setting the level.
However, for example, a special control for specifying the clear operation mode
Control signals may be provided, and control signals may be any combination.
You can In addition, in the clear operation mode,
Of the complementary write signal output from the right amplifier
Must be the same as the read signal level of the memory cell.
No need to cancel read signal of memory cell and need
It may be any level that can leave a large level difference.
In this embodiment, according to the mask data, the write amplifier W
Although A1 to WA4 are selectively activated, for example,
The column address data for the random access port in Fig. 1
The NAND gate circuits NAG3 to NAG4 of the coder RCD
Provided for each memory array, these NAND gate circuits
Mask the timing signal φad to the other input terminal
According to each memory array phase.
Select all complementary data lines according to mask data
It is also good to In addition, these mask data are
Independent memory cycle to supply the data
Therefore, it is supplied to dual port memory.
May be used, or external terminals other than the input / output terminals IO1 to IO4
It may be supplied from a child. In addition, input / output
Terminals, common data lines, write amplifiers, memory arrays, etc.
8 may be provided in 8 or more sets, as shown in FIG.
Of random input / output circuit RIO and its peripheral circuits
The physical circuit configuration and the dual port memory shown in Figure 2
Memory block configuration and set of control signals shown in FIG.
Various embodiments such as matching can be adopted. In the above explanation
The background is the invention mainly made by the present inventor.
Applied to dual port memory
However, it is not limited to this.
, Various semiconductors such as normal dynamic RAM
It can also be applied to body storage devices. The present invention is based on at least each data
Semiconductor memory in which a sense amplifier is provided corresponding to the data line
Device and digitizer incorporating such a semiconductor memory device
It can be widely applied to electronic devices.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the clear operation mode is executed in word line units with the data lines of the memory array being in the all-selected state. At this time, the write amplifier is operated from the all-selected state of the data lines to the start of the word-line selecting operation. During this time, the write signal output from the write amplifier is made into a complementary signal and the level is set to a minute level that is equal to or higher than the read signal of the memory cell, and semiconductors such as dual port memory are provided. The clear operation mode of the storage device can be speeded up and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a random input / output circuit of a dual port memory to which the present invention is applied and its peripheral circuit.

FIG. 2 is a block diagram showing an embodiment of a dual port memory including the random input / output circuit of FIG.

FIG. 3 is a timing diagram showing an example of a clear operation mode of the dual port memory of FIG.

[Explanation of symbols]

RIO ... Random input / output circuit, M-ARY1 to MA
RY4 ... memory array, SA1 to SA4 ... sense amplifier, CSW1 to CSW4 ... column switch, RCD ...
Random access port column address decoder, RD ... Row address decoder, WA1-WA4 ...
Write amplifier, RA1 to RA4 ... Read amplifier, IB
1-IB4 ... Input buffer, OB1-OB4 ... Output buffer, MR ... Mask register, USA1-USA2 ...
..Sense amplifier unit amplification circuit, Cs ... Information storage capacitor, Qm ... Address selection MOSFET, Q1 ...
P-channel MOSFET, Q2-Q12 ... N-channel MOSFET, N1-N3 ... Inverter circuit, N
AG1 to NAG4 ... NAND gate circuits, NOG1 to N
OG4 ... NOR gate circuit, DR1 to DR4 ... Data register, DSL1 to DSL4 ... Data selector, PN
T ... pointer, AL ... address latch, SCD ... serial access port column address decoder,
SIO ... Serial input / output circuit, FC ... Function control circuit,
CADB ... column address buffer, RADB ... row address buffer, AMX ... address multiplexer, REFC ... refresh address counter, TC.
..Timing control circuits

Claims (11)

[Claims] 1. A plurality of data line pairs, a plurality of word lines,
A plurality of memory arrays each including a plurality of dynamic memory cells provided at the intersections of each word line and each data line pair, and for amplifying the potential difference between each data line pair to obtain a logic high level or a logic low level A plurality of sense amplifiers, a plurality of common data line pairs provided corresponding to each memory array, and a plurality of common data line pairs provided corresponding to each memory array and selectively between the common data line pair and the data line pair. A plurality of switch means for coupling to each other, a plurality of write amplifiers provided corresponding to each common data line pair, and a control means for selectively operating one of the plurality of write amplifiers, The write signal externally input by the write amplifier selected in the operating state by the control means is transferred to the common data line pair corresponding to the write amplifier. The emission state via the said switch means brought supplied to the data line pair, then by the sense amplifiers operating state semiconductor memory device characterized by allowed to amplifying the write signal. 2. In the semiconductor memory device, when the memory cell is in a non-selected state, the plurality of data line pairs and the common data line pair are set to substantially the same potential level by a precharge circuit. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor memory device according to claim 2, wherein the same potential level is a potential level approximately in the middle between the logic high level and the logic low level. 4. A semiconductor memory device according to claim 1, wherein the operation of the switch means is performed prior to the operation of selecting the word line. 5. The semiconductor memory device according to claim 4, wherein the sense amplifier is operated after the word line is selected. 6. The stored information of a dynamic memory cell coupled to a selected word line in a memory array corresponding to a write amplifier inactivated by the control means is refreshed. 2. A semiconductor memory device according to claim 1. 7. The word line in the memory array corresponding to the write amplifier which has been made active by the control means and the word line in the memory array corresponding to the write amplifier which has been made inactive are almost at the same timing. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is in a selected state. 8. A memory array corresponding to a write amplifier activated by said control means, said switch means being turned on, and said write signal amplified by a plurality of sense amplifiers is applied to a selected word line. 2. The semiconductor memory device according to claim 1, wherein data is written in a plurality of coupled memory cells. 9. The semiconductor memory device according to claim 1, wherein the control means holds information indicating an operating state or a non-selected state of the plurality of write amplifiers by the storage means. . 10. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a serial access port and a random access port. 11. The semiconductor memory device includes a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, and a third external terminal for receiving input data or output data. And receiving data for controlling the operation of the write amplifier from the third external terminal in response to the fall of the signal supplied to the first external terminal. 11. The semiconductor memory device according to claim 1, wherein any one of them is selectively operated.