JPH06314974A - Method and device for d/a conversion - Google Patents

Abstract

PURPOSE:To provide the D/A converter in which second harmonic distortion in an output signal of the D/A converter circuit is suppressed and production of an undesired signal for a desired frequency band is prevented. CONSTITUTION:A delay by one D/A conversion clock (CLK) is given to a video signal (DVBS) given to a latch circuit 11 synchronously with a D/A conversion clock. An adder circuit 12 adds the DVBS and an output signal of the latch circuit 11. Multiplier circuits 13,14 multiply signals received from both input terminals. A bit switch 15 is a switch to set a coefficient A. A delay circuit 16 is a circuit to provide a delay to the DVBS synchronously with the CLK thereby compensating the delay produced each section above. The DVBS is corrected before conversion through the processing above to cancel distortion produced by D/A conversion and a signal component produced newly by the correction with each other thereby decreasing distortion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog conversion method and apparatus for correcting an input signal in a digital format before conversion to suppress the occurrence of distortion in an output signal in an analog format.

[0002]

2. Description of the Related Art It has been general practice to digitally convert a high frequency signal, for example, a video signal of NTSC system or PAL system, and perform various image processing or recording. When processing as a digital format signal or displaying a recorded video signal on a CRT monitor device, the digital format video signal is D / A converted by a digital / analog (D / A) conversion IC or the like. It is converted and supplied to the CRT monitor device.

In this D / A conversion, the characteristic of the D / A converting IC is ideal, that is, the output characteristic of the D / A converting IC is completely proportional to the value of the input digital signal, and If the slew rate is infinite, I for D / A conversion
The output signal before band limitation by the C low-pass filter is completely stepped, and no distortion occurs in the video signal after band limitation.

However, in reality, the output signal of the D / A conversion IC is not perfectly stepped and is not perfectly proportional to the input digital signal. The actual output signal of the D / A conversion IC will be described. For convenience of explanation, this D / A conversion IC performs linear D / A conversion as shown in the figure,
A case where the input digital signal changes by one bit for each sample period will be described.

FIG. 7 shows a conventional I / A for D / A conversion.
It is a figure which shows the output characteristic of C. In FIG. 7, (A)
Is D / A when the slew rate is assumed to be infinite.
It is a figure which shows the actual linearity of conversion IC, (B) is
It is a figure which shows the actual slew rate of the IC for D / A conversion when the linearity is assumed to be ideal. here,
If there is a deviation between the ideal output signal and the actual output signal,
The ideal signal is shown by the dotted line and the actual signal is shown by the solid line.

As shown in FIG. 7A, a D / A conversion I
When the output characteristic of C is not perfectly linear with respect to the input signal, a difference occurs with respect to the ideal output signal as indicated by a and b in the figure. Due to such non-linearity of the output signal characteristics, the signal waveform becomes vertically asymmetric when viewed in terms of alternating current, so that a harmonic such as a second harmonic is generated and distortion occurs.

Further, as shown by adding c and d in FIG. 7B, when the slew rate characteristic of the D / A conversion IC is different between the rising edge and the falling edge of the signal, that is, the angle e shown in the figure. And the angle f are different, the output signal waveform becomes asymmetric in the time axis direction, so that a second harmonic is generated and distortion occurs.

[0008]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When the D / A conversion is performed by the conversion IC, the D / A conversion clock and the harmonic signal are converted due to their non-linearity (the harmonic signal is folded back by the clock signal), and the D / A conversion I
There is a problem that an unnecessary signal is generated in the pass band of the low-pass filter after C.

This problem is particularly noticeable when the video signal contains a subcarrier signal (SC). The harmonic component of this subcarrier signal (SC) is folded back by the D / A conversion clock and is a low-pass filter. , The unnecessary signal components interfere with the original subcarrier signal (SC) or its harmonics to generate a beat signal, resulting in deterioration of image quality.

The distortion caused by the output characteristic of the D / A conversion IC can be reduced by bringing the output characteristic of the D / A conversion IC close to the ideal characteristic. However, at present, in a conversion speed required for handling a video signal, for example, a D / A conversion IC operating at a clock frequency of 13.5 MHz, linearity characteristics capable of sufficiently suppressing distortion, and However, there is a problem that it is difficult to realize a D / A conversion IC having a slew rate characteristic.

In order to reduce the distortion, there is a method of performing D / A conversion by using a conversion clock having a frequency twice that of a normal frequency, but a circuit for performing oversampling with a clock twice the frequency is required, Also, double the operating frequency of D
Since it is necessary to use an A / A conversion IC, the amount of hardware increases, and the device becomes expensive.

The present invention has been made in view of the above-mentioned problems of the prior art, and suppresses, for example, the generation of second harmonics and the distortion caused by them, which occur in the output signal of the D / A conversion circuit, It is an object of the present invention to provide a digital / analog conversion device capable of preventing generation of unnecessary signals in a desired frequency band.

[0013]

In order to achieve the above object, the digital / analog conversion device of the present invention is provided with a correcting means before the digital / analog converting means, which corrects the digital input signal. A correction process for compensating the conversion characteristic of the digital / analog conversion means is performed by a time-series process to suppress the occurrence of distortion.

Further, the correction means includes the digital / digital
It further has setting means for setting the coefficient obtained corresponding to the conversion characteristic of the analog conversion means, and a low-pass filter for performing a predetermined band limitation on the output signal, and adapted to the amplitude characteristic and phase characteristic of the distortion component. The above-mentioned correction processing is performed.

Further, the correction means further includes means for selecting any one of the time-series input signals for the input signal in accordance with the conversion characteristic, and the amplitude characteristic and the phase characteristic of the distortion component are selected. It is characterized in that the adapted correction processing is performed.

In the digital / analog conversion method of the present invention, a time series digital input signal is subjected to digital / analog conversion after correction for compensating for distortion caused by the digital / analog conversion is given in advance. / Outputs the signal after analog conversion after applying a predetermined band limitation.

[0017]

The digital input signal is subjected to correction processing corresponding to the harmonic distortion generated in the D / A conversion circuit, and D / A conversion is performed.
The harmonic components generated by the A conversion are canceled to suppress the generation of distortion and the generation of unnecessary signals. Further, the generation of distortion or the like is suppressed by selecting a signal to be used for the compensation processing and optimizing this processing according to the distortion characteristic of the D / A conversion circuit using the coefficient used for the correction processing. Enhance the effect.

[0018]

EXAMPLE A first example of the present invention will be described below. The digital / analog converter (D / A converter) 1 of the present invention is used for inputting a digital video signal (DV).
BS) is corrected in advance to suppress the harmonic distortion generated in the digital / analog conversion circuit (D / A conversion circuit) 3, and this correction and the harmonic distortion generated in the D / A conversion circuit 2 are cancelled. In particular, it suppresses the generation of unnecessary signals relating to the subcarrier signal (SC) component.

FIG. 1 is a diagram showing the configuration of a D / A converter 1 of the present invention. In FIG. 1, a DSP 2 is composed of, for example, a signal processor for signal operation and its peripheral circuit, and is inputted as a digital video signal (DVB).
S) corresponds to the harmonic distortion generated in the D / A conversion circuit 3, and a correction process for canceling it is performed. Here, the video signal (DVBS) includes a video signal (V), a blanking signal (B), a synchronizing signal (S), and a subcarrier signal (SC).

The D / A conversion circuit 3 converts the video signal (DVBS) corrected by the DSP 2 into a D / A conversion clock (C).
D / A conversion in synchronization with LK). The low pass filter (LPF) 4 is an analog low pass filter, and
Regarding the output signal of the / A conversion circuit 3, the D / A conversion frequency f _CLK (= frequency of the D / A conversion clock (CLK))
The frequency is halved as the cutoff frequency to limit the band. D
In the A / A converter 1, the digital signal is
For example, it is handled and processed with a 10-bit width.

FIG. 2 shows a harmonic canceller (H which realizes the processing of the DSP 2 in the first embodiment by hardware.
It is a figure which shows the structure of C) 5. In FIG. 2, the latch circuit 11 latches the video signal (DVBS) input in synchronization with the D / A conversion clock (CLK). The latch circuit 11 delays the video signal (DVBS) by the 1D / A conversion clock (CLK).

The adder circuit 12 outputs the video signal (DVBS) input from the input terminal a and the output signal of the latch circuit 11 input from the input terminal b in synchronization with the D / A conversion clock (CLK). Add and output from the output terminal x. The multiplication circuits 13 and 14 are signals that are input from the input terminal a in synchronization with the D / A conversion clock (CLK).
Also, the signal input from the input terminal b is multiplied and output from the output terminal x.

Here, in the multiplication circuit 13, the output of the addition circuit 12 is input to both input terminals a and b, and the output signal of the addition circuit 12 is squared. Further, the multiplication circuit 14 has a coefficient A input from the bit switch (SW) 15 to the input terminal a,
Also, the output signal of the multiplication circuit 13 input to the input terminal b is multiplied.

The bit switch 15 is a switch in which the coefficient A used for multiplication in the multiplication circuit 14 is set.
The coefficient A can take both positive and negative values. The delay circuit 16 is
Video signal (DVBS) D / A conversion clock (CL
K) is a circuit that gives a delay in synchronization with K) and compensates for the delay caused by the processing in the latch circuit 11 to the multiplication circuit 14.

The adder circuit 17 adds the output signal of the multiplier circuit 14 input to the input terminal a and the delay circuit 16 input to the input terminal b in synchronization with the D / A conversion clock (CLK). . Even in the harmonic canceller 5,
Similar to the D / A converter 1, a digital signal is handled with a 10-bit width, for example.

The operating principle of the D / A converter 1 and its operation will be described below with reference to the drawings. The second harmonic distortion generated in the subcarrier signal (SC) can be expressed by the following equation.

[Number 1] G [x _SC (t)] _{= x SC (t) + k} SC · x SC 2 (t-α ') = x SC (ω SC t) + k SC sin2ω (t-α) ··· ( 1) However, G [x _SC (t)] is a subcarrier signal (SC)
Second harmonic distortion, x _SC (t) is the subcarrier signal (SC), ω _SC is the angular frequency of the subcarrier signal (SC), k _SC is a coefficient indicating the strength of the second harmonic component, α is
It is the phase difference between the second harmonic component and the subcarrier signal (SC).

When the output characteristic of the D / A conversion circuit 3 has no second-order distortion, the component of the second term on the right side of the equation 1 is the D / A conversion circuit 3.
It is cut off by and does not appear in the output of the D / A converter 1. D /
When the output characteristic of the A conversion circuit 3 has second-order distortion, the subcarrier signal (SC) and its second-order harmonic component are D
The distortion component whose frequency is converted (folded back) by the / A conversion clock (CLK) is added to the equation 1. Taking this signal component into consideration, the second harmonic distortion of the subcarrier signal (SC) is expressed by the following equation.

[0028]

[Number 2] G [x _SC (t)] _{= x SC (ω SC t)} + k SC sin2ω (t-α) + sin (ω CLK -ω SC) t + k SC sin (ω CLK -2ω SC) · (t −α) + ... (2) where ω _CLK is the angular frequency of the D / A conversion clock (CLK).

Here, the normal D / A conversion clock (CL
The frequency f _{CLK of} K) is 13.5 MHz, and the frequency f _SC of the subcarrier signal (SC) is 3.58 MHz. Therefore, the distortion component of the fourth term on the right side of Expression 2 having a frequency lower than the cutoff frequency of the low-pass filter 4 becomes a problem. That is, the frequency of this component is as follows.

[0030]

Equation 3 Equation 2 of the right side of the fourth term frequency _{= (ω CLK -2ω SC) /} 2π = f CLK -2 × f SC = 6.34 (MHz) <f CLK / 2 ··· (3)

Therefore, this distortion component passes through the low-pass filter 4 and appears in the output video signal (AVBS).

FIG. 3 is a diagram showing a frequency spectrum when the video signal (DVBS) is D / A converted only by the D / A conversion circuit 3 and the low pass filter 4 at a conversion frequency of 13.5 MHz. Unwanted signals such as the above-described 6.34 MHz distortion component are generated in the range indicated by a in the figure.

In reality, the 6.34 MHz distortion component is D
A clock for D / A conversion (C
It is further folded back by a signal having a frequency (6.75 MHz) that is half that of LK), and a distortion component of 7.16 MHz is generated. This 6.34MHz distortion component and 7.16MH
z distortion component and 2 of subcarrier signal (SC)
The double harmonic component and the 7.16 MHz distortion component interfere with each other to generate a beat signal, resulting in deterioration of the quality of the output video signal (AVBS).

If the distortion component of 6.34 MHz is suppressed,
The distortion component of 7.16 MHz is also reduced, and the distortion component of 7.16 MHz and the subcarrier signal (S
The beat signal due to the interference between the second harmonic components of C) is also suppressed. Therefore, the generation of the distortion component of 6.34 MHz is suppressed by performing the correction process on the video signal (DVBS).

The DSP 2 is placed in front of the D / A conversion circuit 3, and the input video signal (DVBS) is corrected by the following equation.

[0036]

Equation 4] _{X n '= X n + A} · [X _n -X _n-1] ² .... (4) where, X _n', the correction in the period n of the D / A conversion clock (CLK) Video signal after processing (DVBS), X _n
Is a video signal (DVBS) before correction processing in a cycle n of the D / A conversion clock (CLK), A is a correction coefficient, and X _n-1 is a cycle of the D / A conversion clock (CLK). It is a video signal (DVBS) before correction processing in n-1.

When the corrected video signal (DVBS) is input to the D / A conversion circuit 3, its output signal is represented by the following equation.

[0038]

[Number 5] G [x _SC '(t)] = x _SC (t) + A _{[x SC (t) -x SC (} t-T) ] ^{_{2 + k SC' · x SC}} 2 (t-α ') + A _{· k SC '· x SC (} t) _{[x SC (t) -x SC (} t-T) ] ² + k _SC' ² _{[x SC (t) -x SC (} t-T) ] ⁴ ( 5) where T is the cycle of the D / A conversion clock (CLK),
k _SC 'is a coefficient indicating the strength of the harmonic component.

Here, for k _SC 'and A, k _SC '<<
1 and A << 1, the fourth term on the right side, 5
Terms can be ignored. Therefore, on condition that the following expression is satisfied, correction processing is performed in advance so as to generate a second harmonic component that cancels a second harmonic generated in the D / A conversion circuit 3 with respect to the input signal. It is possible to cancel the second harmonic distortion of the subcarrier signal (SC) generated in the conversion circuit 3.

[0040]

[6] A _{[x SC (t) -x SC (} t-T) ] ^{_{2 + k SC '· x SC}} 2 (t-α') = 0 ··· (6)

Actually, the only value that can be arbitrarily set in the equation 6 is the coefficient A, and the phase of the D / A conversion clock (CLK) is changed by 0 ° by changing the sign of the value of the coefficient A.
Also, it is possible to cancel the unnecessary signal for 180 °. On the other hand, since both terms on the left side of Expression 6 have a phase difference α ′ on the time axis, the right side of Expression 6 is not completely zero.
However, the unnecessary signal at 6.34 MHz described above can be suppressed by bringing the right side of Expression 6 as close to 0 as possible. Here, regarding Expression 6, as shown in Expression 2,

[0042]

## EQU00007 ## x _SC (t) = sin ω _SC t (7)

By substituting for, the following equation is obtained.

[0044]

[Equation 8] A _{[sinω SC (t) -sinω SC (} t-T) ] ^{_{2 + k SC '· sin 2}} ω SC (t-α') = 0 ··· (8)

Equation 8 The following equation is obtained by sequentially transforming the left side.

[0046]

Equation 9] _{A {2cosω SC (t-T} / 2) · sinω SC T / 2} 2 = A · cos 2 ω SC (t-T / 2) · 2sin 2 ω SC T / 2 = A {1 + cos2ω SC (t-T / 2)} · (1-cosω SC T) ··· (9)

Equation 8 The following equation is obtained by sequentially modifying the right side.

[0048]

[Number 10] ^{_{k SC '· sin 2 ω SC}} (t-α') = k SC '{1-2cos2ω SC (t-α')} / 2 ··· (10)

By substituting equations 9 and 10 into equation 8, the following equation is obtained.

[0050]

Equation 11] _{A {1 + cos2ω SC (t} -T / 2)} · (1-cosω SC T) + k SC '{1-2cos2ω SC (t-α')} / 2 = 0 ··· (11)

[0051] Here, a cos .omega _SC T and k _SC 'is a constant, the second harmonic component is assumed to fully canceled, the following equation is obtained.

[0052]

[Number 12] _{A (1-cosω SC T)} + k SC '/ 2 = 0 ··· (12)

The left side of Expression 12 shows the error of the DC component of the video signal (DVBS).

Further, by modifying the equation 11, the following equation is obtained.

[0055]

[Number 13] _{A (1-cosω SC T)} · cos2ω SC (t-T / 2) + k SC '· cos2ω SC (t-α') / 2 = 0 ··· (13)

The left side of the equation 13 shows the amount of the second harmonic, and when the equation 13 is satisfied, the second harmonic is completely canceled. The value of the coefficient A can be calculated or actually measured based on the output characteristics of the D / A conversion circuit 3.

The operation of the D / A converter 1 will be described below with reference to FIG. 10 input to the D / A converter 1
Bit digital format video signal (DVBS) X
_n-1 is sequentially input to the DSP 2. Here, the subscript n-1 attached to X indicates the video signal (DVBS) of the (n-1) th cycle of the D / A conversion clock (CLK).

The DSP 2 receives the input video signal (DVB
S) Clock for D / A conversion (CLK) for X _n-1
Give a delay of one cycle. A video signal (DVBS) X _n-1 given the delay for the next D / A conversion clock (CLK) cycle of the video signal (DVBS) X _n performs correction processing of the following equation, the corrected To obtain the video signal X _n '.

[0059]

[Number 14] _{X n '= X n + A} · [X _n -X _n-1] ² (14)

The corrected video signal X _n 'is D / A converted by the D / A conversion circuit 3 and output as a stepwise waveform. The stepwise output signal of the D / A conversion circuit 3 is band-limited by the low-pass filter 4 and output as an analog output video signal (AVBS).

In the DSP 2, since the input video signal (DVBS) is corrected as described above, the 6.34 MHz unnecessary signal is less likely to occur in the output video signal (AVBS). FIG. 4 is a diagram for explaining the effect of the D / A conversion device 1. The range indicated by a in FIG. 4 is
FIG. 3 is an enlarged view of the signal waveform in the range indicated by a in FIG. 3, in which the output signal of the D / A conversion device 1 is shown by a solid line, and
The waveform after D / A conversion when no correction processing is performed on the video signal (DVBS) according to No. 2 is shown by a dotted line.

By applying a correction process to the video signal (DVBS) input to the D / A conversion circuit 3 in advance by the DSP 2, unnecessary signals generated at 6.34 MHz and 7.16 MHz can be suppressed, and further, these signals can be suppressed. It is possible to suppress the beat signal generated between the signals and between the second harmonic of the subcarrier signal (SC) and improve the quality of the output video signal (AVBS).

Since the calculation shown in Expression 14 is relatively simple, it can be replaced with hardware processing. The harmonic canceller 5 is used by replacing it with the DSP 2 in the D / A converter 1, and performs the correction process of Expression 14 on the input video signal (DVBS).

The operation of the harmonic canceller 5 will be described below. The video signal (DVBS) X _n-1 input to the harmonic canceller 5 is 1D /
A delay corresponding to the A conversion clock (CLK) cycle is given. Therefore, in the next D / A conversion clock cycle,
The video signal (DVBS) X is input to the input terminal a of the adder circuit 12.
_n and the video signal (DVBS) X _n-1 are input to the input terminal b, and the adder circuit 12 calculates the following equation.

[0065]

X ₁ = X _n + X _n-1 (15)

The output signal of the addition circuit 12 is the multiplication circuit 13
Are input to the input terminals a and b, and the operation of the following equation is performed.

[0067]

## EQU16 ## X ₁ ² = (X _n + X _n-1 ) ² (16)

The count A is input to the input terminal a of the multiplication circuit 13, the output of the multiplication circuit 13 is input to the input terminal b, and the operation of the following equation is performed.

[0069]

AX ² = A (X _n + X _n-1 ) ² (17)

On the other hand, in the delay circuit 16, the latch circuit 11
The delays that occur in .about.14 are compensated, the output of the multiplication circuit 14 is input to the input terminal a of the adder circuit 17, the video signal (DVBS) _Xn is input to the input terminal b, and the operation of the following equation is performed. .

[0071]

X '= X _n + A (X _n + X _n-1 ) ² (18)

As described above, the harmonic canceller 5
It is also possible to perform the correction processing equivalent to that of the DSP 2.

The preferred method of use is to construct the harmonic canceller 5 as one IC and place it in front of the D / A conversion circuit 3. Further, it is more preferable to form the IC together with the circuit of the D / A conversion circuit 3 as one IC.

The second embodiment of the present invention will be described below.
The D / A converter 6 of the present invention converts an analog format image signal corresponding to three primary colors of red (R), green (G), and blue (B) light into an analog format output video signal (AVBS). ) A device that generates a signal.

FIG. 5 shows the D of the present invention in the second embodiment.
It is a figure which shows the structure of the / A converter 6. In FIG.
The encoder 7 is a digital format video signal (DVBS) based on the input digital format RGB signal.
Convert to. The parts other than the encoder 7 are the same as the parts indicated by the same reference numerals in the D / A converter 1.

The operation of the D / A converter 6 of the present invention will be described below. The digital format RGB signal input to the D / A converter 6 of the present invention,
It is synthesized by digital operation processing, and the blanking signal and the synchronization signal are added to the video signal (DVB
It is output as S).

In the harmonic canceller 5, the input video signal (DVBS) X _n is subjected to the correction processing shown in Expression 18, and is input to the D / A conversion circuit 3. The D / A conversion circuit 3 D / A converts the output signal of the harmonic canceller 5 and inputs it to the low pass filter 4.

The low-pass filter 4 includes the D / A conversion circuit 3
Output signal is output as an output video signal (AVBS). By configuring the D / A conversion device 6 as described above, the correction processing according to the present invention can be performed on the RGB image signal, and the output video signal (AVBS) is obtained.
It is possible to improve the quality of.

The third embodiment of the present invention will be described below.
FIG. 6 is a diagram showing the configuration of the harmonic canceller 8 of the present invention in the third embodiment. The harmonic canceller 8 differs from the harmonic canceller 5 in that the latch circuit 11 is preceded by the same latch circuit 18 and the selector 19 is preceded by an adder circuit 12.
With this configuration, in addition to the coefficient A, the video signal (DVBS) before and after being used for the hydrochloric acid treatment can be changed to perform the phase adjustment.

In FIG. 6, the latch circuit 18 has a D / A
The input video signal (DVBS) is latched in synchronization with the conversion clock (CLK), delayed by the 1D / A conversion clock (CLK), and output. In the selector 19, the output signal of the latch circuit 11 is input to the input terminal a and the output signal of the latch circuit 18 is input to the input terminal a, and one of these is selected and output to the output terminal x. The output terminal x is connected to the input terminal b of the adder circuit 12. The parts other than those described above are the same as the parts to which the same reference numerals are attached for the harmonic canceller 5.

In the adder circuit 12, the video signal (DVBS) X _{n + 1} of the D / A conversion clock (CLK) cycle _{n + 1} or the D / A conversion clock (CLK) cycle n− is selected by the selector 19. 1 video signal (DVBS) X _n-1
Is entered. Therefore, the correction process performed by the harmonic canceller 8 is

[0082]

X ′ = X _n + A (X _n + X _{n + 1} ) ² (19)

Or

[0084]

X '= X _n + A (X _n + X _n-1 ) ² (20)

One of the following:

The second-order harmonic waveforms corresponding to equations 19 and 20 can be shown in the following equations with reference to equation 5, respectively.

[0087]

[Number 21] G [x _SC '(t)] = x _SC (t) + A _{[x SC (t) -x SC (} t + T) ] ^{_{2 + k SC' · x SC}} 2 (t-α ') ··· (21)

[0088]

[Number 22] G [x _SC '(t)] = x _SC (t) + A _{[x SC (t) -x SC (} t-T) ] ^{_{2 + k SC' · x SC}} 2 (t-α ') ·・ ・ (22)

That is, since x _SC (t ± T) can be changed on the right side, the phase difference of the second harmonic can be adjusted.

Here, the clock for D / A conversion (CLK)
One cycle is set to 1 as the phase of the subcarrier signal (SC).
Since it is about 00 °, as shown in the first embodiment,
The movement can be adjusted for 0 °, 180 °, and ± 100 °. That is, 0 °, 100 °, 180 °, 2
Supports phase difference of 80 °, harmonic canceller 5
The second harmonic of the subcarrier signal (SC) can be canceled more accurately than that.

A video signal (DV
BS) X _{n + 1} or X _n-1 is selected according to the coefficient A
Is set by calculation or by actual measurement. Note that the number of stages of the latch circuit provided at the input of the harmonic canceller 8 is limited to two stages, for example, three stages are 0 °,
It may be configured so as to correspond to five types of phase characteristics of 100 °, 180 °, 200 °, and 280 °.

There is also means for automatically obtaining the value of A.
Or the above video signal (DVBS) X _{n + 1}, X_n-1Nozu
A means for deciding which to select may be provided. This strange
For example, the harmonic canceller 8 is equipped with a computer,
Install a harmonic canceller 8 in computer controlled equipment.
The coefficient of the harmonic canceller 8 is adaptively adjusted by the computer.
You may comprise so that adjustment of A etc. may be performed. Also, the present invention
Is not only for video signal processing, but for QAM transmission, for example.
There are applications such as reducing transmission distortion. Each real mentioned above
Other than the embodiment, as described in each embodiment as a modification
In addition, the digital / analog converter of the present invention has various
Can be configured.

[0093]

As described above, according to the digital / analog converter of the present invention, a simple correction process can be performed by the D / A converter.
By applying it to the input signal of the conversion circuit, it is possible to effectively suppress the second harmonic distortion resulting from the D / A conversion,
It is possible to suppress the intensity of the unnecessary signal caused by this distortion. Further, the calculation required for the correction processing is simple and can be easily realized by a signal processing processor or hardware.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a D / A conversion device of the present invention.

FIG. 2 is a diagram illustrating a configuration of a harmonic canceller (HC) that implements DSP processing in hardware according to the first embodiment.

FIG. 3 shows a video signal (DVBS) with a conversion frequency of 13.5.
It is a figure which shows the frequency spectrum at the time of D / A-converting only with a D / A-converting circuit and a low pass filter in MHz.

FIG. 4 is a diagram illustrating an effect of the conversion device.

FIG. 5 is a diagram showing a configuration of a D / A conversion device of the present invention in a second embodiment.

FIG. 6 is a diagram showing a configuration of a harmonic canceller of the present invention in a third embodiment.

FIG. 7 is a diagram showing an output characteristic of a conventional actual D / A conversion IC.

[Explanation of symbols]

1, 6 ... D / A converter, 2 ... DSP, 3 ...
.D / A conversion circuit, 4 ... Low-pass filter, 5, 8
... Harmonic canceller, 11, 18 ... Latch circuit, 12, 17 ... Addition circuit, 13, 14 ... Multiplication circuit, 15 ... Bit switch, 16 ... Delay circuit, 19 ... ..Selectors, 7 ... Encoders

Claims (4)

[Claims] 1. A digital / analog conversion means and a correction means placed in front of the digital / analog conversion means, wherein the correction means is provided for the input signals in a digital format which are successively input in sequence. A digital / analog conversion device for performing a correction process for compensating the conversion characteristic of the digital / analog conversion means based on an input signal and a time-series input signal to the input signal and applying the correction processing to the digital / analog conversion means. 2. The correction means includes a setting means for setting a coefficient obtained corresponding to the conversion characteristic of the digital / analog conversion means, and a digital / analog converter provided after the digital / analog conversion means. And a low-pass filter that performs a predetermined band limitation on the output signal of the conversion unit, the coefficient set in the setting unit, the input signal, and
The digital / analog conversion device according to claim 1, wherein the correction processing adapted to the amplitude characteristic and the phase characteristic of the distortion component is performed on the basis of a time-series input signal to the input signal. 3. The correcting means further comprises means for selecting any one of the time-series input signals for the input signal in accordance with the conversion characteristic, the amplitude characteristic and the phase characteristic of the distortion component being selected. 3. The digital / analog conversion device according to claim 1, wherein the adapted correction processing is performed. 4. A time-series digital input signal is subjected to digital / analog conversion after a correction for compensating for distortion caused by digital / analog conversion is given in advance, and a predetermined band is applied to the signal after digital / analog conversion. Digital-to-analog conversion method with limited output.