JPH06311788A - Control method for inverter stall prevention - Google Patents

Abstract

PURPOSE:To enable smooth starting by adding a specified time to acceleration time data when output current exceeds a specified level of stall, and returning acceleration data to the set value when output frequency reaches a set frequency or becomes zero. CONSTITUTION:Difference in operation from conventional inverter circuits is as follows: If ouutput current exceeds a specified stall value and the acceleration time alteration flag, a specified address of RAM in CPU 10, has not been set, acceleration time data, stored in a non-volatile memory element (ME) 11, is read. A specified time is added to the read acceleration time data, and the resultant data is stored in ME 11. Then the added time alteration flag is reset. If output frequency is equal to a set frequency or zero, a set value for acceleration time is reset to its initial value, and the resultant data is stored in ME 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION When a three-phase AC motor is operated at a variable speed with an inverter, a voltage drop occurs due to the primary resistance and wiring resistance of the motor, and the torque decreases in the low frequency range. In particular, when the load torque is increased during acceleration of the electric motor or when an attempt is made to accelerate for a short time beyond the capacity, the electric motor speed may not follow the frequency and slip may become excessive. At this time, a current higher than the rated current flows through the motor, and overcurrent protection and overload protection may operate and the inverter may stop. The inverter has a stall prevention function which operates at the time of acceleration in order to prevent such a problem, and the present invention relates to improvement of the stall prevention function.

[0002]

2. Description of the Related Art The inverter circuit configuration of the present invention is composed of the same circuit configuration as the conventional one, and FIG. 1 is a diagram showing the configuration of an inverter circuit which has been conventionally implemented. Is converted into a DC voltage in the converter unit 2, 3 is a smoothing capacitor for smoothing the DC voltage, 4 is an inverter unit for converting DC to AC, and the output through the inverter unit 4 is the motor 5 Applied to. A control unit 6 includes a drive circuit unit 7, an A / D converter 8, an interface circuit 9, and a CPU.
The unit 10 and the non-volatile memory element 11 are included. 1
Reference numeral 5 is a current sensor for converting a direct current into a voltage, which is provided for detecting a load current of the motor 5 so as to detect a direct current between the smoothing capacitor 3 and the inverter section 4. .

A frequency setting input voltage, which is an analog signal set by the frequency setting unit 12, is input to the A / D converter 8, converted into a digital signal, and input to the CPU section 10. On the other hand, when the operation switch 13 is closed, the CPU is passed through the interface circuit 9 which isolates an external signal.
It is input to the section 10. The current sensor 15
The load current of the converter 5 is converted into an analog signal and the A / D
It is input to the converter 8 and then to the CPU unit 10. C
When the PU unit 10 performs all the arithmetic processing, the PU unit 10 reads the data from the non-volatile memory element 11 storing the arithmetic result and the data of various parameters and performs the arithmetic processing. 14
Is a display unit for displaying the output frequency of the inverter and a switch operation unit for setting and starting and stopping data of various parameters, and inputs signals to the CPU unit 10. C
The signal calculated from the PU unit 10 is input to the drive circuit unit 7, is further amplified, and drives the inverter unit 4.

FIG. 2 is a diagram showing the relationship between the output current and the output frequency when the level does not reach the specified level of the stole, and FIG. 3 shows the output current when the level exceeds the specified level of the conventional practice. 2 is a diagram showing the relationship between the output frequency and the output frequency. In the case of FIG. 2, since the output current does not reach the stole prescribed level or higher, the output frequency is linearly accelerated in the set acceleration time.
In the case of FIG. 3, the output current becomes equal to or higher than the stole specified level at time t1, at which time the output frequency interrupts acceleration. At time t2, the output current falls below the stow level and the output frequency restarts acceleration again, but at time t3 the output current rises above the stow level again and the output frequency suspends acceleration.

[0005]

Conventionally, when the output current exceeds the specified value during acceleration, the acceleration is temporarily interrupted, the output frequency at that time is held, and the acceleration is restarted when the output current falls below the specified value. In this case, since the acceleration rate is the same, when the acceleration rate is small, and the acceleration rate is small, the output current becomes equal to or higher than the specified value and the acceleration is likely to be interrupted again.

[0006]

Each time the output current exceeds the specified level of the stole, the data of the acceleration time stored in the non-volatile memory element 11 is read out and the acceleration time is increased by adding a fixed time. The data of the acceleration time is stored in the nonvolatile memory element 11 at the same time. When the output frequency has reached the set frequency or when the output frequency has become 0, the data of the acceleration time is returned to the set value and stored in the non-volatile memory element 11 to solve the problem.

[0007]

When the output current exceeds the specified level of the stole, the output frequency stops the acceleration but the output current is stopped.
Since the output frequency becomes lower than the specified level and the acceleration rate becomes longer when the acceleration is restarted again, the increase in the output current does not increase and it becomes difficult to increase the specified level more. Even if the output current increases greatly and exceeds the stow regulation level, the acceleration rate when restarting the acceleration again becomes longer, so it is difficult for the output current to rise above the stow regulation level, and Operation interruption due to electric current is less likely to occur.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 5 is a data flow chart of the present invention in the case where the output current exceeds the specified level of the stall, and it is determined whether the output current exceeds the specified value of the stall or not. If the output current exceeds the stall specified level, C
A stall flag, which is a specific address in the RAM inside the PU, is set, and if the output current drops below the stow regulation level for a prescribed number of times, the stole flag is reset. When the load current of the motor 5 is detected by the DC current between the smoothing capacitor 3 and the inverter unit 4 by the current sensor 15 of the inverter circuit configuration of the prior art shown in FIG. 1, step 102 Check to see if it is above the specified value. If it is not less than the specified value of the stole, a stole flag which is a specific address of the RAM in the CPU is set at step 103. And CP at step 104
The data of the stall counter which sets the time for canceling the stall process, which is a specific address of the RAM in the U, is set to 0. If it is not equal to or more than the specified value of the stall at step 102, it is judged at step 105 whether the stall flag which is a specific address of the RAM is set, and if the stall flag is set, at step 106 the stall
1 is added to the data of the counter and stored in the specific address of the original RAM. In step 107, it is judged whether or not the data of the stall counter is equal to or more than a specified value. If it is equal to or more than the specified value, the stall flag is reset in step 108.

FIG. 6 is a data processing diagram of the acceleration time when the output current of the present invention exceeds the specified value of the stole. The acceleration time is processed based on the set state of the stall flag shown in FIG. . Each time the output current exceeds the specified value of the stole, the data of the acceleration time stored in the non-volatile memory element 11 is read out and added to the non-volatile memory element 11 after adding a certain time, and the output frequency is set. When the frequency is reached or the output frequency becomes 0, the acceleration time data is returned to the set value and stored in the non-volatile memory element 11.

In FIG. 6, when the output current becomes equal to or more than the specified value of the stole, it is judged in step 111 whether the stole flag is set. If the stole flag is set, in step 112 the CPU section 10 It is determined whether the acceleration time change flag, which is a specific address of the RAM, is set, and if the acceleration time change flag is not set, the acceleration time data stored in the non-volatile storage element 11 in step 113. Of the acceleration time read in step 114.
The data added for a fixed time is added to the data, the data added in step 115 is stored in the nonvolatile memory element 11, and the acceleration time change flag is reset in step 116. If the acceleration time flag is set in step 112, step 113, step 114, step 11
5, the process of step 116 is not performed. Step 11
In step 7, it is determined whether the output frequency matches the set frequency or 0 (stop). If the output frequency matches the set frequency or 0, the acceleration time set value is set to the initial set value in step 118. Data is stored in the nonvolatile memory element 11.

FIG. 4 shows the relationship between the output current and the output frequency when the level exceeds the specified level of the stole according to the present invention. By increasing the data, the output current becomes equal to or less than the stole specified value, and the acceleration time when accelerating again can be lengthened. Also, until the output frequency matches the set frequency or becomes 0 (stop), the output current rises above the stall specified level because the acceleration time becomes longer each time the output current exceeds the stall specified value. Therefore, tripping due to overcurrent is less likely to occur.

[0012]

By storing the above-mentioned program in the non-volatile memory element, the acceleration time data can be kept constant for each time the output current exceeds the stow regulation level without increasing the number of parts. Is added to return the acceleration time data to the set value when the output frequency reaches the set frequency or when the output frequency becomes 0, enabling a smooth start-up that is less likely to trip due to overcurrent. Become.

[Brief description of drawings]

 This will be described below.

FIG. 1 is a block diagram of an inverter circuit that has been conventionally implemented.

FIG. 2 is a diagram showing a relationship between an output current and an output frequency in the case where the stole level is not exceeded.

FIG. 3 is a diagram showing the relationship between the output current and the output frequency when the level reaches or exceeds the specified level of the conventional practice.

FIG. 4 is a diagram showing the relationship between the output current and the output frequency when the stole level of the present invention is reached or higher.

FIG. 5 is a data processing flow chart when the output current of the present invention exceeds the specified level of the stole.

FIG. 6 is a data processing flowchart of the acceleration time when the output current of the present invention exceeds the specified level of the stole.

[Explanation of symbols]

 1 Commercial AC power supply 2 Converter part 3 Smoothing capacitor 4 Inverter part 5 Electric motor 6 Control part 7 Drive circuit part 8 A / D converter 9 Interface circuit 10 CPU part 11 Nonvolatile memory element 12 Frequency setting Device 13 operation switch 14 operation switch 15 current sensor

Claims (1)

[Claims] 1. A converter for converting a commercial AC power source into a direct current.
A converter section, an inverter section for converting the direct current converted by the converter section into an alternating current output, a control section having a CPU section for controlling the pulse width of the inverter section, and the inverter output. In the inverter having the function of controlling the frequency according to the load current of the AC motor, the acceleration time stored in the non-volatile memory element is stored every time the load current of the AC motor exceeds the stall specified level. A means for reading out data, a means for adding a fixed time to the data for the acceleration time and storing it in a non-volatile memory element, and a means for outputting when the output frequency of the inverter section reaches a set frequency. A method for controlling the anti-stalling of an inverter, comprising means for returning the acceleration time data to a set value and storing it in a non-volatile memory element when the frequency becomes 0.