JPH06310732A - Fabrication of semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To realize cost reduction by forming three layers of active region, control gate and source line and allowing implementation of self-alined process in many processes thereby eliminating the photolithographic process for forming two layers of floating gates and wirings. CONSTITUTION:A laminate pattern comprising an n<+> polysilicon film 545, a conductive film 547, and an oxide film 549, isolated from each other by an embedded oxide, is formed. The n<+> polysilicon film 545 serves as a floating gate whereas the conductive film 547 serves as a control gate. n<+> diffusion layers 551, 553, 555, 557, 559, 561 of As are then formed by ion implantation. In this regard, each n<+> diffusion layer is isolated by the embedded oxide and laminate gate pattern and the n<+> diffusion layers 551, 553 and 555 provide source regions whereas the n<+> diffusion layers 557, 559, 561 provide drain regions. Subsequently, wirings 571, 573 and 575 are formed only in the recessed regions delimited by the isolation oxide by self-aligned technology.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor nonvolatile memory device such as a highly integrated flash memory.

[0002]

2. Description of the Related Art Conventionally, as a technique of this kind of field,
F. Masuka, et al, "ANew Fla.
sh EEPROM Cell Using Trip
lePolysilicon Technology ”
IEDM, p. 464,1984.

A semiconductor non-volatile memory device capable of electrically writing and erasing does not have a mechanical drive portion such as a magnetic disk, and therefore has an advantage that the auxiliary storage device can be downsized and the power consumption can be reduced. have. Conventionally, this type of device has a stacked gate MOSFET structure in which a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate are stacked in this order from the bottom on an upper portion between a source region and a drain region formed in a substrate. That is, the fact that the threshold value seen from the control gate changes depending on the amount of electrons in the floating gate is used.

The structure and operating method of the conventional semiconductor nonvolatile memory device will be briefly described below. FIG. 5 is a cross-sectional view of essential parts of such a conventional semiconductor nonvolatile memory device. In this figure, 100 is a p-type silicon substrate, 103 is a tunnel insulating film, 105 is a floating gate, 107 is an inter-gate insulating film, 109 is a control gate, and 101, 10
Reference numeral 2 indicates a source region and a drain region of the n-type diffusion layer.

The write operation is, for example, +6 on the drain.
V and +12 V are applied to the control gate 109, a current is caused to flow from the source to the drain, and hot electrons generated are injected into the floating gate 105. Erasing is performed, for example, by applying −9 V to the floating gate 105 and +5 V to the source to extract electrons from the floating gate 105 to the source.

A plan view of such an integrated semiconductor non-volatile memory device is shown in FIG. In FIG. 6, eight 1-unit devices (referred to as cells) shown in FIG. 5 are arranged. Figure 6
In the figure, 201 is a boundary of a field oxide film for separating cells, 203 is a floating gate, 205 is a control gate (word line), 207 is a drain diffusion layer, and 209 is a source diffusion layer. Reference numeral 211 denotes a contact hole formed by partially opening an intermediate insulating film (not shown), 2
Reference numeral 13 is a metal wiring (bit line) for extracting the drain diffusion layer potential.

The manufacturing method will be described below with reference to sectional views in the middle of steps. FIG. 7 shows a cross section taken along line XX of FIG. 6 as the process progresses. (1) First, as shown in FIG. 7A, in order to form a MOS formation region (active region), a patterned nitride film is used as a mask to perform oxidation to form a field oxide film 30.
3, 305 and 307 are formed. A region surrounded by a boundary 201 in FIG. 6 is a field oxide film. In addition, 301 is a semiconductor substrate.

(2) Next, as shown in FIG. 7B, after forming a tunnel insulating film (not shown) on the surface of the active region by oxidation, the floating gates 309 and 311 are formed of n ⁺ polycrystalline silicon. The film is formed by patterning. (3) Next, as shown in FIG. 7C, the floating gate 30
An inter-gate insulating film (not shown) is formed on 9 and then a control gate 313 is formed and patterned.

Continuing the description of the manufacturing process, refer to FIG.
This is performed using FIG. 8 which is a line cross section. (4) Next, after the step of FIG. 7C, as shown in FIG. 8A, the source diffusion layer 40 is formed by ion implantation of As.
1. Form the drain diffusion layer 403. In addition, 101,
Reference numerals 103, 105, 107, and 109 are the same as those shown in FIG. 5, and a description thereof will be omitted here.

(5) Next, as shown in FIG. 8B, an intermediate insulating film 405 is formed on the entire surface. (6) Next, as shown in FIG. 8C, the drain contact 40 is formed by photolithography etching of the contact opening.
Form 7. (7) Next, as shown in FIG. 8D, wiring (bit line) is formed by forming and patterning a metal such as aluminum.
408 is formed.

Through the above steps, the main part of the semiconductor nonvolatile memory device is formed. In the above description, the steps of forming a mask for ion implantation, annealing, forming a surface protective film, etc. are omitted.

[0012]

However, as the degree of integration of the semiconductor nonvolatile memory device is improved,
Problems have arisen in the photolithography process for patterning. This is an increase in the number of photolithography processes and a hindrance to cell area reduction by securing a mask alignment margin. As for the number of photolithography steps, for example, in the pattern of FIG. 6, it is necessary to form an active region, a floating gate, a control gate, a contact, a wiring and five layers. Actually, since the ion implantation photolithography and the peripheral circuit photolithography are required, the number of photolithography processes is larger than that. An increase in the number of photolithography steps is an increase in manufacturing time, which has become a fatal problem of an increase in cost.

For ensuring the mask alignment, for example, FIG.
The active / gate margin L1, the field / contact margin L2, and the contact / wiring margin L3 are required. For these, the mask alignment in the photolithography process does not completely match the underlying pattern,
This is to give a margin beforehand because a certain dimension is displaced. If there is not enough room, for example, if the contact extends over the field oxide film, there arise problems that the contact resistance increases or the contact becomes defective.

Therefore, this margin is unavoidable, but as a result, the dimensions of other parts are reduced, while this margin cannot be reduced, which is a major impediment to device integration. . Since the integration increases the operation speed of the device and reduces the manufacturing cost, the inhibition is a big problem. The present invention eliminates the above-described problems of increasing the number of photolithography processes and increasing the mask alignment margin dimension. Therefore, in the method of manufacturing a semiconductor nonvolatile memory device, the number of photolithography processes is reduced by a self-aligning process. It is an object of the present invention to provide a method for manufacturing a semiconductor nonvolatile memory device, which can reduce the mask alignment margin dimension as well as reduce the size.

[0015]

In order to achieve the above object, the present invention sequentially stacks a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate on a first conductivity type semiconductor substrate from the bottom. And a second conductive type source / drain region formed on the substrate with the stacked gate sandwiched between the first and second conductive type semiconductor substrates. Forming a mask material pattern, and using the first mask material pattern as a mask, the semiconductor substrate is etched to a predetermined depth to form a groove, and the first insulating film is self-aligned with the groove. Forming a buried isolation insulating film; removing the first mask material; and forming a tunnel insulating film on the exposed surface of the semiconductor substrate sandwiched by the isolation insulating film, and then forming a first conductive film. Film formation A step of removing only the upper surface of the isolation insulating film by anisotropic etching of the first conductive film, and forming a second insulating film on the remaining first conductive film. A step of forming a first insulating film by laminating a third insulating film after forming a second conductive film, the first insulating film, the second insulating film, and the first conductive film. Patterning the film and the tunnel insulating film in a direction orthogonal to the isolation insulating film to form a stacked gate, and then forming drain / source regions on both sides of the stacked gate; and a fourth step on the stacked gate sidewall. A step of forming an insulating film, and after forming a third conductive film on the entire surface, a fifth insulating film is laminated to form a second laminated film, which is selectively etched to sandwich the laminated gate. A step of remaining forming the second laminated film only on the source side, and a fourth conductive film on the entire surface. It was formed, the fourth
And the step of forming a wiring by remaining the conductive film remaining only in the region between the isolation insulating films by etching back.

[0016]

According to the present invention, since it is configured as described above,
In the method for manufacturing a semiconductor non-volatile memory device, the photolithography process includes forming an active region [see FIG. 1 (a)], forming a control gate (word line) [see FIG. 3 (c)], and forming a source line [see FIG. 4 (b)]. ) Reference]. That is, conventionally, active area formation [FIG.
Floating gate formation [see FIG. 7B], control gate (word line) formation [see FIG. 8A], contact formation [see FIG. 8C], wiring formation [FIG. 8D] 5 layers are required, it is possible to eliminate the photolithography process for forming two layers of floating gate formation and wiring formation.

Further, since the self-alignment process is frequently used, the mask alignment margin can be significantly reduced. For example, in a conventional semiconductor non-volatile memory device, an alignment margin (indicated by L3 in FIG. 6) between the contact and the wiring is indispensable, and as a result, the wiring becomes thicker at the contact portion and the pitch between the wirings becomes larger. It was restricted by and became an obstacle to reducing the pitch.

On the other hand, in the present invention, since the wiring can be formed in the active region in a self-aligning manner, such an alignment margin is not necessary at all, and as a result, the pitch between the wirings can be greatly reduced. Further, regarding the margin between the active region and the gate wiring (indicated by L1 in FIG. 6), since the active area is not separated in the gate wiring direction in the present invention, no margin dimension is required.

[0019]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 to 4 are partially cutaway perspective views showing a manufacturing process of a semiconductor nonvolatile memory device showing an embodiment of the present invention. (1) First, as shown in FIG. 1A, a nitride film (first mask material) is formed on the entire surface of the p-type silicon substrate 501 by using, for example, the CVD method. After that, a part of this nitride film is removed by etching using a known photolithography method and etching, and the exposed portion 5 of the p-type silicon substrate 501 is removed.
09, 511 and residual nitride films 503, 505, 507 (first mask material pattern) are formed.

(2) Next, as shown in FIG. 1B, the exposed portions 509 and 511 of the p-type silicon substrate 501 are selectively dry-etched by masking the remaining nitride films 503, 505 and 507. Etching to, for example, 0.2 to
Silicon grooves 513 and 515 having a depth of about 0.5 μm are formed. (3) Next, after forming an oxide film on the entire surface by the CVD method,
As shown in FIG. 1C, an oxide film 517, is formed on the silicon trenches 513, 515 by using a known etchback method or the like.
519 (separation insulating film) is embedded. Note that the etch-back method may be a method of advancing the etching until the nitride film mask is exposed when the oxide film is formed on the entire surface or after being planarized by a heat treatment, or after the oxide film is formed. Alternatively, a method using a method of flattening by applying and etching can be used.

(4) After that, as shown in FIG.
Residual nitride films 503, 505, 50 that are nitride film patterns
7 (see FIG. 1C) is removed. (5) Next, as shown in FIG. 2B, the exposed surface of the p-type silicon substrate 501 is subjected to 3 to 3 by a heat treatment oxidation method.
An oxide film 521, 523, 525 (tunnel insulating film) having a thickness of about 20 nm is formed. Here, it goes without saying that the formation of the oxide film may include not only the oxidation treatment in the oxygen atmosphere but also the nitriding treatment with nitrous oxide (N ₂ O), ammonia (NH ₃ ), or the like. Then, an n ⁺ polycrystalline silicon film 527 (first conductive film) having a film thickness of about 0.1 to 0.3 μm is formed on the entire surface.

(6) Next, buried oxide films 517 and 51
A mask material such as a resist is formed on the bottom surface of the recess surrounded by 9 by an etch-back method or the like (not shown), and then the n ⁺ polycrystalline silicon film 527 is selectively etched by anisotropic etching from the vertical direction. Etched and buried oxide film 5
The upper part of 17,519 is exposed. Then, by removing the mask material (not shown) provided on the bottom surface of the concave portion, as shown in FIG.
As shown in FIG. 5, n ⁺ polycrystalline silicon films 529, 531 and 533 separated from each other by oxide films 517 and 519 are formed.

(7) Next, as shown in FIG. 3A, the insulating films 535, 537, 539 (second insulating film) made of an oxide film or a laminated film of an oxide film and a nitride film, etc. ~ 30
It is formed with a film thickness of about nm. The buried oxide film 51
The insulating films above 7,519 are not shown in the figure because they are the same insulating film. (8) Next, as shown in FIG.
A conductive film 541 (second conductive film) made of an n ⁺ polycrystalline silicon film or a laminated film of an n ⁺ polycrystalline silicon film and a high melting point silicide with a film thickness of about 0.5 μm is formed. After that, an oxide film 543 (third insulating film) is formed to a thickness of about 0.1 μm to 0.3 μm by a CVD method to form a first first laminated film.

(9) Next, a known photolithography method,
By using an etching method, as shown in FIG. 3C, an oxide film 543, a conductive film 541, insulating films 535, 537, 53.
The layers of 9, n ⁺ polycrystalline silicon 529, 531, 533 and the oxide films 521, 523, 525 are formed in a strip shape in the direction orthogonal to the extending direction of the buried oxide film to form a laminated gate. As a result, the n ⁺ polycrystalline silicon film 545 and the conductive film 54 separated by the buried oxide film are formed.
7. A laminated pattern composed of each layer of the oxide film 549 is obtained.
The n ⁺ polycrystalline silicon film 545 serves as a floating gate, and the conductive film 547 serves as a control gate.

Next, by using the ion implantation method, n
⁺ Diffusion layers 551,553,555,557,559,5
61 is formed. Wherein each n ⁺ diffusion layer are separated by the oxide film and the stacked gate pattern embedding, n ⁺
The diffusion layers 551, 553, 555 are formed in the source region, and 55
7, 559 and 561 are drain regions. (10) Next, as shown in FIG. 4A, an oxide film having a thickness of about 0.1 μm to 0.3 μm is formed by the CVD method, and then the oxide film 563 is anisotropically etched only on the side wall of the laminated gate pattern. , 565 (fourth insulating film) are left. Although a residual oxide film is also formed on the sidewalls of the buried oxide film, they are not shown separately because they are the same oxide film.

(11) Subsequently, as shown in FIG. 4B, a conductive film of tungsten or the like (third conductive film) is formed on the entire surface.
Is deposited to a thickness of about 0.05 to 0.2 μm, and then an oxide film (fifth insulating film) is deposited to a thickness of about 0.1 to 0.3 μm.
Then, masking only the source side with a resist (not shown), the oxide film and the conductive film formed on the drain side are selectively etched, and the conductive film 567 (third conductive film) only on the source side. Then, the oxide film 569 (fifth insulating film) is left and formed to form a second laminated film. Therefore, in this step, only the surface of the drain diffusion layer is exposed and the other surfaces are all covered with the insulating film.

(12) Next, a metal film (a fourth conductive film) of aluminum or the like is formed on the entire surface and is etched back to be sandwiched between the isolation oxide films as shown in FIG. 4 (c). Wiring 571, 573 in a self-aligned manner only in the recessed area
575 is formed. Here, the etch-back is formed so that the metal film does not remain in the upper portion of the isolation oxide film and that the metal film continuously remains in the insulating film concave portion without disconnection. This wiring is in contact with the drain diffusion layer and serves as a drain connection wiring, that is, a bit line.

Through the above steps, the main part of the semiconductor nonvolatile memory device of this embodiment is formed. Although description of the threshold value adjusting ion implantation, the annealing step, the surface protective film forming step, and the like is omitted, it goes without saying that they can be appropriately used. Further, the operation method of the semiconductor nonvolatile memory of the present invention can be performed in the same manner as the conventional method.

The present invention is not limited to the above embodiments, but various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0030]

As described in detail above, according to the present invention, the following effects can be obtained. (1) First, the number of photolithography steps can be significantly reduced. That is, as described above, in the main steps of cell manufacturing, conventionally, active region formation [see FIG. 7A], floating gate formation [see FIG. 7B], control gate (word line) formation [FIG. (See (a)), contact formation [see FIG. 8 (c)], and wiring formation [see FIG. 8 (d)].

On the other hand, according to the present invention, active region formation (see FIG. 1A), control gate (word line) formation (see FIG. 3C), and source line formation (FIG. 4B). ) Reference]. That is, the number of masks can be reduced by enabling the self-alignment process in many steps. Specifically, the photolithography process for forming two layers of floating gate formation and wiring formation can be eliminated. The reduction of the photolithography process can bring about a great effect that the manufacturing period can be shortened and the cost can be reduced.

(2) Further, since the self-alignment process is frequently used, the mask alignment margin can be significantly reduced. For example, in the conventional semiconductor non-volatile memory device, the alignment margin between the contact and the wiring (see FIG.
(Indicated by L3 in FIG. 2) is essential, and as a result, the wiring becomes thick at the contact portion, and the pitch between the wirings is limited at this contact portion, which is an obstacle to reducing the pitch.

On the other hand, in the present invention, since the wiring can be formed in the active region in a self-aligning manner, such an alignment margin is not required at all, and as a result, the pitch between the wirings can be greatly reduced. Further, regarding the margin between the active region and the gate wiring (indicated by L1 in FIG. 6), since the active area is not separated in the gate wiring direction in the present invention, no margin dimension is required.

As a result, according to the present invention, the integration of the semiconductor nonvolatile memory device can be greatly promoted.
The integration, that is, the increase in capacity of the semiconductor nonvolatile memory device increases the added value of the device, which is an extremely large effect. Further, when compared with the same capacity, since the device size can be reduced in the present invention, the material cost and the manufacturing cost per device can be reduced.

[Brief description of drawings]

FIG. 1 is a partial cutaway perspective view (1) showing a manufacturing process of a semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a partially cutaway perspective view showing the manufacturing process of the semiconductor nonvolatile memory device according to the embodiment of the present invention (Part 2).

FIG. 3 is a partially cutaway perspective view (No. 3) showing the manufacturing process of the semiconductor nonvolatile memory device according to the embodiment of the present invention.

FIG. 4 is a partially cutaway perspective view (No. 4) showing the manufacturing process of the semiconductor nonvolatile memory device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view of a main part of a conventional semiconductor nonvolatile memory device.

FIG. 6 is a plan view of a conventional integrated semiconductor nonvolatile memory device.

FIG. 7 is a process drawing of a cross section taken along line XX of FIG. 6;

FIG. 8 is a process drawing of a section taken along line YY of FIG. 6;

[Explanation of symbols]

501 p-type silicon substrate 503, 505, 507 Residual nitride film 509, 511 Exposed part 513, 515 Silicon groove 517, 519 Embedded oxide film 521, 523, 525, 543, 549, 563, 5
65 oxide film 527, 529, 531, 533, 545 n ⁺ polycrystalline silicon film 535, 537, 539 insulating film 541, 547, 567 conductive film 551, 553, 555, 557, 559, 561
n ⁺ diffusion layer 571, 573, 575 wiring

Claims (1)

[Claims] 1. A laminated gate formed by laminating a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate in order from the bottom on a first conductivity type semiconductor substrate, and on the semiconductor substrate sandwiching the laminated gate. A method of manufacturing a semiconductor non-volatile memory device having second-conductivity-type source and drain regions formed, comprising: (a) a step of forming a first mask material pattern on the first-conductivity-type semiconductor substrate; ) A step of etching the semiconductor substrate to a predetermined depth by using the first mask material pattern as a mask to form a groove, and (c) a first insulating film embedded in the groove in a self-aligning manner and an isolation insulating film. And (d) removing the first mask material, and (e) forming a tunnel insulating film on the exposed surface of the semiconductor substrate sandwiched by the isolation insulating film, and Forming a conductive film And (f) removing only the upper surface of the isolation insulating film by anisotropic etching of the first conductive film, and (g) forming a second insulating film on the remaining formed first conductive film. A step of forming a film; (h) a step of forming a second insulating film after forming a second conductive film to form a first laminated film; (i) the first laminated film; After patterning the second insulating film, the first conductive film, and the tunnel insulating film in a direction orthogonal to the separation insulating film to form a stacked gate,
Forming a drain / source region on both sides of the stacked gate; (j) forming a fourth insulating film on the sidewall of the stacked gate; and (k) forming a third conductive film on the entire surface, Laminating the insulating films of No. 5 to form a second laminated film, selectively etching, and forming the second laminated film only on the source side with the laminated gate sandwiched therebetween (l) And a step of forming a fourth conductive film over the entire surface and etching the fourth conductive film to leave only a region between the isolation insulating films. Memory device manufacturing method.