JPH06310664A - Isolation structure of semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide an isolation structure for a semiconductor device wherein elements can be surely isolated with low energy and a manufacturing process is simple, in a hybrid LSI structure wherein a bipolar transistor and a MOS transistor are formed on the same substrate. CONSTITUTION:In the isolation structure of a semiconductor device wherein a MIS transistor 9 and a bipolar transistor 8 are formed on a semiconductor substrate 1, a trench 15 as well as a burled contact is formed in an element isolation region of the bipolar transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an isolation structure for isolating elements of a semiconductor device, and more particularly to a semiconductor device isolation structure in which a MIS transistor and a bipolar transistor are formed on the same substrate and a method of manufacturing the same. It is a thing.

[0002]

2. Description of the Related Art As an isolation structure of a semiconductor device, a field oxide film in which an oxide film is selectively formed thick and a structure in which an impurity is doped into this field oxide film are used. Such isolation prevents electrical interference between adjacent elements on the same chip. Further, as an element isolation structure of a bipolar LSI, U
An example of groove separation is described (see "Monthly Semi
on director World "1987.4 P1
04 Figure 14). Separation by such a U-groove enables separation having higher electrical characteristics (compared to withstand voltage) than separation by an impurity region.

On the other hand, a bipolar transistor which operates at high speed and has a large output, and C which has a high integration density and consumes little power.
BiCMOS (Bipolar-CMOS) for realizing a high-speed and low-power highly integrated LSI by forming a MIS transistor such as a MOS transistor on the same substrate.
A structured LSI has been developed in recent years. BiC like this
In the MOS structure, a plurality of transistors of different types are formed on the same substrate, which increases the number of manufacturing steps and complicates the manufacturing process. Therefore, even in the case of forming the element isolation region, an isolation structure that can achieve element isolation surely in a simplified step is required.

[0004]

However, the conventional U-groove isolation structure has a problem that a special etching or burying step is required for the groove, which significantly complicates the process and lowers the throughput. In addition, in the structure in which the impurity region is formed in the field oxide film, high-energy ion implantation reaching from the surface of the epitaxial growth layer to the substrate below the epitaxial growth layer is necessary, including the case of the isolation structure only by the impurity region, The throughput and the capability of the ion implantation apparatus or the reproducibility for forming a constant and stable element isolation region always occur. In this case, the film thickness of the epitaxial growth layer targeted for high energy ion implantation is about 1 to 2 μm, and 500 KeV for B + ions.
Energy of 1 MeV or more is required. Further, in order to perform element isolation by the impurity region, a large area is required due to lateral diffusion and the like.

The present invention has been made in view of the above problems of the prior art, and particularly, a bipolar transistor and an MO
It is an object of the present invention to provide an isolation structure for a semiconductor device, which can achieve reliable element isolation with low energy and simplifies the manufacturing process in a mixed LSI structure in which an S transistor is formed on the same substrate.

[0006]

In order to achieve the above object, the present invention provides an isolation structure of a bipolar transistor in an isolation structure of a semiconductor device in which a MIS type transistor and a bipolar transistor are formed on a semiconductor substrate. A trench is formed in the.

Moreover, the trench is formed at the same time as the buried contact provided in the element forming region of the MIS transistor.

In a further preferred embodiment, the M
The IS type transistor has a CMOS structure and constitutes a BiCMOS device together with the bipolar transistor.

Further, in order to achieve the above object, a method of manufacturing an isolation structure of a semiconductor device according to the present invention is a method of manufacturing an isolation structure of a semiconductor device in which a MIS type transistor and a bipolar transistor are formed on a semiconductor substrate. Forming an oxide film on the semiconductor substrate, selectively removing the oxide film in the element formation region of the MIS transistor to form a buried contact portion, and oxide film in the buried contact portion. In a method of manufacturing an isolation structure of a semiconductor device, which includes a step of covering a semiconductor substrate with a polysilicon layer after removal and a step of patterning a polysilicon layer of the MIS transistor, oxidation of a buried contact portion of the MIS transistor. In the film removal step, Oxide film in the element isolation region of the bipolar transistor is removed at the same time, and in the patterning step of the polysilicon layer, a trench is formed in the element isolation region of the bipolar transistor from which the oxide film has been removed, and the trench is formed by the trench. The elements are separated.

In a preferred embodiment, the step of patterning the polysilicon layer comprises an etching process, which simultaneously forms trenches in the element forming region of the MIS type transistor and the element isolation region of the bipolar transistor.

[0011]

For example, at the same time as the step of forming a buried contact by removing the surface oxide film of the source / drain region of the CMOS structure MIS transistor, the surface oxide film of the element isolation region of the bipolar transistor is also removed, and etching is performed in the gate electrode forming step. By processing, a trench is formed in the element isolation region of the bipolar transistor. By implanting impurities into the bottom of the trench, an impurity layer reaching the substrate surface with low energy is formed.

[0012]

EXAMPLE FIG. 1 (A) (B) and FIG. 2 (A) (B)
FIG. 6 is a sectional configuration diagram sequentially showing a manufacturing process of a BiCMOS device according to an example of the present invention. The figure shows a bipolar transistor formation region 8 and MO on a common P-type substrate 1.
The cross section of the S transistor formation region 9 is shown.

In the state shown in FIG. 1A, in the MOS transistor formation region 9, an N type epitaxial growth layer 3 and a P type well region 3'are formed on the P type substrate 1.
An oxide film 4 made of SiO ₂ and a field oxide film 5 are formed thereon. A channel stopper 6 is formed at the bottom of the field oxide film 5 by implanting impurities (phosphorus ions). A buried contact 7 from which the oxide film 4 has been removed to form a buried contact is formed in the element formation region of this MOS transistor.

In the bipolar transistor forming region 8, an N layer 3 is formed on a P type substrate 1 with an N + buried layer interposed, and an oxide film 4 and a field oxide film 5 made of SiO ₂ are formed thereon. A channel stopper 6 is formed at the bottom of the field oxide film 5 by implanting impurities (phosphorus ions). A buried contact 7 from which the oxide film 4 has been removed is formed in the element isolation region of the bipolar transistor formation region 8. This buried contact 7 is formed simultaneously with the buried contact 7 in the MOS transistor formation region 9.

Next, as shown in FIG. 1B, in the MOS transistor formation region 9, for example, a polysilicon layer 12 of 100 μm and a tungsten silicide layer 1 of 100 μm are formed.
The first-layer gate electrode 10 having a polycide structure composed of
Is formed. When the gate electrode 10 is formed, a polysilicon layer is formed over the entire surface of the substrate including the bipolar transistor forming region 8, and the buried contact 7 of the MOS transistor and the bipolar transistor (see FIG. 1) is formed.
By patterning the portion (A)) by etching, a trench (groove) 15 is formed in the element isolation region of the bipolar transistor together with the trench 13 forming the buried contact of the MOS transistor. Then, an N-type impurity layer 14 is formed in the source / drain portion of the MOS transistor by ion implantation and diffusion.

Next, as shown in FIG. 2A, a P + impurity layer 16 is formed by ion implantation at the bottom of the trench 15 formed in the element isolation region of the bipolar transistor. In this case, since the groove formed by the trench 15 is formed, the ions reach the substrate 1 with low energy and achieve a reliable element isolation function.

Subsequently, as shown in FIG. 2B, the base 20 and the emitter 31 of the bipolar transistor are formed. The emitter 31 is formed by diffusion from the polysilicon layer 21. Further, the interlayer insulating film 18 is patterned to connect the aluminum electrodes 22 and 23, respectively. An aluminum electrode 19 is also connected to the N + buried layer 2 via the N + connection layer 17. Similarly MOS
Also for the transistor, the interlayer insulating film 18 is patterned to form an aluminum electrode terminal.

The manufacturing process of the above BiCMOS device will be described in more detail with reference to FIGS. 3A to 3D and FIGS. 4E to 4G are cross-sectional configuration diagrams sequentially showing the manufacturing process of the CMOS formation portion of the BiCMOS device according to the embodiment of the present invention.

First, as shown in FIG. 3A, an N layer 3 is epitaxially grown on a P-type silicon substrate 1. Subsequently, as shown in FIG. 3B, an oxide film 4 of SiO ₂ is formed on the N layer 3, and a nitride layer 24 of SiN or the like is formed on the oxide film 4 for patterning. Form (LOCOS method).

Next, as shown in FIG. 3C, boron ions are implanted through the resist pattern mask 25 to form a P well 26. Phosphorus ions are ion-implanted to form the channel stop layer 6. Next, as shown in FIG. 3D, the resist pattern mask 25 and the oxide film 4 are removed. Subsequently, a gate oxide film 4a is formed (FIG. 4).
(E)).

Next, as shown in FIG.
The gate oxide film 4a is opened through the via 7, and a buried contact 28 is formed. Then, the resist 27 is removed, a polycide layer (polysilicon and tungsten silicide) is stacked, and a buried contact 28 is formed by etching.
A groove is formed in the portion. Further, as shown in FIG. 4G, the NMOS section 42 and the PMOS section 43 have N
Implanting ions and P ions to form the polysilicon layer 12
Then, an electrode composed of the silicide layer 11 is formed. Then, aluminum electrode terminals (not shown) are formed through the patterned interlayer insulating film.

5 (A) to 5 (D) and 6 (E) to
FIG. 3H is a cross-sectional configuration diagram sequentially showing the manufacturing process of the bipolar transistor formed on the same substrate in parallel with the manufacturing process of the CMOS formation portion of the BiCMOS device.

First, as shown in FIG. 5A, an N + layer 2 and an N layer 3 are formed on a P-type silicon substrate 1. This N layer 3 is simultaneously performed in the above-described manufacturing step (FIG. 3A) of the N layer 3 of the CMOS transistor. Next, as shown in FIG. 5B, an oxide film 4 is formed on the N layer 3 and the nitride layer 24 is patterned to form LOCO.
The field oxide film 5 is selectively formed by the S method. This field oxide film 5 is also formed at the same time as the field oxide film 5 of the CMOS transistor shown in FIG.

Next, as shown in FIG. 5C, the gate oxide film 4a and the field oxide film 5 are covered with a resist 27, and the resist 27 is patterned to open the gate oxide film 4a in the element isolation region. Velid Contact 28
To form. This buried contact 28 is the above-mentioned C.
They are simultaneously formed in the step of forming the buried contact of the MOS transistor (FIG. 4F).

Next, as shown in FIG. 5D, a trench 15 is formed by etching in the buried contact 28 portion formed in the element isolation region. This trench 15
The etching step is performed at the same time as the step of forming the electrode of the CMOS transistor described above. When the polysilicon of the CMOS transistor electrode is laminated, the polysilicon is also laminated on the bipolar transistor portion at the same time, and the patterning of this polysilicon is performed to form the electrode of the CMOS transistor. By performing them simultaneously, the trench 15 in the element isolation region of the bipolar transistor is formed in the same step.

Next, as shown in FIG. 6E, a P + impurity layer 16 is formed in the bottom of the trench 15 by ion implantation. The trench 15 and the impurity layer 16 reaching the substrate 1 at the bottom of the trench 15 separate the elements of the bipolar transistor.

Thereafter, as shown in FIG. 6 (F), BF ₂
By implanting + ions of, the intrinsic base 29 is formed on the lower surface of the gate oxide film 4a. Subsequently, as shown in FIG. 6G, a graft base 30 is formed, a polysilicon layer 32 is provided, As ions are implanted through the polysilicon layer 32, and after patterning, an interlayer insulating film 18 is formed. . Further, annealing is performed to remove As from the polysilicon layer 32.
Are diffused to form the emitter 31. Furthermore, FIG.
As shown in (H), the interlayer insulating film 18 is patterned to form aluminum electrode terminals 19, 22, 23, and 24 in the collector connection portion 17, the base 30, the emitter 31, and the element isolation trench portion, respectively.

As described above, the bipolar transistor and the MOS transistor can be formed on the same silicon substrate by partially overlapping the manufacturing process. In addition, in the above-mentioned embodiment, the trench structure at the time of forming the transistor electrode of the first layer is described, but the trench can be similarly formed in the polysilicon layer of the second layer and the third layer. If the second layer polysilicon layer, the third layer polysilicon, etc. are also etched in the same manner, the trench becomes deeper and reaches the P-type substrate 1, so that no impurities are needed.

[0029]

As described above, according to the present invention, in a mixed LSI of a bipolar element and a MOS element, a trench is formed in an element isolation region of an epitaxial growth layer on a bipolar element substrate and an impurity is formed at the bottom of the trench. Since the layer is provided, the impurity ions can be implanted at a low energy to a depth reaching the substrate surface, and reliable element isolation can be achieved. Also, the trench is M
Since the OS element is formed in the same process at the same time as the buried contact formation, the process for forming the element isolation structure is simplified and the throughput of device manufacturing is improved. Further, since ion implantation can be controlled with low energy, reproducible and stable element isolation characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a manufacturing process explanatory diagram showing, in the order of manufacturing processes, a cross-sectional structure of a BiCMOS LSI according to an embodiment of the present invention.

FIG. 2 is a manufacturing process explanatory diagram sequentially showing a cross-sectional structure of a process subsequent to the manufacturing process of FIG.

FIG. 3 is a manufacturing process explanatory diagram showing, in the order of manufacturing processes, a cross-sectional structure of a CMOS formation portion of a BiCMOS LSI according to an example of the present invention.

FIG. 4 is a manufacturing process explanatory diagram sequentially showing the cross-sectional structure of the CMOS formation portion subsequent to the manufacturing process of FIG. 3;

FIG. 5 is a manufacturing process explanatory diagram sequentially showing the cross-sectional structure of the bipolar element formation portion of the BiCMOS LSI according to the embodiment of the invention.

FIG. 6 is a manufacturing process explanatory diagram sequentially showing the cross-sectional structure of the bipolar element formation portion subsequent to the manufacturing process of FIG. 5;

[Explanation of symbols]

1: P-type substrate, 2: N + layer, 3: N layer, 4: oxide film, 4a: gate oxide film, 5: field oxide film,
6: channel stopper, 7: buried contact, 8: bipolar transistor formation region, 9: M
OS transistor forming region, 10: electrode, 15: trench, 16: impurity layer, 19, 22, 23: aluminum electrode terminal, 20: base, 31: emitter.

Claims (4)

[Claims] 1. In an isolation structure of a semiconductor device in which a MIS type transistor and a bipolar transistor are formed on a semiconductor substrate, an embedded contact for connecting a gate electrode of the MIS type transistor and the semiconductor substrate is formed, The buried contact is provided by forming a trench in an element isolation region of the bipolar transistor, and an isolation structure of a semiconductor device. 2. The MIS type transistor has a CMOS structure, and together with the bipolar transistor, Bi
A CMOS device is configured to claim 1.
An isolation structure for a semiconductor device according to 1. 3. A method of manufacturing an isolation structure of a semiconductor device, wherein a MIS type transistor and a bipolar transistor are formed on a semiconductor substrate, the method comprising: forming an oxide film on the semiconductor substrate; and an element of the MIS type transistor. Selectively removing an oxide film on the formation region to form a buried contact portion; covering the semiconductor substrate with a polysilicon layer after removing the oxide film in the buried contact portion; A method of manufacturing an isolation structure of a semiconductor device, which comprises a step of patterning a silicon layer, wherein an oxide film in an element isolation region of the bipolar transistor is simultaneously removed in an oxide film removing step of a buried contact portion of the MIS transistor. , The polysilicon layer In the turning step,
A method of manufacturing an isolation structure of a semiconductor device, comprising forming a trench in an element isolation region of the bipolar transistor from which an oxide film has been removed, and performing element isolation of the bipolar transistor by the trench. 4. The patterning step of the polysilicon layer comprises an etching step, and by the etching, trenches are simultaneously formed in an element forming region of the MIS type transistor and an element isolation region of the bipolar transistor. A method of manufacturing an isolation structure for a semiconductor device according to claim 3.