JPH06309281A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To provide an inter-processor communication system in which the number of times of inter-processor communication can be sharply decreased, and a parallel processing effect can be improved by preparing transmitting buffers and receiving buffers corresponding to each communicating party processor at each processor, and operating block transfer. CONSTITUTION:This system is equipped with a step 11 in which plural processors prepare the transmitting buffers which temporarily store transmission information to the other processors for each other processor, and prepare the receiving buffers which temporarily store reception information for each other processor, step 14 in which data to be transmitted after a prescribed arithmetic operation is performed and a writing address are integrated as a set, and written and stored in the corresponding transmitting buffers, step 16 in which the information of the transmitting buffers is block-transferred to the corresponding processors after the arithmetic operation is ended, step 17 in which the transferred information is written in the receiving buffers, and step 19 in which the data of the receiving buffer are written in the address of a memory corresponding to the writing address transmitted as the set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication system, and more particularly to an interprocessor communication system for a parallel computer composed of a plurality of processors.

[0002]

2. Description of the Related Art A parallel computer system consisting of a plurality of processors each having a memory and a network for transferring and synchronizing data between these processors has a function distribution and load distribution processing. With the aim of speeding up and improving the reliability of the microprocessor, it has been widely used as the performance of microprocessors and the integration of memories have increased.

Interprocessor communication in such a so-called loosely coupled multiprocessor system is performed in the form of message communication, and a packet communication system or the like is used.

In the interprocessor communication system, that is, in the transfer of data from the processor Pi to another processor Pj, for example, conventionally, a plurality of words having consecutive addresses in the memory of the processor Pi are processed by the processor Pj.
In the case of transferring to consecutive addresses of the memory of the, the block transfer is performed by starting communication between processors once.

However, in other cases, for example,
Transfer of a plurality of words each having a non-contiguous address in the memory of the processor Pi, or the processor Pj
In the case of transferring a plurality of words to non-consecutive addresses in the memory of, each word is treated as one inter-processor communication, and inter-processor communication is activated a plurality of times.
Has been done.

[0006]

Interprocessor communication is one
As a result, the communication packet generation overhead on the transmission side and the interruption overhead on the reception side inevitably occur.

Therefore, in the above-described conventional inter-processor communication system, when transferring a plurality of words relating to non-consecutive addresses, the above-mentioned overhead occurs only a number of times related to the number of transferred words, which increases the overhead. However, there is a problem that a sufficient parallel processing effect cannot be obtained.

It is an object of the present invention to prepare a transmission buffer and a reception buffer corresponding to each communication partner processor for each processor and perform block transfer, so that the number of communication between processors can be greatly reduced and the parallel processing effect can be improved. It is to provide an inter-processor communication system.

[0009]

According to a first aspect of the present invention, there is provided an interprocessor communication system for a parallel computer, which comprises a plurality of processors each having a memory. A transmission buffer for temporarily storing information to be transmitted to the processor is prepared for each of the other communication partner processors, and a reception buffer for temporarily storing information received from the other communication partner processor is prepared for each of the other communication partner processors. The buffer preparation step and the plurality of processors perform a predetermined operation respectively and transmit the data to be transmitted to the other communication partner processor and the write address of this data in the other communication partner processor as a set to the corresponding transmission buffer. A transmission buffer writing step for writing and accumulating; A block transfer step of performing a block transfer of the information written and accumulated in the transmission buffer to the corresponding other communication partner processor after completion of the predetermined calculation; and the plurality of processors respectively from the other communication partner processor. A reception buffer writing step of writing the transferred information to the reception buffer corresponding to the other communication partner processor, and the plurality of processors corresponding to the write address sent with the data of the reception buffer as a set. A memory writing step of writing to an address of the memory of the own processor.

The inter-processor communication system of the second invention corresponds to the inter-processor communication system of the first invention when the amount of data communicated between the processors is known in the buffer preparation step. A transmitting buffer and a receiving buffer are prepared. If not known, first prepare a transmitting buffer and a receiving buffer having a data amount corresponding to one block transfer between processors, and thereafter, each time these buffers become full, It is configured by dynamically securing an area corresponding to the amount of data corresponding to one block transfer and preparing to connect them by a link.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a flow chart showing an embodiment of the interprocessor communication system of the present invention.

FIG. 2 shows an example of a parallel computer system which performs the interprocessor communication system of this embodiment. This parallel computer system is composed of three processors Pi, Pj and Pk, which are connected by a network. In the figure, the network is shown schematically by connecting each processor with a line.

Each processor has the same structure and stores a memory for storing data necessary for its own processing, and the result of the processing,
A transmission buffer that temporarily stores the data to be transmitted to other processors for each destination processor, and the data required for its own processing that is received from the other processor as a result of the processing by the other processor is temporarily stored for each source processor. It is equipped with a reception buffer.

Taking the processor Pi as an example,
The processor Pi stores a memory Mi for storing data necessary for the processing of its own processor, and a transmission buffer Sij for temporarily storing data to be transmitted from the processor Pi to the processor Pj as a result of the processing (suffix ij is transmitted by the processor Pi and the processor Pj Indicates that it will receive the same below)
A transmission buffer Sik for temporarily storing data to be transmitted from the processor Pi to the processor Pk;
It includes a reception buffer Rji for temporarily storing the data received from j for its own processing and a reception buffer Rki for temporarily storing the data received from the processor Pk for its own processing.

FIGS. 3 to 5 schematically show how the data exchanged between the processors is transferred as the interprocessor communication system is executed.

The operation of this embodiment will be described with reference to FIGS.

First, in each processor, a transmission buffer for temporarily storing data to be written in the memory of another communication partner processor and a reception buffer for temporarily storing data received from another processor are secured for each communication partner processor (step 11). . This may be provided in the main memory in each processor or may be provided as a separate memory.

In securing, when the number of transfer words from each processor to another processor is known in advance, a buffer corresponding to that is reserved and unknown, that is, when the number of transfer words cannot be known without processing. Prepares a buffer for one block transfer at the beginning, dynamically reserves an area for one block transfer each time the buffer is full, and links these areas with a link.

In FIG. 2, the transmission buffers Sij and Sik and the reception buffers Rji and Rki are secured in the processor Pi, the transmission buffers Sji and Sjk are secured in the processor Pj, and the reception buffers Rij and Rkj are secured in the processor Pk. The state is shown in which the transmission buffers Ski and Skj and the reception buffers Rik and Rjk are secured.

Next, each processor performs a predetermined operation A (step 12). As for the processor Pi, since the data necessary for the operation A is stored in the memory Mi owned by itself, the predetermined operation A is performed by this, and when the operation result or the like is written in the memory Mi, the memory is stored. When writing to Mi (step 13) and writing to the memory Mj of another processor, for example, the processor Pj, the processor in the processor Pi forms a pair with the data to be written and the address on the memory Mj in which the data is to be stored. The transmission data to Pj is written in the transmission buffer Sij for temporary storage (step 14). In this way, each time data to be written to the memory of another processor is generated by the time the operation is completed, the set data of these data and address is stored in the corresponding transmission buffer (loop of steps 12 and 14). ). FIG. 3 shows the state in which the set data of the data and the address is stored and written in the transmission buffer for each processor. The pattern of the accumulated data is illustrated differently for each processor in order to clearly indicate from which processor the accumulated data is output.

Each processor has its own operation A
As soon as is completed (YES branch of step 15), the set data accumulated in all the transmission buffers in the own processor is block-transferred to another processor corresponding to each transmission buffer (step 16). For example, the contents of the transmission buffer Sij of the processor Pi can be changed from the processor Pi to the processor P.
Block transferred to j.

One format of the transmission packet at that time is shown in FIG. The transmission packet stores a reception processor number storage area 61 for storing a reception processor number, a transmission processor number storage area 62 for storing a transmission processor number, a data length storage area 63 for storing a data length of transmission data, and data. Data storage area 64
And is configured. The data storage area 64 can accommodate one or more sets of data to be transmitted and an address on a memory in a destination processor that stores the data.

The processor that receives the transmission packet temporarily stores the set data of the transmission packet in the reception buffer corresponding to the processor that is the transmission source of the transmission packet (step 17). For example, the transmission buffer S of the processor Pi
The contents of ij are block-transferred from the processor Pi to the processor Pj, and the processor Pj temporarily stores the contents of the received packet in the reception buffer Rij corresponding to the processor Pi in its own processor.

The transfer status of the set data from the transmission buffer to the reception buffer of each processor is shown in FIG.

If all the processors have completed the operation of step 12 and have transferred the set data of the transmission buffer to the corresponding processors and temporarily stored the transferred set data in the corresponding reception buffers, they are all processed simultaneously. All processors are synchronized so that the next operation can be started (step 17).

Next, each processor reads the set data of the data and the address in the reception buffer and writes the data indicated by the set data to the address indicated by the set data in the memory of its own processor (step 19).

FIG. 5 shows a situation in which data is written from the reception buffer of each processor to its own memory. The pattern of the area in the memory M clearly indicates from which processor the data is transmitted.

Next, each processor performs operation B using the data transmitted from the other processor and stored in its own memory (step 20).

In this embodiment, the operation B is an operation that is performed using the received data and does not cause writing to the memory of another processor, and the operation A described above is a writing to the memory of another processor. Is a calculation that can occur.

When this operation B is completed in all processors, synchronization is established among all processors (step 21). This is to prevent the reception buffer of a certain processor from being disturbed by the inter-processor communication after the next operation A or the like is started, and to check the processing end of this parallel computer system in step 22.

When the processing of this parallel computer system is not completed in step 22, the process returns to step 12 and the operation described above is repeated until the processing is completed.

As described above, in the inter-processor communication system of the present embodiment, each processor is provided with a transmission buffer and a reception buffer corresponding to each communication partner processor, and block transfer is performed. Can be significantly reduced and the parallel processing effect can be improved.

[0034]

As described above, according to the interprocessor communication system of the present invention, a transmission buffer and a reception buffer corresponding to each communication partner processor are prepared for each processor and block transfer is performed, so that the number of communication between processors can be increased. It has the effect that it can be greatly reduced and the parallel processing effect can be improved.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of an interprocessor communication system of the present invention.

FIG. 2 is a state schematic diagram showing a secured state of a transmission buffer and a reception buffer.

FIG. 3 is a state schematic diagram showing a writing state in a transmission buffer.

FIG. 4 is a state schematic diagram showing a block transfer state from a transmission buffer to a reception buffer.

FIG. 5 is a state schematic diagram showing a situation in which data is transferred from a reception buffer to a memory.

FIG. 6 is a data format diagram showing a data storage state of a packet.

[Explanation of symbols]

 11 to 22 Steps in Flowchart 61 Received Processor Number Storage Area 62 Transmitted Processor Number Storage Area 63 Data Length Storage Area 64 Data Storage Areas Pi, Pj, Pk Processors Mi, Mj, Mk Memory Sij, Sik, Sji, Sjk, Ski, Skj Transmit buffer Rji, Rki, Rij, Rkj, Rik, Rjk Receive buffer

Claims (2)

[Claims] 1. In an interprocessor communication system of a parallel computer, which comprises a plurality of processors each having a memory, each of the plurality of processors has a transmission buffer for temporarily storing information to be transmitted to another communication partner processor. A buffer preparation step of preparing for each communication partner processor a reception buffer for temporarily storing information received from the other communication partner processor, and a buffer preparation step of preparing a plurality of processors for each predetermined communication. A transmission buffer writing step of writing and accumulating in a corresponding transmission buffer a set of data to be transmitted to the other communication partner processor and a write address of this data in the other communication partner processor; and the plurality of processors, respectively. After the completion of the predetermined calculation, the transmission A block transfer step of performing block transfer of the information stored and stored in the buffer to the corresponding other communication partner processor; and the plurality of processors respectively transmitting the information transferred from the other communication partner processor to the other communication partner. A reception buffer writing step of writing to the reception buffer corresponding to the processor; and a memory write for the plurality of processors to write the data of the reception buffer to the address of the memory of the own processor corresponding to the write address sent as a set with the reception buffer. An interprocessor communication method comprising the steps of: 2. In the buffer preparation step, if the amount of data to be communicated between the processors is known, a transmission buffer and a reception buffer corresponding to this amount are prepared. A transmission buffer and a reception buffer with a data amount corresponding to the block transfer are prepared, and thereafter, every time these buffers become full, an area corresponding to the data amount corresponding to the one block transfer is dynamically secured and these are allocated. 2. The interprocessor communication system according to claim 1, wherein preparation is made for linking.