JP3033646B2 - Communication method between processors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system between processors, and more particularly, to a communication system between processors of a parallel computer including a plurality of processors.

[0002]

2. Description of the Related Art A parallel computer system comprising a plurality of processors, each having a memory, and a network for transferring and synchronizing data among these processors, has a function distribution and a load distribution. For the purpose of increasing the speed and reliability of the microprocessor, the microprocessor has been widely used with the advancement of the performance of the microprocessor and the integration of the memory.

Communication between processors in such a so-called loosely coupled multiprocessor system is performed in the form of message communication, and a packet communication system or the like is used.

In this inter-processor communication system, that is, for example, in the transfer of data from a processor Pi to another processor Pj, conventionally, a plurality of words having a continuous address in a memory of the processor Pi are stored in the processor Pj.
In the case where the data is transferred to consecutive addresses in the memory included in the system, the block transfer is performed by starting the inter-processor communication once.

However, in other cases, for example,
Transfer of a plurality of words having non-consecutive addresses in the memory of the processor Pi or the processor Pj
In the case where a plurality of words are transferred to non-consecutive addresses of the memory of the above, the communication between the processors is performed one word at a time, and the communication between the processors is activated a plurality of times.
Is being done.

[0006]

The communication between the processors is 1
As a result, the overhead of creating a communication packet on the transmission side and the overhead due to an interruption on the reception side necessarily occur.

Therefore, in the above-mentioned conventional inter-processor communication system, when transferring a plurality of words related to non-consecutive addresses, the above-mentioned overhead is generated by the number of times related to the number of transferred words, and the overhead is increased. This causes a problem that a sufficient parallel processing effect cannot be obtained.

An object of the present invention is to provide a transmission buffer and a reception buffer corresponding to each communication partner processor in each processor and perform block transfer, thereby greatly reducing the number of inter-processor communications and improving the parallel processing effect. It is to provide a communication method between processors.

[0009]

According to a first aspect of the present invention, there is provided an inter-processor communication system for a parallel computer comprising a plurality of processors each having a memory, wherein the plurality of processors each have another communication partner. providing a transmission Baffua for temporarily storing information to be transmitted to the processor for each of the other communication party processor also provides a reception Baffua for temporarily storing information received from the other communication party processor for each of the other communication party processor A buffer preparation step, wherein the plurality of processors each perform a predetermined operation to transmit data to the other communication partner processor and a write address of the data in the other communication partner processor as a set, and the corresponding transmission buffer Writing a transmission buffer for writing and accumulating the data in the buffer; A block transfer step of performing a block transfer to the other communication partner processor corresponding to the information written and stored in the transmission buffer after completion of the predetermined operation, and the plurality of processors each comprising the other communication partner processor Writing the information transferred from the receiving buffer to the receiving buffer corresponding to the other communication partner processor, and the plurality of processors correspond to the writing address transmitted as a pair with the data of the receiving buffer. And writing to an address of the memory of the own processor.

(B) The plurality of processors are the other processors.
Upon receiving the information transferred from the communication partner processor,
Respectively transferred from the other communication partner processor
Information corresponding to the other communication partner processor.
Write to the receive buffer and save the data in the receive buffer
This corresponds to the write address sent as a pair.
Writing to the address of the memory of the own processor
It is characterized by.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the interprocessor communication system of the present invention.

FIG. 2 shows an example of a parallel computer system that performs the interprocessor communication system of the present embodiment. This parallel computer system comprises three processors Pi, Pj and Pk, which are connected by a network. In the figure, the network is schematically illustrated by connecting each processor with a line.

Each processor has the same configuration, a memory for storing data necessary for processing of its own processor, and a result of the processing.
A transmission buffer that temporarily stores data to be transmitted to another processor for each destination processor, and temporarily stores data required for own processing received from another processor for each transmission source processor as a result of processing by another processor. And a receiving buffer.

For example, taking the processor Pi as an example,
The processor Pi stores a memory Mi for storing data necessary for processing of the processor itself, and a transmission buffer Sij for temporarily storing data to be transmitted from the processor Pi to the processor Pj as a result of the processing (a suffix ij indicates that the processor Pi transmits the processor Pj. Indicates that it receives, the same applies hereinafter)
A transmission buffer Sik for temporarily storing data to be transmitted from the processor Pi to the processor Pk;
It has a receiving buffer Rji for temporarily storing data required for its own processing received from j, and a receiving buffer Rki for temporarily storing data required for its own processing received from the processor Pk.

FIGS. 3 to 5 schematically show how data exchanged between processors is transferred as the interprocessor communication system is executed.

The operation of this embodiment will be described with reference to FIGS.

First, each processor secures a transmission buffer for temporarily storing data to be written to the memory of another communication partner processor and a reception buffer for temporarily storing data received from another processor for each communication partner processor (step 11). . This may be provided in the main memory in each processor, or may be provided as a separate memory.

When the number of words to be transferred from each processor to another processor is known in advance, a buffer corresponding to the number of words to be transferred is reserved. Prepares a buffer for one block transfer at first, and dynamically reserves an area for one block transfer each time the buffer becomes full thereafter, and prepares to connect them by a link.

In FIG. 2, the transmission buffers Sij and Sik and the reception buffers Rji and Rki are secured in the processor Pi, the transmission buffers Sji and Sjk are secured in the processor Pj, and the reception buffers Rij and Rkj are secured in the processor Pk. The state where the transmission buffers Ski and Skj and the reception buffers Rik and Rjk are secured is illustrated.

Next, each processor performs a predetermined operation A (step 12). As for the processor Pi, the data required for the operation A is stored in the memory Mi owned by itself, so that a predetermined operation A is performed. Mi (step 13), and when writing to the memory Mj of another processor, for example, the processor Pj, the data to be written and the address on the memory Mj to store the data are paired to form a processor in the processor Pi. The transmission data to Pj is written to the transmission buffer Sij for temporarily storing (Step 14). In this way, each time data to be written to the memory of another processor is generated until the operation is completed, a set of the data and the address is accumulated in the corresponding transmission buffer (the loop of steps 12 and 14). ). FIG. 3 shows a state in which a set of data and address is stored and written in the transmission buffer for each processor. The accumulated data is shown with different patterns for each processor in order to clearly indicate from which processor the data is output.

Each processor performs an operation A in its own processor.
Is completed (YES branch of step 15), the set data accumulated in all the transmission buffers in the own processor is block-transferred to another processor corresponding to each transmission buffer (step 16). For example, the content of the transmission buffer Sij of the processor Pi is changed from the processor Pi to the processor Pij.
Block transfer to j.

FIG. 6 shows one form of the transmission packet at that time. The transmission packet stores a reception processor number storage area 61 for storing a reception processor number, a transmission processor number storage area 62 for storing a transmission processor number, a data length storage area 63 for storing the data length of transmission data, and stores data. Data storage area 64
It is comprised including. The data storage area 64 can accommodate at least one set of data to be transmitted and an address on a memory of a destination processor for storing the data.

The processor that has received the transmission packet temporarily stores the set data of the transmission packet in the reception buffer corresponding to the processor that has transmitted the transmission packet (step 17). For example, the transmission buffer S of the processor Pi
The contents of ij are block-transferred from the processor Pi to the processor Pj, and the processor Pj temporarily stores the contents of the received packet in the reception buffer Rij corresponding to the processor Pi in its own processor.

FIG. 4 shows the state of transfer of the set data from the transmission buffer to the reception buffer of each processor.

If all the processors have completed the operation in step 12 and have transferred the set data of the transmission buffer to the corresponding processor and temporarily stored the transferred set data in the corresponding reception buffer, Then, synchronization is established between all processors so that the next operation can be performed (step 17).

Next, each processor reads the set data of the data and the address in the reception buffer and writes the data indicated by the set data to the address indicated by the set data in the memory of the own processor (step 19).

FIG. 5 shows a situation in which data is written from the receiving buffer of each processor to its own memory. The pattern of the area in the memory M clearly indicates from which processor the data is transmitted.

Next, each processor performs the operation B using the data transmitted from the other processor and stored in its own memory (step 20).

In the present embodiment, the operation B is an operation performed using the received data and does not cause writing to the memory of another processor, and the operation A described above is a writing to the memory of the other processor. Is calculated.

When this operation B is completed in all processors, synchronization is established between all processors (step 21). This is for the purpose of preventing the reception buffer of a certain processor from being disturbed by the inter-processor communication after the start of the next operation A and the like, and for checking the processing completion of this parallel computer system in step 22.

If the processing of the parallel computer system is not completed in step 22, the operation returns to step 12 again and repeats the above operation until the processing is completed.

As described above, in the inter-processor communication method according to the present embodiment, the transmission buffer and the reception buffer corresponding to each communication partner processor are prepared in each processor and block transfer is performed, whereby the number of inter-processor communications is increased. Can be greatly reduced, and the parallel processing effect can be improved.

[0034]

As described above, according to the interprocessor communication method of the present invention, the transmission buffer and the reception buffer corresponding to each communication partner processor are prepared in each processor and block transfer is performed, whereby the number of interprocessor communication times is increased. Can be greatly reduced, and the parallel processing effect can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing one embodiment of an inter-processor communication system of the present invention.

FIG. 2 is a schematic diagram showing a state of securing a transmission buffer and a reception buffer.

FIG. 3 is a schematic diagram showing a state of writing to a transmission buffer.

FIG. 4 is a schematic diagram showing a state of block transfer from a transmission buffer to a reception buffer.

FIG. 5 is a schematic state diagram showing a situation in which data is transferred from a reception buffer to a memory.

FIG. 6 is a data format diagram showing a data storage state of a packet.

[Explanation of symbols]

 11 to 22 Steps in the flowchart 61 Receive processor number storage area 62 Transmit processor number storage area 63 Data length storage area 64 Data storage area Pi, Pj, Pk Processor Mi, Mj, Mk memory Sij, Sik, Sji, Sjk, Ski, Skj Transmit buffer Rji, Rki, Rij, Rkj, Rik, Rjk Receive buffer

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-186407 (JP, A) JP-A-53-5939 (JP, A) JP-A-4-336639 (JP, A) JP-A 5- 12220 (JP, A) JP-A-63-221452 (JP, A)

Claims (1)

(57) [Claims] An inter-processor communication method for a parallel computer comprising a plurality of processors each having a memory, wherein each of the plurality of processors temporarily stores information to be transmitted to another communication partner processor. A buffer preparing step for preparing a buffer for each of the other communication partner processors, and preparing a reception buffer for temporarily storing information received from the other communication partner processor for each of the other communication partner processors; and A transmission buffer writing step of performing a predetermined operation and writing a data to be transmitted to the other communication partner processor and a write address of the data in the other communication partner processor in a corresponding transmission buffer, and accumulating the data. The plurality of processors are respectively before and after the predetermined calculation is completed. A block transfer step of performing block transfer to the other communication partner processor corresponding to the information written and accumulated in the transmission buffer; and the plurality of processors respectively transmit the information transferred from the other communication partner processor to the other communication partner processor. A receiving buffer writing step of writing to the receiving buffer corresponding to the partner processor; and the plurality of processors writing the data of the receiving buffer to an address of the memory of the own processor corresponding to a writing address transmitted as a pair with the receiving buffer. And a writing step .