JPS6289162A - Data processor for multi processor - Google Patents

Abstract

PURPOSE:To preserve an maintain the plural communication data independent of a processing speed between processors, prevent omission of the data and system down of all systems and attain a highly efficient data communication. CONSTITUTION:A processor P11a successively searches a communicating pointer 3a by a PUSH operation and forms a pointer a1. A memory managing processor 5 detects that a flag of the pointer a1 is '0', forms a data pointer and sets 'm1' of a memory address in a communication data memory 4 for storing the data. The processor P11a writes the communication data in the memory address 'm1' in the communication data memory 4 by a WRITE operation. A processor P21b of a receiving side reads the pointer a1 from the communicating pointers 3a by a POP operation, the data of the memory address 'm1' is read from the communication data memory 4, at the same time read is end, the processor moves to a RECEIVE operation and resets a synchronizing flag to '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor data processing device that synchronizes data communication between processors in a multiprocessor system.

[Conventional technology]

Figure 4 shows the overall configuration of a general multiprocessor system. In Figure 6, (1a) to (li) are processors, and (2) is data access performed by each processor (1a) to (11). It is a common memory.

When data communication is performed in a multiprocessor system having the above configuration, a system configuration as shown in FIG. 5 has conventionally been adopted.

In the figure, (la) and (lc) are processors on the data sending side, (lb) and (ld) are processors on the data receiving side, and (10a) and (10b) are buffers for data communication between each processor. The functional data memories (lla) and (llb) are flags for synchronizing data exchange between processors.

The memories (10a) and (10b) and the flag sections (lla) and (llb) indicating flag states are respectively stored in specific address spaces in the common memory (2) (see FIG. 4).

Each of the processors (la) to (1d) basically processes data independently, and the processing operations therebetween are asynchronous. However, when data communication is required between processors, it is necessary to synchronize data exchange between the processors.

Next, a method of synchronized data communication in a conventional multiprocessor system will be explained with reference to the flowchart of FIG.

For example, processor P2(l) is more efficient than processor P1(la).
To explain the case of data communication to b) as an example, first, the processor Pl (la) reads the flag part (lla) of the common memory (2) and checks whether it has been reset to "0°". That is, Flag section (lla)
If the data memory (10a) is reset by the processor P2 (1b), data can be written to the data memory (10a) (S-1), and if the data memory (10a) is in the data writeable state, the processor P1 (la)
writes the data to be transmitted to the processor P2 (lb) to the data memory (10a) (S-2), and after completing writing the data to the memory, the processor Pl (la
) sets the flag (11a) to "1'°" and completes the data transmission process (S-3).

On the other hand, the processor P2 (1b) on the data receiving side reads the flag section (11a) and checks whether the flag is set (S-1"). As a result, the flag "
1”, the processor P2 (1b) reads communication data from the data memory (10a) (S
-2′), after data reading is completed, processor p2(l
b) resets the flag to "Q II" and completes the data reception process (S-3');
When performing data communication next time, confirm that the flag has been reset and then perform data transmission processing again.

Processor P3 (lc) to processor P4 (1d)
Data communication to is also the same as above.

[Problem that the invention seeks to solve]

Since the conventional multiprocessor 2 data processing device is configured as described above, the address space of the data memory for communication between each processor is fixedly allocated, and the data memory can only be used for one communication. Since only the address space for data is secured, if processor P1 is faster in data transfer processing than processor P2, or if processor P2's data transfer processing is congested, processor P1 will transfer the next communication data via the data memory.

cannot be sent to processor P2, and processor P1 must either enter a data transfer hold operation or discard the current data in favor of new data generated by processor P1. There were problems such as system-wide congestion or data loss.

This invention was made to solve the above-mentioned problems by completely synchronizing data communication between processors and preventing system-wide congestion or data loss due to unsynchronization. The object of the present invention is to obtain a multiprocessor data processing device capable of processing data.

[Means for solving problems]

A data processing device for a multiprocessor according to the present invention shares a plurality of fixed data memories so that the address space can be allocated in a variable structure according to the data length, and also provides a plurality of pointers for specifying the address space. , create/delete this pointer for each communication data unit,
Each transmitting/receiving processor writes and reads communication data with reference to this pointer, and synchronizes data communication between the processors.

[Effect]

In this invention, the address space of the data memory is made variable so that multiple allocations can be made, so communication data can be stored regardless of the difference in data transfer speed between processors, thereby preventing system-wide congestion. Furthermore, since data loss does not occur, the reliability of the system is improved, and since the memory area is shared, hardware resources can be used effectively.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The configuration of the multiprocessor system is the same as that shown in FIG. In the first part, (3a) and (3b) are communication pointers for managing communication data, (4) is a communication data memory that stores communication data, and (5) is a memory management processor that centrally manages the data. be. Note that each communication pointer (3a), (3b) and communication data memory are both configured in a common memory (2) and allocated to a determined address.

The configuration of each of the communication pointers (3a) and (3b) is shown in FIG. In the figure, (al) to (aa) indicate each pointer. Each pointer consists of a data pointer that indicates the allocated address for storing communication data in the communication data memory [4], a data length, and a flag for communication synchronization. be done.

These communication pointers (3a) and (3b) are QUEU
It has an E (queue) configuration, and each time data transmission processing is completed, the pointer is updated to the next pointer content. Also, the size of QUEUE and the number of pointers are set to a predetermined size due to system constraints. Furthermore, the size of communication data memory is also limited. ) Next, the operation of an embodiment of the present invention having the above configuration will be explained according to the flowchart shown in FIG. The explanation will proceed by taking as an example the communication of data from processor Pl (la) to processor P2 (lb).

First, in the data transmission process of processor Pl (la), processor P1 (la) Pt1S)! The communication pointer (3a) is sequentially searched by the operation, and the pointer (
al) and stores the communication data in the communication data memory (4).
The pointer (al) that generated the data pointer to be stored in
) is "1", and the data pointer, data length, and flag are all "0". In this initial state, the memory management processor (5) uses the pointer (al)
It detects that the flag is "θ'°, generates a data pointer, and sets the memory address "■1" in the communication data memory (4) where the data is to be stored in the data pointer (S-tt ).

As described above, if the memory address m1 is set in the data pointer, processor P1 (1a)
The communication data is written to the above memory address "m1" in the communication data memory (4) by the TE operation (S-12). After the data writing process is completed, the processor Pt (la
) enters the 5END operation of communication data, and sets the synchronization flag to "1" (S-13).

Note that if the synchronization flag is set to "l" in a PUSH operation other than the initial state, the communication pointer (
3a) is sequentially searched and the next ink (a2) is newly generated.

On the other hand, the processor p2 (tb) on the communication data receiving side is P
In the OP operation, the pointer (a) is transferred from the communication pointer (3a).
1) and refer to the contents (S-21). First, the synchronization flag is detected, and if "1P" is set, the data at the memory address "ml" indicated by the data pointer is read from the communication data memory (4). Read out (S-22).

Upon completion of data reading, processor p2 (Ib)
The process moves to the RECEIVE operation (S-23), and the synchronization flag is reset to aa Oto. At this point, the pointer (
al) is set to the initial state, returns a data pointer to the memory management processor (5), and the memory address "lllll1l" indicated by the data pointer becomes free and can be allocated as a memory area for the next data communication.Next, The contents of the pointer (a2) are sequentially shifted to the pointer (al), and the contents of the pointer (aa) are shifted to the pointer (a2) (three times in the figure), and reception is completed.

The memory management processor (5) has a communication data memory (4).
), it checks the length of the data memory in response to data pointer requests from each processor, secures the necessary area, and then generates a data pointer. When the reception from each processor is completed, the corresponding data pointer is deleted to make the area empty. If a new memory area cannot be secured in response to a request from the processor, a new data pointer cannot be generated.
Update the previous pointer 0 For example, if the pointer (al) is in use and data communication has not yet been completed (when the flag is "1"), the data pointer indicated by the data pointer (al) is reset, and the processor is overridden only at this time.

Furthermore, if communication data is accumulated due to some kind of traffic jam, the pointer will eventually reach a full state, but even at this time, the previous pointer will be updated and the latest data will be stored in the communication data. For example, if the data up to pointer (a3) is in use and data communication is not completed, the data pointer indicated by data pointer (a3) is reset and the data is overridden.

In addition, although two processors were shown in the above embodiment, processor P3 (lc) and processor P4 (1d)
Similarly, in general, by providing pointers between n processors, data communication can be performed in the same manner.

〔Effect of the invention〕

As described above, the present invention has a configuration in which communication data pointers are provided to synchronize data communication, so that multiple pieces of communication data can be saved regardless of the processing speed between processors, and data loss can be prevented. Also, it has the effect of preventing the entire system from going down without being affected by processing congestion of the processor, and enabling high-rate data communication.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of a multiprocessor data processing device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a communication pointer, FIG. 3 is an operation flowchart of data communication in this embodiment, and FIG. 4 5 is a general configuration diagram of a data processing device using a multiprocessor system, and FIG. 5 shows the entire system of a conventional multiprocessor data processing device.
FIG. 6 is an operational flowchart of data communication in a conventional example. In the figure, (1a) to (1d) are processors, (2)
is a common memory, (3) is a communication pointer, (4) is a communication data memory, and (5) is a memory management processor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] In a multiprocessor data processing device that includes a plurality of processors and a common data memory that temporarily stores communication data exchanged between these processors, a memory management processor, data length information of communication data, and the data Stores communication data information consisting of specific address information in the common memory generated by the memory management processor based on the length information, and communication synchronization flag information that synchronizes data communication between processors that transmit and receive data. 1. A multiprocessor data processing device characterized by comprising a communication pointer and synchronizing data communication between processors.