JPH03204065A - Data transfer contention evading system in inter-processor communication - Google Patents

Abstract

PURPOSE:To evade contention in data transfer by performing transmission processing immediately when neither first nor second state is established, and performing the processing again after setting reception preparation completion information RR at a holding state in the case other that. CONSTITUTION:When neither already transmitted RR nor already received RR exists, both an RR transmitted flag 106 and an RR received flag 108 are reset. When an RR transmission request for the certain transmission subchannel of the channels of a processor 200 is generated, RR transmission control processing is executed. Since both the flag 106 and the flag 108 are reset in the RR transmission control processing, RR transmission processing based on the RR transmission request is executed after the reset of the flags are confirmed and the flag 106 is set. In other words, the RR including the address of its own PCE 100, that of an opposite PCE, a transmission subchannel number, a reception subchannel number, etc., is sent to the opposite PCE via a transmission buffer 103 and a serial bus 300.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer conflict avoidance method in inter-processor communication.

[Prior Art] As a method for inter-processor communication, various methods have been proposed or put into practical use, and one of them is, for example, Japanese Patent Laid-Open No. 58-158732 and Japanese Patent Laid-Open No. 58-1921.
A processor-to-processor connection device (hereinafter referred to as PCE) having a function as seen in Publication No. Each subchannel is independently associated with other subchannels to set up a pair of communication buses, and a PCE having a function of assembling a transmission frame etc. in place of the processor is used, and each processor is connected to the above. There is an inter-processor communication system that connects to a serial bus via a PCB such as , and enables direct transmission and reception of data between designated subchannels between multiple processors.

By the way, in such an inter-processor communication system, the communication overhead of the processor is small because the transmission frame is assembled on the PCB, and one PCB is shared by multiple subchannels of the channel. The amount of hardware is reduced. However, since multiple subchannels share the sending and receiving buffers in the PCB, unless some countermeasure is taken, data sending and receiving will conflict on one PCB, resulting in a situation where data cannot be received due to buffer busy, etc. It is possible. Therefore, the inventors of the present invention have devised the following several methods for avoiding contention in data transmission and reception.

(1) Method 1 ■First, basically, when the reception side subchannel is ready for reception, it sends a reception completion notification (hereinafter referred to as RR) to the transmission side indicating that. RR transmission processing is performed, and when the transmitting side receives the RR, RR receiving processing is performed in which it requests data from the transmitting side subchannel, and in response, the receiving side receives the data sent from the transmitting side subchannel. A configuration in which the data is transferred to a subchannel is adopted.

■If each PCB is in a state where it has already transmitted or received another RR and the data reception or data transmission has not been completed, the new RR transmission will be awaited and the RR reception will be delayed. Even if there is, I will refuse to receive it.

(2) Method 2 ■The same configuration as in Method 1 above (■) is adopted.

■If each PCB is in a state where it has already transmitted or received another RR and the data reception or data transmission has not been completed, the new RR transmission is deferred and the RR reception is suspended. R if there is
It receives R, but waits for RR reception processing. Furthermore, when transmitting an RR, a timer with a timer value unique to the own PCB is started, and if the data related to the sent RR is not transmitted by the time the timer times up, the data related to the sent RR is The reception is canceled, and if there is a waiting RR reception process, it is executed.

[Problem to be solved by the invention]

However, the above-mentioned method has the following problems.

・Problems with method 1: If another RR has already been sent or received and the data reception or data transmission related to it has not been completed, the reception itself is rejected even if the RR is received. , the RR sending source PCE must continue sending the RR repeatedly until the RR is received, which reduces communication throughput.

・Problems with method 2: If an RR is received in a state where another RR has already been transmitted or received and the data reception or data transmission related to it has not been completed, unlike method 1, the RR's Since reception is performed (however, RR reception processing is delayed), there is no reduction in communication throughput due to RR retransmission. However, for example, RR transmission processing and RR
Two PCEα and PGE3 that are not performing any reception processing
In this case, when the transmission of RR from PCEα to PGE3 and the transmission of RR from PGE3 to PCEα are done almost simultaneously, PCEα waits for the reception processing of the RR received from PGE3 and then sends the data from PGE3. On the other hand, PCEβ waits for the reception processing of the RR received from PCEα and waits for data to be sent from PCEα, and the processing does not proceed. This wait state is a PCE with a small timer value.
The process continues until the timer on the side times out, and then it is resolved, but the process does not proceed for a certain period of time determined by the timer value, resulting in a decrease in communication throughput.

The present invention has been made in view of these circumstances,
The purpose is to provide a data transfer conflict avoidance method in inter-processor communication that can avoid data transfer conflicts in each PCB by controlling the RR while suppressing a decrease in communication throughput as much as possible.

[Means to solve the problem]

In order to achieve the above object, the present invention connects each processor to a serial bus via a PCB,
Through these PCBs, each of the plurality of subchannels, which is a unit of multiplexed operation of the channel of each processor, is independently associated with other subchannels, and a pair of communication buses is set up, and when data is transferred, the receiving side In the inter-processor communication system, the receiving side notifies the transmitting side of the RR when the reception is ready, and the transmitting side performs reception processing on this RR and starts data transmission.
a first display means for displaying on the CB a first state that the RR has already been transmitted and the data reception related to the RR has not been completed; a second display means for displaying a second state; and when transmitting an RR, if neither of the first and second states is established, the transmission process is performed immediately; otherwise, the RR is transmitted. an RR transmission control means that puts the RR in a hold state and processes it again later; and when receiving the RR, if neither the first nor the second state is established, the reception processing is performed immediately, and the first state is established. If the source device address in the received RR is compared with the own device address, which one takes priority over the other, and when the current Rrl reception processing takes priority over the first state, RR reception control means performs waiting control for data reception depending on the first state, and otherwise puts the reception processing on hold and processes it again later.

[Effect]

In the data transfer conflict avoidance method in inter-processor communication of the present invention, the first display means of each PCB is
If the RR has already been sent from E and data reception is not yet completed, the first status to that effect is displayed, and
If the own PCE has already received and processed the RR and the data transmission related to it has not been completed, the second display means displays a second state to that effect, and the receiving side subchannel is ready for reception. Therefore, when each PCB attempts to transmit an RR, the RR transmission control means of each PCB
the first and second display means with reference to the first and second display means of
If none of these conditions hold true, the transmission process is performed immediately; otherwise, the RR is put on hold and processed again later. On the other hand, each PCE receives r? from other PCEs.
When performing R reception processing, the RR reception control means of each PCB refers to the first and second display means of its own PCB and displays the first
If the second condition is not established, the reception process is performed immediately, and if the first condition is established, the reception process is performed according to the comparison result between the source device address in the received RR and the own device address. If one of them is given priority and the current Rrl reception processing is given priority over the first state, performing waiting control for data reception in the first state,
In other cases, data transfer conflicts are avoided by putting the reception process on hold and processing it again later.

[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of main parts showing an example of the configuration of a PCB to which the present invention is applied. The PCBloo in this example has a subchannel which is a unit of input/output operation of the channel of the processor 200, and a subchannel for one-to-one correspondence.
00 is channel interface (channel I/F) 1
It is connected via 02. It is also connected to a serial bus 300 to which other PCBs (not shown) are connected in FIG. 1 via a bus interface (not shown). That is, in a bus interconnection system to which the present invention is applied, a plurality of processors are each connected to a bus-type serial bus via a PCB, as shown in FIG. This is a system in which a plurality of processors are each connected to a loop-type serial bus via a PCB, and FIG. 1 shows a portion of the system. Here, each PCB is assigned a unique address, and in the present invention, the priority direction in the event of a data transfer conflict is determined based on the magnitude of this address.

Referring again to FIG. 1, the PCE 100 includes a controller 1
01. Channel I/F 102. Transmission buffer 103.
Receive buffer 104. Transmission processing queue 105. R.R.
Sending and sending flag 106 Waiting for reception processing 107 . R
R received flag 108. Pig reception waiting flag 10
9. Own PCE address latch 110 and comparison RWII
It has I. Note that the basic function of the PCBloo of the present invention is to associate each subchannel of the channel of the processor 200 with each subchannel of the channel of other PCBs on a one-to-one basis, and to directly transfer data between specified subchannels between multiple processors. Regarding the function that enables transmission and reception of
This is similar to the PCB described in Japanese Patent No. 8-192159.

FIGS. 2 to 6 are flowcharts showing an example of processing related to data transfer conflict avoidance executed by the control unit 101,
The configuration and operation of this embodiment will be described below with reference to each figure.

When the r'cE 100 attempts to transmit an RR on the transmission subchannel of the channel of the processor 200 (a subchannel corresponding to a task that transmits data), the processor 200 transmits an RR regarding the RR received via the serial hash 300. When attempting to perform RRR processing of requesting data to the reception subchannel of the channel (subchannel corresponding to the task that receives data), the status of PCEloo is as follows:
Depending on the presence or absence of R, it can be divided into the following cases.

(1) When RRR is sent ■There are no sent RRs or received RRs.

■Only sent RRs are available.

■Received R1’? Only available.

■There are both sent and received RRs. However, in this case, data reception for the already transmitted RR is in a waiting state.

(2) When RRR is sent ■There are no sent RRs or received RRs.

■Only sent RRs are available.

■Only received RRs are available.

■There are both sent RR and received RR. However, in this case as well, data reception for the already transmitted RR is in a waiting state.

Each case will be explained below. In addition, in the following explanation,
When there is an RRR transmission request or RR reception, the transmission processing waiting queue 105 and the receiving processing waiting queue 1 in FIG.
It is assumed that no RRR request or received RR is stored in 07.

(1) When RRR is sent ■If there are no sent RRs or received RRs.

In this case, R1' in FIG. The transmitted flag 106RR and the received flag 108 are both off.

When an RR transmission request is generated for the transmission subchannel of the channel of the processor 200, the RRR signal control process shown in FIG. 3 is executed. In this RRR signal control process, R
Since both the R transmission/transmission rough flag 106 and the RR received flag IO8 are off, the process proceeds to processing S13 via processing Sll and S12, and after the RR transmission/transmission rough flag 106 is turned on, the RRR reception request is sent in processing S14. Based on <RRR
communication processing is executed. That is, the RR including the address of the own PCE 100, the address of the other party's PCB, the sending subchannel number, the receiving subchannel number, etc.
．． Serial number 300''; is sent to the other party's PCB.

■When there is only a previously sent RR In this case, the RR transmission rough flag 106 in
Since the RR credit card flag 108 is off, in the RRR credit control process in FIG.
[required for RR transmission] k is the transmission processing waiting queue 10
It is stored in 5. That is, the RR transmission process is put on hold. This pending RRR request is processed again when data reception for the already transmitted RR is completed. That is, when the data reception for the already transmitted RR is completed, the fourth
In the process 326 shown in the figure, the RR transmission flag 106 is turned off and the waiting queue process in FIG.
5 and transmitted to the other party's PCE in step S14 in FIG.

■If there are only received RRs.

In this case, the RR transmission/transmission flag 106 in FIG.
Since the RR credit flag 108 is on, the RRR communication control process shown in FIG. 3 proceeds to process S15 through processes S11 and S12, and the RRR communication request is stored in the transmission process waiting user 105. That is, the RR transmission process is put on hold. This pending Rrl transmission request is the received R1'? will be processed once the data transmission is completed. That is, for the received RR, the process S4 in FIG.
When RRR signal processing is performed and data is transmitted from the transmission subchannel of the processor 200 accordingly, the data is transferred to the transmission buffer 103 . The data is sent to the other party's PCB via the serial number 300, and when the data transmission is completed, the RRR credit flag 108 is turned off in process S33 through process S32, and process 334 is performed.The waiting queue process shown in FIG. is executed, the suspended Rrl transmission request is taken out from the transmission processing waiting queue 105 in process S42, and RRR transmission processing is performed in process S14 in FIG.

■If both sent RR and received RR are present.

In this case, I'? Since both the R transmission completion flag 106 and the RRR transmission completion flag 108 are on, in the RRR transmission control process of FIG. 3, the RRR transmission request is stored in the transmission processing waiting 4' knee 105 in step S15. That is, the RR transmission process is put on hold. This pending RRR request is processed when data reception for the already transmitted RR and data transmission for the already received RR are completed.

(2) When RRR is sent ■If there are no sent RRs or 5 received RRs.

In this case, the rlR transmission transmission rough flag 106RR in FIG.
The received flag 108 is set to OFF.

When the receiving router 104 receives an RR including its own PCB address via the serial bus 300, the RRR communication control process shown in FIG. 2 is executed.

This l'? In the R reception control process, the RR transmission/transmission flag 1
06 and the RRR credit card flag 108 are both turned off. Proceed to processing S3 via processing S1 and S2, and R
After the RR credit flag 108 is turned on, <RRR message processing is executed based on the received RR in step S4. That is, a data request is made to the transmission subchannel in the reception RR.

■If there are only sent RRs.

In this case, the rlR transmission transmission rough flag 106 in FIG.
Since the RRR credit flag 108 is off, the second
In the RRR signal control process shown in the figure, the process goes through process 5IS5 and then process S8.
Proceed to. In this process s8, the source PCV in the received RR is
, the address and the own PCB address are determined by the comparator 11 in FIG.
1, and if the own PCB address is smaller, the process proceeds to process S7 via process S6 in order to give priority to data reception for the already transmitted RR that has already been transmitted by the own PCB. That is, the received RR is stored in the reception processing waiting queue I07, and the RRR transmission processing is put on hold. This suspended R
The RR transmission process is performed again when data reception related to the prioritized already transmitted RR is completed. Note that processing S6 is for performing the RRR reception processing of processing S4 when a second or subsequent RR in a series of data reception related to already received RRs is received.

On the other hand, if the own PCB address is larger, the process proceeds to step S9 to give priority to RRR transmission processing, and after turning on the data reception waiting flag 109 in FIG. 1 to wait for data reception for the already transmitted RR. , processing S3
After that, RRR communication processing is performed in step S4.

Data reception control is performed as follows when data is transmitted from the other party's PCB for a previously transmitted RR for which data reception has been scheduled.

When the data related to the already transmitted RR is received by the reception buffer 104 via the serial hash 300, it is recognized in step S21 of the data reception process in FIG. 4 that the data reception waiting flag 109 is on. The process waits for data reception processing in processing S22 without proceeding to data reception processing S23. The waiting time for Party B's data reception processing is 41
The previously processed received RR-ζ is released when the data transmission is completed. That is, when the data transmission related to the already received RR is completed, the RRR acknowledgment flag 108 is cleared in step S33 of the data sending process in FIG. 5, and the data reception wait flag 10 is cleared in step S34.
9 is turned on, the flag is turned off in step S35, and when it is recognized in step S36 that reception waiting data exists, step 1s2 in FIG.
The process advances to step 3, and the awaited data reception process is executed. As a result, the data stored in the reception buffer 104 in FIG. 1 is transferred to the designated reception subchannel ζ, and then the process proceeds to step S24 in FIG. 2 points in the series of data reception at the 81st point ready to receive the next data.
The transmission process for the next RR is performed, and if the data reception is complete, the process proceeds to process 526.

In addition, the PC in determining the priority direction in the case of data transfer contention
The size relationship of the B address may be the opposite of the relationship described above, but all P addresses connected to the serial number 300
It is necessary that the CBs operate under the same conditions.

■If there are only received RRs.

In this case, the RR transmission/transmission flag 106 in FIG.
Since the RR credit flag 108 is on, in the RRR credit control process in FIG. 2, processes S1, S2. Proceeding to process S7 via S6, the received RR is placed in the reception process waiting queue 107.
, and RRR communication processing is put on hold. This suspended RRR signal processing is processed when data transmission related to the received RR is completed.

■If both sent RR and received RR are present.

In this case, the RR transmission/transmission flag 106 in FIG.
Since both R credit completion flags 10B are on, in the RRR communication control process of FIG. 2, processes Sl, S5. Proceeding to step S7 via S6, R1'? concerning the received RR is processed. Reception processing is put on hold.

This suspended RRR signal processing is executed at the time when data reception related to the already transmitted RR and data transmission related to the already received RR are completed.

The operation of this embodiment has been described above for each case. Note that the above operation is such that when there is an RRR transmission request or RR reception, there is no RRR transmission request or reception RR in the transmission processing waiting queue 105 and reception processing waiting queue 107 in FIG.
It is assumed that these are not stored, but if they are stored, the following operation will be performed.

When data transmission or data reception is completed, the waiting queue process shown in FIG. 6 is executed, so the transmission processing waiting queue 10
5 or/and one or more RRR transmission requests and reception RRs are stored in the reception processing waiting queue 107, the RR transmission/transmission rough flag 106 is immediately turned on in step S13 of FIG. The process is started, or the RRR credit flag 108 is turned on in process S3 in FIG. 2, and the RRR credit process is started in process S4.

Therefore, when a new RRR request occurs, a new RRR
At the time of transmission, the transmission processing waiting queue 105. When an RRR request and/or a received RR is stored in the reception processing waiting key 107, the RR transmission/transmission flag 106 or R1'
? The received flag 108 is on and the new RR
R transmission requests and new received RRs are sent to the transmission processing waiting queue 105.
．． It will be stored in the reception processing waiting queue 107.

Then, process S42 in FIG. In S43, the oldest R
Since the RR request and received RR are taken out from the transmission processing waiting queue 105 and the reception processing waiting queue 107, the pending RRR sending request 3 received RR will be processed on a first-come, first-served basis. Note that when the RRR transmission request and the received RR are both stored in the transmission processing waiting queue 105 and the receiving processing waiting queue 107, in the sixth processing S41, the R1 is sent according to the predetermined priority order. '? It is determined whether to process the transmission request or the received RR.

Finally, we will explain how data transfer conflicts are resolved by priority control based on the size of PCB addresses, which is one of the features of the present invention. This will be explained with reference to the figures. In addition,
In FIG. 7, vertical lines indicate each PCB, and arrows connecting the vertical lines indicate RR and data exchange. Also, the address of each PCE #00 to #02 is 00 01 0
2, and here PCE#00-→PCE#01PC
E#01-+PCE#02 PCE#02→PCE#
It shows a situation where RR transmission of OO is competing.

First, at point a in Figure 7, °ζ is 1' after the RRR signal?
This is R reception, and the source PCB address (02 in this case) of the received RR(3) according to FIG. 2 is compared with the own PCB address (00 in this case). And own PCE
Since the address is smaller, T? r? (3) Bitter R
Waiting for RR communication processing RR sent by own PCB (1)
Priority is given to data reception for

The odor ζ at point c is opposite to point a and is larger at the own PCE address, so the received RR(1), RR(
The RRR transmission process related to 2) is performed to give priority to data transmission from the own PCB. As a result, data (1) is transmitted from PCE#O1 to PCE#00, and data (3) is transmitted from PCEO2 to PCE#01.

At this time, PCE #01 starts waiting control for data reception related to the already transmitted RR (2), and PCE #02
Then, waiting control for data reception regarding the already transmitted RR (3) is started.

At point d, the data (
1) and the data reception has not yet been completed, so R
Sending R(4) to PCE #01. And P.C.E.
#01 is the next data (2) in response to this Rrl (4)
is sent to PCE#OO, and since PCE#OO has now completed data reception, it returns ACK (1) to PCB#01.

On the other hand, since PCE #01 is already transmitting data at point C, data (3) sent from PCB #02 is not received due to data reception waiting control for already transmitted RR (2), which has already started at point C. Processing is pending. Then, at point f, immediately before PCE#01 to PCE#00
Since data transmission to point e has been completed, the above data reception queue is canceled and PCE#02, which was being received at point e,
RR(5) is sent to PcE#02 as it is ready to receive the next data. 4
) is sent, and RR(6) is sent again.

At point g, since the data reception from PCE#Ol has been completed, the RR from PCE#02, which was in a pending state at point a, is
Regarding (3), RRR transmission processing has been executed and data has been transmitted to PCE #02.

The lighting is the same as point e, and since PCE #02 is receiving data, the data reception waiting control for the already sent RR (3) started at point C causes the P that was sent at point g to be
Data from CE#00 is awaited.

Point 1 indicates that the data transmission from PCE #02 to PCE #01 has completed data (5), so the data reception waiting for the already sent RR (3) is canceled, and the PC that received the data at the point
The data receiving process from E#00 has been performed, and since this is the last data, a normal end response ACK (2) has been sent.

(Effects of the Invention) As explained above, according to the data transfer conflict avoidance method in inter-processor communication of the present invention, if another RR has already been transmitted or received and the data reception or data transmission is completed. When an RR is received in a state where there is no RR, the RR is received in the same way as method 2 described in the conventional technology section, so there is no reduction in communication throughput due to retransmission of the RR as in method 1. In addition, if a new RR is received while another RR has already been transmitted and the data reception related to it has not been completed, method 2
Instead of uniformly waiting for the reception processing related to the received RR, as in the above, data transfer competition is performed by giving priority to one of the two depending on the comparison result between the source PCE address in the received RR and the own PCE address. In order to avoid this, the communication throughput is improved compared to the method 2 which uses a timer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a PCB to which the present invention is applied; FIGS. 2 to 6 are flowcharts showing examples of processing related to data transfer conflict avoidance executed by the control unit of the PCB; FIG. 8 is a time chart showing an example of an operation when RRR is combined between three PCEs, and FIGS. 8 and 9 are diagrams showing an example of the overall configuration of a data communication system to which the present invention is applied. In the figure, 100...PCB (interprocessor connection device) 200
. . . Processor 300 . . Serial Has 101 . Send/send rough flag 07... Reception processing waiting queue 108... R, R received flag 109... Data reception waiting flag 110...
Own PCB address lunch 111... Comparator old language applicant 2 people other than NEC Corporation

Claims (1)

[Scope of Claims] Each of the processors is connected to a serial bus through an inter-processor connection device, and each of the plurality of sub-channels, which is a unit of multiple operation of the channel of each processor, is connected to a serial bus through an inter-processor connection device. are independently associated with other subchannels to set up a pair of communication buses, respectively, and at the time of data transfer, when the receiving side is ready for reception, the receiving side notifies the transmitting side of a reception preparation completion notification, In the inter-processor communication system in which the transmitting side performs reception processing related to this reception preparation completion notification and starts data transmission, if the reception preparation completion notification has already been sent to each of the inter-processor connection devices and data reception has been completed. a first display means for displaying a first state that there is no data; and a second display means for displaying a second state that the reception preparation completion notification has already been received and the reception process has been completed and the data transmission related to the notification has not been completed. When transmitting a reception preparation completion notification, if neither of the first and second states is satisfied, the transmission process is performed immediately; otherwise, the reception preparation completion notification is put on hold and then re-transmitted. A reception preparation completion notification transmission control means to process the reception preparation completion notification, and when receiving the reception preparation completion notification, if neither of the first and second states is established, the reception processing is performed immediately, and the first state is established. If so, give priority to either one according to the comparison result between the source device address in the received reception preparation completion notification and the own device address, and give priority to the reception processing of the current reception preparation completion notification over the first state. and a reception preparation completion notification reception control means that performs waiting control for data reception according to the first state when the data is received in the first state, and otherwise puts the reception processing on hold and processes it again later. Data transfer conflict avoidance method in inter-processor communication.