JPH03204065A - Data transfer contention evading system in inter-processor communication - Google Patents

Data transfer contention evading system in inter-processor communication

Info

Publication number
JPH03204065A
JPH03204065A JP34177789A JP34177789A JPH03204065A JP H03204065 A JPH03204065 A JP H03204065A JP 34177789 A JP34177789 A JP 34177789A JP 34177789 A JP34177789 A JP 34177789A JP H03204065 A JPH03204065 A JP H03204065A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
rr
transmission
flag
reset
pce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34177789A
Other versions
JP2911931B2 (en )
Inventor
Takayuki Hoshiko
Kazuhiko Yamada
Mitsuhiro Yamaga
Original Assignee
Hitachi Ltd
Nec Corp
Nippon Telegr & Teleph Corp <Ntt>
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To evade contention in data transfer by performing transmission processing immediately when neither first nor second state is established, and performing the processing again after setting reception preparation completion information RR at a holding state in the case other that.
CONSTITUTION: When neither already transmitted RR nor already received RR exists, both an RR transmitted flag 106 and an RR received flag 108 are reset. When an RR transmission request for the certain transmission subchannel of the channels of a processor 200 is generated, RR transmission control processing is executed. Since both the flag 106 and the flag 108 are reset in the RR transmission control processing, RR transmission processing based on the RR transmission request is executed after the reset of the flags are confirmed and the flag 106 is set. In other words, the RR including the address of its own PCE 100, that of an opposite PCE, a transmission subchannel number, a reception subchannel number, etc., is sent to the opposite PCE via a transmission buffer 103 and a serial bus 300.
COPYRIGHT: (C)1991,JPO&Japio
JP34177789A 1989-12-29 1989-12-29 Data transfer conflict avoidance scheme in a communication between processors Expired - Lifetime JP2911931B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34177789A JP2911931B2 (en) 1989-12-29 1989-12-29 Data transfer conflict avoidance scheme in a communication between processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34177789A JP2911931B2 (en) 1989-12-29 1989-12-29 Data transfer conflict avoidance scheme in a communication between processors

Publications (2)

Publication Number Publication Date
JPH03204065A true true JPH03204065A (en) 1991-09-05
JP2911931B2 JP2911931B2 (en) 1999-06-28

Family

ID=18348687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34177789A Expired - Lifetime JP2911931B2 (en) 1989-12-29 1989-12-29 Data transfer conflict avoidance scheme in a communication between processors

Country Status (1)

Country Link
JP (1) JP2911931B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06309281A (en) * 1993-04-20 1994-11-04 Nec Corp Inter-processor communication system
JPH08249295A (en) * 1995-03-15 1996-09-27 Kofu Nippon Denki Kk Message controller
JP2007004690A (en) * 2005-06-27 2007-01-11 Hitachi Ltd Storage control method, system, and program

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06309281A (en) * 1993-04-20 1994-11-04 Nec Corp Inter-processor communication system
JPH08249295A (en) * 1995-03-15 1996-09-27 Kofu Nippon Denki Kk Message controller
JP2007004690A (en) * 2005-06-27 2007-01-11 Hitachi Ltd Storage control method, system, and program
JP4531643B2 (en) * 2005-06-27 2010-08-25 株式会社日立製作所 Storage control method, system and program

Also Published As

Publication number Publication date Type
JP2911931B2 (en) 1999-06-28 grant

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