JPH06309182A - Interrupt processing method - Google Patents

Abstract

PURPOSE:To provide the interrupt processing method which performs filtering processing by software and executes interrupt processing without any delay at the time of the occurrence of an interrupt. CONSTITUTION:In the interrupt processing circuit where an interrupt occurs by the fall of an interrupt signal supplied to a CPU, the level of the interrupt signal is periodically discriminated to store two latest levels, and they are read out and the level of the interrupt signal is discriminated again at the time of the occurrence of an interrupt, and interrupt processing is performed when two latest levels are equal to each other and they are different from the level of the interrupt signal discriminated again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention determines whether or not an interrupt signal is a normal one in an interrupt processing circuit in which an interrupt is generated at the rise or fall of an interrupt signal supplied to a CPU (central processing unit). The present invention relates to an interrupt processing method for identifying, and particularly to an interrupt processing method for preventing the influence of noise by performing a filtering process by software.

[0002]

2. Description of the Related Art In an electronic device using a CPU,
The state of the sensors and switches arranged in each part of the device
The PU sequentially detects as the program progresses, and various controls are performed based on the detection result. However,
In some cases, regardless of the program currently being executed, when a sensor or switch state is detected, it is necessary to perform various kinds of processing in real time at the timing of this detection.

Therefore, in order to meet such a request, when a signal from a specific sensor or switch is input, the CP
U is interrupted, an interrupt program is activated, and specific processing is preferentially performed.

Interrupts to the CPU are usually performed by detecting the rising or falling of the input signal. However, the level of the input signal is not always stable, and it is transient due to noise or chattering. There are many times when the level becomes uneasy. Therefore, interrupt processing may be erroneously performed.

Therefore, in order to prevent the influence of noise,
It is common practice to provide a low-pass filter circuit composed of a coil and a capacitor for removing high frequency components in the input circuit. However, providing a low-pass filter circuit composed of such individual components is
It is not preferable because the number of parts increases and an area for arranging parts is required.

Therefore, as disclosed in Japanese Patent Laid-Open No. 63-311402, it has been proposed to perform the filtering process by software. In the device described in the publication, when a signal from the input circuit is read at a constant time interval by an interrupt signal and the input signal changes for a predetermined time width or longer, for example, when the same state continues twice, The filtering process is performed by making

[0007]

However, in the filtering process described in the above publication, the input signal is regarded as valid when a certain time width or more elapses after the external interrupt occurs, and the interrupt process is performed. Has occurred,
There is a problem that it takes a long time to determine that it is an interrupt, and real-time processing cannot be performed.

Further, since an interrupt is generated, a check is performed at regular intervals, and when there is no change, it is determined that an interrupt has occurred. Therefore, the state of the interrupt signal before the interrupt is checked is checked. Absent. Therefore, if the interrupt is a device that looks at the falling edge of the interrupt signal, if the noise S1 as shown in FIG. 3B occurs at any time before the interrupt occurs, it is regarded as an interrupt occurrence. Will end up.

Therefore, an object of the present invention is to provide an interrupt processing method capable of performing a filtering process by software and capable of executing the interrupt process without delay when an interrupt occurs.

[0010]

In order to achieve the above object, the present invention provides an interrupt processing method of an interrupt processing circuit in which an interrupt is generated at a rising edge or a falling edge of an interrupt signal supplied to a CPU. The level of the interrupt signal is determined, the latest level for at least two times is stored, the latest level for at least two times is read when an interrupt occurs, the level of the interrupt signal is determined again, and the latest level for at least two times is determined. Is the same, and the latest level for at least two times and the level of the interrupt signal determined again are different, interrupt processing is performed.

[0011]

The CPU discriminates the level of the interrupt signal at regular intervals and stores the latest level for at least two times. When an interrupt occurs, the latest level is read out and the level of the interrupt signal is determined again, the latest levels for two times are the same, and the latest level for at least two times and the level for the interrupt signal determined again are the same. Only when they are different, interrupt processing is performed. As a result, the interrupt processing is not performed when the interrupt noise occurs. Re-determining the level of the interrupt signal takes only a few μs, so the interrupt process can be performed immediately after the interrupt occurs.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the present invention will be specifically described below based on embodiments with reference to the drawings.

FIG. 1 is a block diagram of an interrupt processing circuit to which the interrupt processing method of the present invention is applied.

ROM for CPU 1 via bus 2
(Read-only memory) 3 and RAM (random access memory) 4 are connected. CPU1 in ROM3
Stores the main program executed in and the interrupt program executed when an interrupt occurs. Also, RA
M4 is used as a table or work area when the program is executed. Further, the interrupt signal INT from the interrupt signal generation circuit 1 is supplied to the CPU 1. The interrupt signal generation circuit 1 is for generating an interrupt signal INT that is at a high level for a certain period of time, for example, when a specific switch or sensor provided in the device is turned on. In this embodiment, the CPU 1 is interrupted at the falling edge of the interrupt signal INT. Further, the interrupt signal INT is supplied to the bus 2 via the interface 6, and the interrupt signal INT
Is set by the CPU 1 at regular intervals, for example, 1
It is determined every 0 ms.

Next, the operation of the above interrupt processing circuit will be described with reference to the flowchart of FIG.

The CPU 1 has a built-in timer for 10
The level of the interrupt signal INT is discriminated via the interface 6 and the bus 2 every ms, and the latest two levels of data are sequentially updated and written in the table provided in the RAM 4. Therefore, in the table of the RAM4, the interrupt signal I 10 ms before the present time
The NT level and the interrupt signal INT level 20 ms before are written.

When the interrupt signal INT falls, an interrupt occurs, the CPU 1 refers to the table of the RAM 4 and the level of the interrupt signal INT 10 ms before and 20
The level of the interrupt signal INT before ms is determined (steps 101 and 102), and if both are high levels, the current level of the interrupt signal INT is further determined.
(Step 103) If the level is low, it is determined that the interrupt is a true interrupt and interrupt processing is performed. Re-determining the level of the interrupt signal takes only a few μs, so the interrupt process can be performed immediately after the interrupt occurs.

First, the case where the regular interrupt signal INT is input will be described. In this example,
As shown in FIG. 3A, the regular interrupt signal INT is a signal that rises from a low level to a high level, maintains the high level for a relatively long time, for example, about 1000 ms, and then falls to the low level. Shall mean.

In this case, when the signal falls, the CPU
An interrupt occurs at 1, 10ms before and 20m from the current time
Both of the interrupt signals INT before s are at high level and the current level is at low level, so that the process proceeds to steps 101, 102, 103 and 104 to perform interrupt processing.

Next, as shown in FIG. 2B, when the noise S1 in the positive direction is supplied to the CPU 1 as an interrupt signal, an interrupt occurs in the CPU 1 at the falling edge of the noise S1, but 10 ms before the current time. Since it is low level before and 20 ms before, interrupt processing is not performed.

Further, as shown in FIG. 3C, when the noise S2 in the negative direction is mixed in the interrupt signal INT, the CPU 1 is interrupted at the falling edge of the noise S2. In the case of the example shown in FIG. 7C, both the level before 10 ms and the level before 20 ms are high levels, so the routine proceeds to step 103. Since the CPU 1 refers to the table in the RAM 4 and slightly determines the level, when the level of the interrupt signal INT is determined again in step 103, the level returns to the high level. Therefore, in this case, interrupt processing is not performed, and noise does not cause malfunction.

In the above embodiment, the case where the interrupt occurs at the falling edge of the interrupt signal has been described, but the present invention can be applied to the case where the interrupt occurs at the rising edge of the interrupt signal.

[0023]

As described above, according to the present invention,
When an interrupt occurs, it determines whether the interrupt signal remains at a predetermined level for a certain period of time, and then determines whether the level has changed. Therefore, it is possible to perform the interrupt processing without being affected by noise and without delay from the rise or fall of the interrupt signal.

[Brief description of drawings]

FIG. 1 is a block diagram of an interrupt processing circuit to which an interrupt processing method of the present invention is applied.

FIG. 2 is a flowchart for explaining an interrupt processing method of the present invention.

FIG. 3 is a timing chart for explaining processing when a regular interrupt signal or noise is input.

[Explanation of symbols]

1 ... CPU, 2 ... Bus, 3 ... ROM, 4 ... RAM, 5 ...
Interrupt signal generation circuit, 6 ... Interface

Claims (1)

[Claims] 1. An interrupt processing method for an interrupt processing circuit in which an interrupt is generated at the rising or falling edge of an interrupt signal supplied to a CPU, wherein the level of the interrupt signal is determined at a constant cycle, and the latest level for at least two times is determined. When the interrupt occurs, the latest level for at least two times is read and the level of the interrupt signal is determined again, the latest level for at least two times is the same, and the latest level for at least two times is stored. The interrupt processing method is characterized in that the interrupt processing is performed when the level of the interrupt signal and the level of the interrupt signal determined again are different.