JPH06309151A - Data processor - Google Patents

Abstract

PURPOSE:To efficiently perform data processing by changing a machine cycle required for the arithmetic operation of a multiplier corresponding to effective data word length. CONSTITUTION:A control signal EN is set at '1' when the effective data word length shows 32 bits. While, the control signal EN is set at '0' when the effective data word length shows 16 bits, and '0' is inputted to the latch control terminal L of a latch 3, and the latch 3 outputs an input signal as passing it through as it is. Also, an AND circuit 4c is turned off, which disables input to the carry input Cin of an adder 4b with CLA on a low-order side. Also, all the bits of the output of the adder 4b with CLA on the low-order side are changed to '0's compulsorily since no control signal EN is inputted to another input of an AND circuit 4d, and it is outputted to a latch 5. Thereby, it is possible to shorten the propagation delay time of a carry signal propagated between the 32 bits on the low-order side of an adder with CLA at the final stage, and the multiplication of one machine cycle can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device composed of a semiconductor integrated circuit, and more particularly to a data processing device for processing digital data.

[0002]

2. Description of the Related Art A circuit configuration of a conventional data processing apparatus including a parallel multiplier and its operation content will be described with reference to FIG. The block surrounded by the broken line in the figure is a parallel multiplier. This multiplier uses the secondary Booth algorithm and carry save adder, and the input is 32 bits wide and the output is 63 bits wide.

The input side is connected to the ROM 1 via the multiplier latch 10.
The output of the Booth encoder 1 connected to the output of 4 is connected to a carry save adder 2 including a shift circuit. This carry save adder 2 has a multiplicand latch 11
The output of the RAM 13 is also connected via the multiplexer 12 and the output of the carry save adder 2 is the latch 1
It is designed to be input to 03. The output of the multiplier and the multiplicand from the latch 103 is the final stage adder 104 with CLA.
It is designed to be input to. The final multiplication result from the adder 104 with CLA at the final stage is latched by the latch circuit 5 and input to the ALU 6. This A
The output of the multiplexer 9 connected to the 32-bit wide data bus 15 is also input to the LU 6. The output of ALU6 is accumulator 7 with 63-bit width.
And is output to the data bus 15 via the tri-state buffer 8 having a 32-bit width.

On the other hand, in the apparatus shown in the figure, the reading of the ROM 14, the reading and writing of the RAM 13, and the calculation of the ALU each require one machine cycle, and the multiplication requires only two machine cycles.

First, at the beginning of the machine cycle, the RAM 13
Alternatively, the multiplier, which is one input of the multiplier, is latched by the multiplicand latch 11 from the data bus 15. Also ROM1
The multiplier, which is the other input of the multiplier from 4, is latched in the multiplier latch 10. The multipliers and multiplicands latched by the latch circuits 10 and 11 are latched by the latch circuit 103 inside the multiplier at the beginning of the next machine cycle, and by the end of the machine cycle, the final multiplication result from the adder 104 with CLA at the final stage. Is output and latched in the latch circuit 5 having the output of this multiplier as an input at the beginning of the next machine cycle.

Here, in the multiplier of FIG. 2, except for the internal latch 103, the time from the input of data to the multiplier to the output of the multiplication result is less than one machine cycle. By inserting the latch circuit 103 in front of the final stage adder 104 with CLA inside the multiplier, the multiplication is executed in two machine cycles.

[0007]

Conventionally, as described above, the effective word length of the data to be input to the multiplier is 3 bits.
In the case of 2 bits, it is natural to take 2 machine cycles for the calculation time. However, in the case of a processing device with general merit, the effective word length of data to be handled is not always constant. For example, when the effective word length is 16 bits. However, in view of the processing capability of the multiplier, even if the calculation is completed in one machine cycle, the calculation always requires two machine cycles, and there is a problem that the processing speed decreases.

The present invention has been made in view of the above-mentioned problems of the prior art, and its main purpose is to efficiently change the machine cycle required for the operation of the multiplier according to the effective data word length. It is to provide a data processing device capable of performing various data processing.

[0009]

SUMMARY OF THE INVENTION The above-described object is a data processing apparatus including a pipeline-type parallel multiplier including at least one latch circuit between a data input section and a data output section. In order to switch between the first state in which the data handled by the data processing device is latched in each machine cycle according to the effective word length by the latch circuit and the second state in which the input data is directly passed therethrough. Latch control means and data setting means for forcibly setting to 0 in the final stage adder in the parallel multiplier the bits that are equal to or less than the effective data word length viewed from the upper side of the data length. It is achieved by providing a data processing device characterized by:

[0010]

Thus, the latch control means for switching between the first state in which the data to be handled is latched every machine cycle according to the effective word length and the second state in which the input data is passed through as it is. By providing data setting means for forcibly setting the bits less than the effective data word length viewed from the upper side of the data length to 0 in the final stage adder in the multiplier, the effective data word length is It is equal to the bit width of the processing device, but if the bit width is close to it, it takes 2 machine cycles for the operation time of the multiplier, and if the effective data word length is considerably shorter due to the bit width of the device, for example less than half, the multiplication time Efficient operation can be performed according to the effective data word length, such as using one machine cycle.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of a data processing apparatus according to this embodiment. Input side is multiplier latch 10
The output of the Booth encoder 1 connected to the output of the ROM 14 via is connected to a carry save adder 2 including a shift circuit. The carry save adder 2 is connected to the RA via the multiplicand latch 11 and the multiplexer 12.
The output of M13 is also connected, and carry save adder 2
Is output to the latch 3. The latch 3 is provided with a latch control terminal L, and a NAND output of a control signal EN and a clock signal is supplied to the latch control terminal L via a NAND gate 16. Here, when "1" is input to the latch control terminal L of the latch 3, the latch 3 latches the input signal in synchronization with the clock signal, and "0" is input to the latch control terminal L of the latch 3. In this case, the latch 3 outputs the input signal as it is. The outputs of the multiplier and the multiplicand from the latch 3 are the upper CLA adder 4a and the lower CLA adder 4b, which will be described later, in the final stage CLA adder 4.
It is designed to be input to and.

The final stage CLA adder 4 is in charge of the addition of the upper side CLA adder 4a which is in charge of addition from the 33rd bit to the 63th bit of the upper bit side and the addition of 0th bit to the 32nd bit of the lower bit side. Carry output C of lower side CLA adder 4b and lower side CLA adder 4b
AND circuit 4c in which o is one of the inputs, and the output is connected to the carry input Cin of the upper CLA adder 4a
And an AND circuit 4d which receives the output of the lower CLA-added adder 4b as an input and whose output is connected to the latch 5. The same control signal EN that is input to the latch control terminal L is input to the other input of the AND circuit 4c and the AND circuit 4d.

The final multiplication result from the adder 4 with CLA at the final stage is latched by the latch circuit 5 and input to the ALU 6. The other input of the ALU 6 is also connected to the output of the multiplexer 9 connected to the data bus 15. The output of the ALU 6 is output to the data bus 15 via the accumulator 7 and the tristate buffer 8. The bit width of each block is the same as in FIG.

Next, the operating procedure of this embodiment will be described. First, when the effective data word length is 32 bits, the control signal EN becomes "1" and the same operation as the conventional circuit of FIG. 2 is performed. On the other hand, when the effective data word length is 16 bits, the control signal EN becomes "0", "0" is input to the latch control terminal L of the latch 3, and the latch 3 outputs the input signal as it is. Further, the AND circuit 4c is turned off, and the carry signal of the lower CLA adder 4b is not input to the carry input Cin of the upper CLA adder 4a. The output of the lower CLA adder 4b is AND
Since the control signal EN is input to the other input of the circuit 4d, all the bits are forcibly changed to "0" and output to the latch 5. In the figure, reference characters A and B indicate a multiplier and a multiplicand.

By doing so, the propagation delay time of the carry signal transmitted between the lower 32 bits of the adder with CLA in the final stage is almost eliminated, and the multiplication can be executed in one machine cycle.

[0017]

As is apparent from the above description, according to the present invention, the first state in which the data to be handled is latched every machine cycle according to its effective word length and the input data is passed through as it is. Latch control means for switching between the second state and the data setting for forcibly setting to 0 in the final stage adder in the multiplier, the bits having a length equal to or less than the effective data word length viewed from the upper side of the data length. By providing the means, the effective data word length is equal to the bit width of the data processor, but if the bit width is close to that, two machine cycles are used for the operation time of the multiplier, and the effective data word length is the bit width of the device. Is very short, for example, if it is less than half, one machine cycle is used for multiplication time, so that the number of machine cycles required for multiplication can be set more efficiently according to the effective data word length. It can, it is possible to perform efficient operations.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a data processing device to which the present invention is applied.

FIG. 2 is a block diagram showing a circuit configuration of a conventional data processing device.

[Explanation of symbols]

 1 Booth encoder 2 Carry save adder with shift circuit 3, 5, 10, 11, 103 Latch 4, 104 Final stage addition circuit of parallel multiplier 6 ALU 7 Accumulator 8 Tri-state buffer 9, 12 Multiplexer 13 RAM 14 ROM 15 Data bus 16 2-input NAND

Claims (1)

[Claims] 1. A data processor including a pipeline-type parallel multiplier including at least one latch circuit between a data input section and a data output section, wherein the latch circuit holds the data. Latch control means for switching between a first state in which the data handled by the processing device is latched for each machine cycle according to its effective word length and a second state in which the input data is directly passed through; and the parallel multiplication. A data processing device, comprising: data setting means for forcibly setting, to 0, a bit having a length equal to or less than the effective data word length viewed from the upper side of the data length in the final stage addition section in the device.