JPH06309054A - Voltage source circuit - Google Patents

Abstract

PURPOSE:To provide the voltage source circuit which does not decrease in maximum output voltage and can maintain an output voltage without being affected by the output current. CONSTITUTION:In the voltage source circuit which holds the output voltage at an output terminal OUT constant by supplying equal currents by a 1st current mirror circuit between the emitters and collectors of 1st and 2nd transistors(TR) Q11 and Q12 having their common-connected bases connected to resistors R3 and R4 dividing the voltage at the output terminal OUT, a current supplied from a 1st current mirror circuit side to the collector of the 2nd TR Q12 is reduced by as much as the base current supplied from a TR Q26. Further, a 2nd current mirror circuit 2, a 3rd current mirror circuit 3, etc., are provided so as to equalize the collector current of the 1st TR Q1 to the collector current of the 2nd TR Q12.

Description

Detailed Description of the Invention

[0001]

2. Description of the Related Art Generally, a voltage source circuit is widely used in electronic equipment in order to maintain stable operation. FIG. 3 shows a conventional voltage source circuit 31. The circuit configuration of FIG. 3 is as follows. Q11 to Q13 are NPN transistors, Q
21 to Q23 are PNP transistors, R1 to R4 are resistors, and I1
Is a constant current source.

In FIG. 3, the emitter of a base-collector short-circuited transistor Q21 forming a current mirror circuit is connected to a positive power supply terminal Vcc, and this transistor Q21 is used.
Is connected to the base of the transistor Q22. The collector of the transistor Q21 is connected to the collector of the transistor Q11.

The emitter of the transistor Q11 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the transistor Q12 and one end of the resistor R2. Resistance R2
The other end of is grounded to GND. Also transistor Q
The base of 11 is connected to the base of the transistor Q12 and also to the Vref terminal. Also, resistors R3 and R
One end of 4 is connected to the Vref terminal.

The emitter of the transistor Q22 is connected to Vcc. The collector of the transistor Q22 is connected to the collector of the transistor Q12 and the base of the transistor Q23. The emitter of the transistor Q23 is connected to the base of the transistor Q13 and also connected to the power source terminal Vcc via the constant current source I1.

The collector of the transistor Q23 is grounded to GND. The collector of the transistor Q13 is the power supply terminal V
It is connected to cc, and the emitter of the transistor Q13 is connected to the output terminal OUT. The other end of the resistor R3 is the output terminal O
It is connected to UT and the other end of the resistor R4 is grounded to GND. Next, the operation of this conventional example will be described.

First, assuming that the collector current of the transistor Q11 is IC (Q11), the base-emitter voltage of the transistor Q11 is VBE (Q11), and the base-emitter voltage of the transistor Q12 is VBE (Q12).
And the base potential of Q12 is R1 * IC (Q11) + VBE (Q11) = VBE (Q12) ... (1). Here, due to the current mirror circuit configuration of the transistors Q21 and Q22, the collector current I of the transistor Q11 is
C (Q11) and collector current IC (Q of transistor Q12
Regarding the relationship of 12), when the base current of the transistor Q23 is ignored, currents equal to each other flow. That is, IC (Q11) = IC (Q12) (2). Therefore, from equations (1) and (2), the transistor Q11
Assuming that the emitter area is 10 times the basic size, that is, the number of areas is 10, the collector current of R1 · IC (Q11) + VT ln {IC (Q11) / 10 · Is} = VT lnIC (Q12) / Is R1 IC (Q11) = VT ln 10 IC (Q11) = IC (Q12) = (VT / R1) ln 10 (3) Assuming that the voltage at the Vref terminal is Vref = Vr (4), the potential relationship at point A is 2 × Ic (Q11) × R2 = Vr−VBE (Q12) (5), and thus Vr is Vr = 2. × IC (Q11) × R2 + VBE (Q12) (6) Therefore, the output voltage Vout is Vout = (R3 + R4) Vr / R4.

[0007]

However, when output current capability is required, output voltage problems arise. Therefore, the operation when the output current flows will be described.

If the output current is Iout, the current amplification factor of the transistor Q13 is β (Q13), and the currents flowing through the resistors R3 and R4 are ignored, the base current IB (Q1 of the transistor Q15).
In 3), IB (Q13) = Iout / β (Q13). Therefore, assuming that the current flowing through the constant current source I1 is I, the emitter current IE (Q23) of the transistor Q23 is IE (Q23) = I-Iout / β (Q13), and the base current IB (Q23) of the transistor Q23 is IB (Q23) = (I−Iout / β (Q13)) / β (Q23) = I / β (Q23) −Iout / (β (Q13) β (Q23) ... (10) where IC (Q22 ) + IB (Q23) and IC (Q1
Negative feedback is applied and Vref is determined so that 2) becomes equal. However, if Iout increases from equation (10), IB (Q2
3) becomes small, and thus IC (Q12) becomes small.
As a result, there is a drawback that the potential of Vref drops and the output voltage Vout fluctuates.

In order to prevent the output voltage from being affected by Iout, the base of the NPN transistor Q18 is connected to the emitter of the NPN transistor Q18 via the resistor R between the emitter of the transistor Q13 and the output terminal OUT as shown in FIG. The collector of this NPN transistor Q18 to the power supply terminal V
A circuit configuration connected to cc can be considered.

Since the output section of this circuit is connected to Darlington, it is less affected by Iout than the circuit of FIG. However, considering the maximum settable voltage, there are the following problems.

Since the constant current source I1 is composed of a PNP transistor, if the saturated emitter-collector voltage of the PNP transistor is VCEPNPsat, the maximum settable voltage Voutmax of the circuit of FIG. 3 is Voutmax = Vcc- VBE (Q13) -VCEPNPsat.apprxeq.Vcc-1.0 [V] (12). However, the Voutmax of the circuit of FIG. 4 becomes Voutmax = Vcc-VBE (Q18) -VBE (Q13) -VCEPNPsat.apprxeq.Vcc-1.7 [V] (13), and the NPN transistor Q18 newly provided from FIG.
However, there is a drawback that the range of the set voltage is narrowed by the base-emitter voltage VBE (Q18).

The present invention has been made in view of the above points, and an object thereof is to provide a voltage source circuit in which the output voltage is not narrowed and the output voltage is not influenced by the output current.

[0013]

In order to solve the above problems, in order to solve the above problems, the common base is connected between the emitter and collector of the first and second transistors connected to the resistor for dividing the voltage at the output end. A first current mirror circuit formed of a pair of transistors for allowing equal currents to flow, and a current flowing between the emitter and collector to GN
First and second resistors leading to D, a third transistor whose emitter and collector are connected to the output end and power supply end, respectively, one end of which is connected to the power supply end, and the other end of which is the third transistor A constant current source connected to the base of
A fourth transistor whose emitter and collector are connected to the other end of the constant current source and GND, respectively, and a base of the fourth transistor is connected to a connection point between the first current mirror circuit and the second transistor. In the voltage source circuit, the collector of the fourth transistor and the GN
A second current mirror circuit is arranged between D and
A current equal to the current flowing between the emitter and the collector of the transistor of the third current mirror circuit is passed through one current path of the third current mirror circuit, and the other current path of the third current mirror circuit is applied to the base of the first current mirror circuit. A current equal to the current flowing through the one current path, and a current equal to the base current of the fourth transistor between the base of the first current mirror circuit and the emitter / collector of the first transistor. It has a circuit configuration in which a fifth transistor to be supplied is provided.

With the above configuration, the first current is equal to the base current supplied between the emitter and collector of the second transistor through the base of the fourth transistor.
The amount of current supplied from the current mirror circuit side of the second transistor can be reduced so that the current flowing between the emitter and collector of the second transistor does not depend on the current value flowing from the output end to the load side, and the second transistor The emitter of
The current flowing between the collector and the current flowing between the emitter and collector of the first transistor is kept equal. Furthermore, the maximum output voltage supplied from the output terminal to the load side is prevented from decreasing.

[0015]

FIG. 1 shows a first embodiment of the present invention. The circuit configuration of the first embodiment of the present invention will be described below. Q11 ~ Q
Reference numeral 15 is an NPN transistor, Q21 to Q26 are PNP transistors, R1 to R4 are resistors, and I1 is a constant current source.

As shown in FIG. 1, the voltage source circuit 1 of the first embodiment is similar to the voltage source circuit 1 of the conventional example shown in FIG. 3 in which one current path side is arranged between the collector and the ground of the transistor Q23. Current mirror circuit 2 is provided. The other current path side of the current mirror circuit 2 is connected to the one current path side of the second current mirror circuit 3.

The second current mirror circuit 3 is a transistor Q2 forming the current mirror circuit in FIG.
The other current path side is arranged between the base and the power source terminal Vcc of 1 and Q22.

More specifically, the collector of the transistor Q23 is connected to the base-collector of the transistor Q15 forming the first current mirror circuit 2, the emitter of the transistor Q15 is grounded, and the base of the transistor Q15 is a pair. Is connected to the base of the transistor Q14, the emitter of the transistor Q14 is grounded, and the collector of the transistor Q14 is connected to the base / collector of one transistor Q26 forming the second current mirror circuit 3.

The emitter of the transistor Q26 is connected to the power supply terminal Vcc, the base of the transistor Q26 is connected to the base of the paired transistor Q25, and the emitter of the transistor Q25 is connected to the power supply terminal Vcc. The collector is connected to the base of the transistor Q21.

Further, in FIG. 3, the emitter / base of a PNP transistor Q24 is connected between the base and collector of a transistor Q21 forming a current mirror circuit, and the collector of this transistor Q24 is connected to GND. Other configurations are the same as those of the voltage source circuit 31 shown in FIG.

That is, the emitter of the transistor Q21 is connected to the power source terminal Vcc, the collector of the transistor Q21 is connected to the base of the transistor Q24 and the collector of the transistor Q11. Transistor Q11
The emitter of is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the resistor R2 and also to the emitter of the transistor Q12.

The other end of the resistor R2 is grounded to GND, and the collector of the transistor Q24 is also grounded to GND.
The emitter of the transistor Q22 is connected to the power source terminal Vcc,
The collector of the transistor Q22 is connected to the base of the transistor Q23 and the collector of the transistor Q12.

The base of the transistor Q11 is connected to the base of the transistor Q12 and the Vref terminal, and the resistor R3
, And R4 at one end. The other end of the resistor R3 is connected to the output end OUT, and the other end of the resistor R4 is grounded to GND. The emitter of the transistor Q22 is connected to Vcc, the emitter of the transistor Q23 is connected to the base of the transistor Q13, and is also connected to the power supply terminal Vcc via the constant current source I1.

The collector of the transistor Q13 is the power source terminal Vcc.
The emitter of the transistor Q13 is connected to the output terminal OUT.

Next, the operation of this embodiment will be described. The output current is Iout, and the current amplification factor of the transistor Q13 is β (Q1
3) and neglecting the current flowing through the resistors R3 and R4, the base current IB (Q13) of the transistor Q13 becomes IB (Q13) = Iout / β (Q13) (14).

Therefore, assuming that the current flowing through the constant current source I1 is I, the emitter current IE (Q23) of the transistor Q23 is IE (Q23) = I−IB (Q13) = I−Iout / β (Q13) (15) Becomes Therefore, the current amplification factor of the transistor Q23 is β (Q
23), the base current IB of the transistor Q23 (Q2
3) is IB (Q23) = IE (Q23) / β (Q23) = (I−Iout / β (Q13)) / β (Q23) (16)

Further, the collector current I of the transistor Q23
C (Q23), collector current IC of transistor Q26 (Q2
6) The collector current IC (Q21) of the transistor Q21 has the following relationship due to the characteristics of the current mirror: IC (Q23) = IC (Q26) = IC (Q25) (17). Therefore, from the equation (17), Ic (Q25) = Ic (Q23) = I-Iout / β (Q13) (18)

Therefore, ignoring the base currents of the transistors Q21 and Q22, the base current IB of the transistor Q24 is
(Q24) becomes IB (Q24) = (I-Iout / β (Q13)) / β (Q24) (19). The relationship between the current amplification factors of the transistors Q24 and Q23 is β (Q24) = β (Q23) by using the elements having the same characteristics.

Therefore, the relation between the base currents of the transistors Q24 and Q23 is IB (Q24) = IB (Q23) (20) according to the equations (16) and (19), and thus the collector current IC of the transistor Q21.
(Q21) becomes IC (Q21) = IC (Q11) -IB (Q24) (21). Therefore, the collector current IC of the transistor Q22
(Q22) becomes IC (Q22) = IC (Q11) -IB (Q24) (22).

Collector current IC (Q22) and base current IB
Let IA be the sum of (Q23) and transistor Q1.
The voltage of the Vref terminal at the connection point of the resistors R3 and R4 is determined so that the collector current IC (Q12) of 2 and IA become equal. Therefore, from equations (20) and (22), IA = IC (Q22) + IB (Q23) = IC (Q11) -IB (Q24) + IB (Q23) = IC (Q11) (23).

Therefore, even if the output current increases, the current IA flowing through the collectors of the transistors Q11 and Q12 does not change, so the voltage at the Vref terminal does not change. Therefore, the output voltage does not change. Further, the maximum settable voltage Voutmax of the voltage source circuit 1 is the same as that in FIG. 3, and does not become narrow as in FIG.

FIG. 2 shows a voltage source circuit 1 according to the second embodiment of the present invention.
1 is shown. In this embodiment, the collector-emitter voltages of the transistors Q21 and Q22 are equalized based on the first embodiment,
It has a circuit configuration that is not subject to the Early effect (phenomenon).

That is, in FIG. 1, the transistor Q21
An NPN transistor Q16 having a collector and an emitter connected between the base of the transistor Q24 and the emitter of the transistor Q24, and the base of the transistor Q16 is connected to the transistor Q13.
And an NPN transistor Q17 having a collector and an emitter connected between the base of the transistor Q13 and the emitter of the transistor Q23.
The base of PN transistor Q17 is shorted to its collector.

The other structure is the same as that of FIG. Except for the effect of preventing the Early phenomenon, it has the same operation and effect as the first embodiment.

Note that the NPN transistors Q11 to Q15 in the embodiment of FIG.
The NP transistors Q21 to Q26 may be replaced by NPN transistors, and the positive power supply terminal Vcc may be replaced by a negative power supply terminal to output a negative voltage.

[0036]

As described above, according to the present invention, it is possible to obtain a circuit in which the output voltage is not affected by the output current without impairing the settable voltage range.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a voltage source circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a voltage source circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional voltage source circuit.

FIG. 4 is a circuit diagram of a voltage source circuit of a modification of the conventional example.

[Explanation of symbols]

 1 ... Voltage source circuit 2, 3 ... Current mirror circuit Q11 to Q15 ... NPN transistor Q21 to Q26 ... PNP transistor R1 to R4 ... Resistor I1 ... Constant current source OUT ... Output terminal

Claims (1)

[Claims] 1. A common base is formed by a pair of transistors that allow equal currents to flow between the emitter and collector of first and second transistors connected to a resistor that divides the voltage at the output. The current flowing between the first current mirror circuit and the emitter / collector is
First and second resistors leading to D, a third transistor whose emitter and collector are connected to the output end and power supply end, respectively, one end of which is connected to the power supply end, and the other end of which is the third transistor A constant current source connected to the base of
A fourth transistor whose emitter and collector are connected to the other end of the constant current source and GND, respectively, and a base of the fourth transistor is connected to a connection point between the first current mirror circuit and the second transistor. In the voltage source circuit described above, a second voltage is provided between the collector of the fourth transistor and GND.
Current mirror circuit is arranged, and a current equal to the current flowing between the emitter and collector of the fourth transistor is caused to flow through one current path of the third current mirror circuit, and the other current of the third current mirror circuit is supplied. From the road to the first
A current equal to the current flowing in the one current path is supplied to the base of the current mirror circuit, and the fourth transistor is connected between the base of the first current mirror circuit and the emitter / collector of the first transistor. A voltage source circuit comprising a fifth transistor for supplying a current equal to a base current.