JPH06308786A - Image forming device - Google Patents

Abstract

PURPOSE:To provide an image forming device capable of surely detecting and dealing with abnormality at an early stage and to suppress the image defect, a fault of the device, etc., as little as possible. CONSTITUTION:In the image forming device, which is provided with the DC controller 104 equipped with the CPU 101 for controlling a series of image forming operation, the composite power source 111 equipped with the CPU 108 for controlling electric power supplied to the device such as the halogen lamp 115, the first electrifier 116, the transferring electrifier 117 and the developing unit 118, and the communication means between the CPU 101 and the CPU 108, and where the electric power supply to the load is controlled for switching off when the abnormality of communication is detected by repeating the periodical communication between the CPU 101 and the CPU 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a copying machine or a printer having a microprocessor for sequence control and a microprocessor for controlling power supply to an internal load separately from the microprocessor. Is.

[0002]

2. Description of the Related Art Conventionally, when controlling a copying machine by a plurality of microprocessors, it is generally known that the control is performed while exchanging data by communication.

The control of the high-voltage power supply of the copying machine is known by performing feedback control so that it is constant with respect to a certain target value.

[0004]

However, in the case of a copying machine having a microprocessor for controlling the sequence of the apparatus and a microprocessor for controlling the low-voltage and high-voltage power supplies, it is supplied when an abnormality occurs in communication between the microprocessors. However, there is a problem that the power supply voltage is not supplied at a normal voltage, which may cause the device to stop operating, have a defective image, or have a hardware failure.

Further, since the abnormality of the circuit which performs the feedback control of the high voltage power supply is not detected, there is a problem that an image defect is caused due to the abnormality of the high voltage output, and it is specified which high voltage output abnormality is caused. Because it was not possible, it hindered quick service response.

Further, when detecting an abnormality in the circuit for performing feedback control of the high voltage power supply, there is a problem that noise for high voltage output is likely to occur in a signal around the abnormality detection circuit, and an erroneous detection is likely to occur.

The present invention has been made in order to solve the above-mentioned problems of the prior art. It is possible to detect an abnormality early and surely and deal with it, and it is possible to suppress image defects, device failures, etc. as much as possible. An object is to provide an image forming apparatus.

[0008]

Therefore, the image forming apparatus according to the present invention is provided with a first control means for controlling a series of image forming operations provided with a microprocessor and a load in the apparatus provided with the microprocessor. There is provided a second control means for controlling the power to be supplied, a communication means between the first control means and the second control means, and a communication abnormality detection means for detecting an abnormality in the communication. The present invention is intended to achieve the above-mentioned object by a configuration characterized in that when it is detected, control is performed to cut off the power supply to the load.

Further, the second control means compares the detection signal detecting the output value of the high-voltage power to the load with the output target value corresponding to the control signal input from the first control means to detect an abnormal output. It is an object of the present invention to achieve the above-mentioned object by a configuration having an output abnormality detecting means for detecting, and performing control to stop the output of high voltage power when an abnormality is detected.

[0010]

With the above structure, the communication abnormality detection means
When a communication abnormality is detected by the communication means, the power supply to the load is controlled so that the detected abnormality can be dealt with immediately and accurately, and image defects, device failures, etc. can be suppressed as much as possible.

Further, the output abnormality detecting means compares the detection signal obtained by detecting the output value of the high-voltage power to the load with the output target value corresponding to the control signal inputted from the first control means, whereby the output abnormality is detected. Therefore, the detected abnormality can be immediately and accurately dealt with, and image defects, device failures, etc. can be suppressed as much as possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the arrangement of the first embodiment.

Reference numeral 101 denotes a central processing unit (hereinafter referred to as CPU) which controls the sequence of the entire copying apparatus.
Reference numeral 102 denotes a read-only memory (ROM) that stores a control procedure (control program) of the copying apparatus.
1 reads signals from each sensor 106 according to the control procedure stored in the ROM 102 and drives each load (motor, clutch, solenoid, etc.) 105 to control the copying machine. Reference numeral 103 denotes a random access memory (RAM) which is a main storage device used as a storage area for input data, a work storage area, and the like.
These are in a board called DC Controller 104.

The switches and displays necessary for operating the copying apparatus are provided on the operation unit 107, switch inputs of the operator are given to the DC controller 104, and the DC controller 104 appropriately displays according to the instructions.

Reference numeral 108 denotes a CPU for controlling the power output such as low voltage power supply, high voltage power supply, and lamp dimming. 109 is a control procedure (control program) for power supply control and lamp dimming control
Is a read-only memory (ROM) that stores
U108 performs power supply control and lamp dimming control according to the control procedure stored in the ROM 109. Also, 1
Reference numeral 10 denotes a random access memory (RAM) which is a main storage device used as a storage area for input data, a work storage area, or the like. These are in a board called 111 Combined Power Supply.

A low voltage power source (+ 5V, + 24V, etc.) required in the copying machine is generated in the composite power source 111, and a low voltage power source control unit 112 for performing constant voltage control and an electrostatic latent image are generated on the photoconductor. , A high-voltage power supply control unit 113 for generating a high-voltage power supply required for transfer onto a copy sheet, and an exposure lamp 115.
Lamp regulator (CVR) 1 that controls the lighting voltage of the
14 and each of which is controlled by the CPU 108.

The high-voltage output generated by the high-voltage power supply controller 113 is supplied to the primary charger 116, the transfer charger 117, and the developing device 11.
8 respectively. From the low voltage power supply control unit 112, D
+ 5V supplied to the C controller 104 and + 24V supplied to each load 105 in the copying machine are output.

The + 5V power supplied to the CPU 108 in the composite power supply 111 is supplied from the AC line passing through the main switch 119 of the apparatus to the transformer 120, the rectification / smoothing circuit 112.
Is generated via. Further, the main switch 119 is a switch having a configuration such as a relay that can be turned off by a signal from the outside, and the DC controller 1
It is configured so that it can be turned off by a signal from the CPU 101 in 04.

CPU 101 in DC controller 104
And the CPU 108 in the composite power source 111 is, for example, the CPU 1
Parallel communication is performed by an 11-bit command / data line output from 01, a REQ (data request) signal, a 3-bit data line output from the CPU 108, and an ACK (data acknowledge) signal. Of course, this may be serial communication.

Reference numeral 122 denotes a display unit for displaying an abnormality when the CPU 108 detects the communication abnormality between the CPUs.
When the CPU 101 detects an abnormality, the main switch 119 is turned off by a signal to cut off the power supply of the entire device.

Next, the communication operation of the CPU of this embodiment will be described with reference to the timing chart of FIG.

CPU 101 in DC controller 104
Sets the communication contents in the 3-bit command line (CMD) and 8-bit data line (DATA). After that, the request signal (REQ) is raised to the H level to the CPU 108 in the composite power source 111. CPU10
When detecting the H level of the REQ signal, 8 stores the contents of the command data in the RAM 110 and raises the ACK signal (ACK) to the H level for the CPU 101.

When the CPU 101 detects the H level of the ACK signal, it lowers the REQ signal to the L level. CPU1
When 08 detects the L level of the REQ signal, it lowers the ACK signal to the L level. CPU101 is L of ACK signal
When the level is detected, the command data transmission is completed, and the next command data is set.
In this way, the CPU 101 and the CPU 108 perform communication while performing the handshake.

Further, in order to check whether the communication operation is normally performed, the CPU 101 makes a command data request to the CPU 108 at least once within a certain time T. That is, when the CPU 108 does not detect the H level of the request signal (REQ) within the fixed time T (T <T1), the CPU 108 determines that the CPU 101 or its peripheral circuit is abnormal and determines that the CPU 101
+ 5V supplied to etc., + 24V supplied to the load
A voltage OFF signal is input to the low voltage power supply control unit 112 in order to cut off the voltage.

During the copying operation, the exposure lamp 11
When the lamp 5 is on and high voltage is being output, the OFF signal is input to the lamp regulator 114 and the high voltage power supply control unit 113 to turn off the exposure lamp and the high voltage output. Further, the fact that the communication between the CPUs is disabled due to the abnormality of the CPU 101 and the apparatus is stopped is displayed on the display unit 122.

On the other hand, the CPU 101 sends a RE to the CPU 108.
The time from the rise of the Q signal to the rise of the ACK signal and the time from the fall of the REQ signal to the fall of the ACK signal are monitored, and when they do not rise within a certain time t (t <T2, At T3), the main switch 119 of the device is turned off to cut off the power supply to the entire device. At this time, the CPU 101 turns on the main switch.
Before the FF is performed, the fact that a communication error has occurred is displayed on the operation unit 107 for several seconds.

Next, the detailed operation of the present embodiment will be described with reference to the flow charts of FIGS.

FIG. 3 shows the CPU of the DC controller 104.
3 is a flowchart showing a communication abnormality detection operation of 101.

In FIG. 3, first, it is checked whether or not there is a data transmission request to the composite power source 111 in another sequence program (step S1). If there is no transmission request, it waits as it is, but if there is a transmission request, the command data to be transmitted is output to the I / O port (S2). After that, the REQ signal is turned on (S3) and the error timer is started (S4). A from the composite power supply side
It is judged whether the CK signal is turned on (S5), and if it is turned on, it means that the command data has been normally sent. Therefore, the error timer is reset (S6), and the R that was started up is reset.
The EQ signal is turned off (S7). Next, an error timer for determining whether the ACK signal started by the composite power source is turned off is started (S8). It is determined whether the ACK signal is turned off (S9). If the ACK signal is turned off, the command data change is permitted. Therefore, the error timer is reset (S10), and the process returns to the start.

The ACK signal is turned on by the judgment in step S5.
No or the ACK signal is OF in the judgment in step S9.
If the error timer is timed out in step S11 or step S12 without F, it is determined that an error has occurred in communication with the CPU 108 of the composite power source 111, and an error code is displayed on the operation unit 107 of the copying apparatus ( After a few seconds, the main switch 119 is turned off (S13) (S13).
14) Then, the power supply to the device is cut off.

FIG. 4 is a flowchart showing the communication abnormality detection operation of the CPU 108 of the composite power source 111.

On the composite power source side 111, first, an error timer for checking whether the DC controller turns on the REQ signal within a fixed time is started (S21). It is judged whether the REQ signal is ON (S22), and O
If N, the sent command data is stored in RAM (S23) and the error timer is reset (S2).
4). Then, since the command / data has been received, the ACK signal is turned on (S25). Next, an error timer for determining whether the REQ signal started by the DC controller is turned off is started (S26). It is determined whether the REQ signal is turned off (S27). If it is turned off, the DC controller has received the ACK signal, so the ACK signal is turned off (S28) and the error timer is reset (S29).

If the REQ signal is not turned on in step S22 or the REQ signal is not turned off in step S27 and the error timer is timed out in the judgment of step S30 or step S31, the DC controller 104
It is determined that an abnormality has occurred in the communication with the CPU 101, and a high voltage OFF signal is sent to the high voltage control unit (S32), and CVR1
An OFF signal of the exposure lamp is sent to 14 (S33). Furthermore, low voltage (+ 5V, + 24V) supplied to the load of the equipment
Is stopped (S34), and an error is displayed on the display unit 122 in the composite power source 111 (S35).

With the above configuration and control, when an abnormality occurs in the data communication between the DC controller 104 and the composite power source 111, the power is surely detected and the power is cut off, the power supply to the load is stopped, and the abnormality is displayed. Therefore, it is possible to minimize image defects and device failures.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the communication abnormality detection circuit diagram of FIG.

In the above-mentioned embodiment, each CPU detects whether the REQ signal and the ACK signal are normally exchanged by using the internal timer, but in this embodiment, the abnormality is detected by the hardware circuit as shown in FIG. It is composed.
The other structure is similar to that of the first embodiment, and the description thereof is omitted.

As the monitor signal of the REQ signal, an inverted signal of the REQ signal is input to a charge / discharge circuit composed of a resistor and a capacitor, and its output is input to the comparator 51. A fixed voltage is input to the other input of the comparator 51. With such a circuit configuration, it is possible to monitor the time from when the REQ signal becomes L level until it rises to the next H level.

When the REQ signal is not output for a certain time or longer, the charging time of the charging circuit becomes long and the output of the comparator changes.

The ACK signal monitoring signal is the REQ signal and the A signal.
The exclusive OR with the CK signal is similarly input to the charge / discharge circuit, and is generated by comparing the constant voltage with the comparator 52. With such a circuit configuration, it is possible to monitor the time from the rising edge of the REQ signal to the rising edge of the ACK signal or the time from the falling edge of the REQ signal to the falling edge of the ACK signal.

When the above time exceeds a certain value, the charging time of the charging circuit becomes long and the output of the comparator changes.

With the above structure, it is possible to detect an abnormality in the communication means between the DC controller and the composite power source, take the same measures as in the first embodiment, and achieve the same effects.

In other words, in the first and second embodiments, data communication is performed between the power supply to the load, each high-voltage power supply for image formation, the microcomputer that controls the exposure lamp, and the microcomputer that performs the sequence control. In the copying machine configured to perform, the abnormality in the communication is detected and the power supply to the load is cut off. Therefore, the operation of the apparatus occurs because the power supply voltage supplied due to the abnormality in the data communication is not supplied with a normal voltage. It is possible to suppress stoppages, defective images, and hardware failures. In addition, since the fact that the abnormality has occurred is displayed, quick service can be performed.

(Third Embodiment) FIG. 6 is a block diagram of the third embodiment. The same or corresponding parts as those of the first embodiment are designated by the same reference numerals, and the duplicate description will be omitted.

The block configuration of the present embodiment is similar to that of the first embodiment. In FIG. 6, in addition to the configuration shown in FIG. 1, a high voltage output controlled by the high voltage power supply controller 113 is used as the pre-image transfer charger 1
19 and separate charger 120 are added.

In this embodiment, when the CPU 108 detects an abnormality in the high voltage output, the output abnormality information is CPU1.
01 through a 5-bit data line. With this communication, the CPU 101 performing sequence control can determine which high voltage output is abnormal.

FIG. 7 is a detailed block diagram of the periphery of the high voltage output controller of the third embodiment.

CP of composite power source 111 for controlling high voltage output
When the U108 receives the high voltage value data and the ON data from the CPU 101 of the DC controller 104 for sequence control, each of the control circuits 121 to 12 in the high voltage power supply control unit 113 is received.
The pulse of PWM is output to 5. A high voltage output corresponding to this pulse width is generated in each of the control circuits 121 to 125 and sent to the primary charger 116, the transfer charger 117, the developing device 118, the pre-transfer charger 119, and the separation charger 120.

In this control circuit, an output monitor signal corresponding to the actual high voltage output is generated, and feedback control is performed based on this output to obtain a stable high voltage output. Further, this monitor signal is sent to the A / D converter 1
After being input to 26 to 130 and converted into digital 8-bit data, they are input to the CPU 108. CPU10
8 compares this value with the high voltage value (control target value) received from the CPU 101 to determine whether or not the high voltage control circuit is abnormal.

FIG. 8 is a timing chart of communication between the CPU 101 and the CPU 108. The configuration and timing for detecting a communication abnormality by the communication operation of the CPU and controlling and displaying the power output are the same as those described in the first embodiment with reference to FIG.

The data format of communication is as shown in FIG. 8, where command 0 is primary high voltage data and command 1 is
Is transfer high voltage data, command 2 is development bias data,
Command 3 is high voltage data before transfer, command 4 is high voltage data for separation, command 5 is lamp lighting voltage data, command 6 is ON / OFF of each high voltage and exposure lamp, command 7
Is a reserve.

CP according to this data format
U101 instructs the CPU 108 at what value to output each high voltage. By using this value as the target value and comparing it with the A / D converted output of the signal that monitors the actual output, each control of high voltage is detected. If any abnormality is detected, the high voltage or total high voltage is stopped and the error data ( 5 bits) corresponding bits are set. As a result, high-voltage control error information is transmitted from the CPU 108 to the CPU 101.

Next, the detailed operation of this embodiment will be described with reference to the flowchart of FIG.

FIG. 9 is a flow chart showing each high pressure process of the CPU 108.

First, it is judged whether or not a high voltage data command is sent from the CPU 101 (step S4).
1) If it is sent (S42), the data is RAM
Store in 110 and return. If the data command has not been sent (S43), it is determined whether or not a command for turning ON / OFF the high voltage has been sent. If it has not been sent, the process directly returns. If an ON / OFF command is sent (S44), that command is ON or OFF.
If it is OFF, the high voltage OFF data is read from the RAM 110 in S50, and the data is PWM
Is set in the output register of (S51), and the high voltage is turned off.

When the high voltage ON is sent in the judgment of step S44, the high voltage data stored in the RAM 110 is read (S45), the data is set in the PWM output register (S46) and the high voltage is turned on. . Next, in step S47, the A / D conversion value of the signal for monitoring the actual high voltage output is read, and this value and the CPU 10 are read.
The high-voltage data sent from No. 1 is compared (S4
8). When it is determined in step S49 that the difference is larger than the predetermined value, the process proceeds to step S50, the high voltage OFF data is read from the RAM 110, and the data is set in the PWM output register (S5
1) Turn off the high voltage. When it is determined in step S49 that the difference is smaller than the predetermined value, the high voltage output is kept ON and the process returns.

This flow control is performed for each of the primary high voltage, the transfer high voltage, the developing bias, the pre-transfer high voltage, and the separation high voltage.

By the above flow control, the high voltage data sent from the CPU 101 is used as a target value and compared with the A / D conversion output of the signal for monitoring the actual output, so that each high voltage control abnormality is detected and the abnormality is detected. When detected, stop the high pressure or total high pressure.

With the above configuration and control, it is possible to reliably detect a control abnormality of the high voltage output, and to suppress image defects, device failures, etc. to a minimum.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to the flow charts of FIGS. The block configuration is similar to that of the third embodiment, and will be described with reference to FIG.

In the present embodiment, the high voltage data sent from the CPU 101 is used as a target value and is compared with the A / D converted output of the signal for monitoring the actual output to detect each high voltage control abnormality and communicate with the CPU 101. Then, the copying operation is stopped and a message to that effect is displayed on the operation unit.

FIG. 10 is a flow chart showing the high pressure control by the CPU 108. First, it is judged whether or not a high-voltage data command is sent from the CPU 101 (step S61), and if it is sent (step S62), the data is stored in the RAM 110 and the process returns. If the data command is not sent (S63), it is judged whether or not the command for turning on / off the high voltage is sent. If it is not sent, the process directly returns. ON /
If an OFF command is sent (S64), it is judged whether the command is ON or OFF. If it is OFF (S7).
0) read the high voltage OFF data from RAM110,
The data is set in the PWM output register (S7
1) Turn off the high voltage. Then, in step S72, C
A high voltage error bit (5 bits) is set to the PU 101 and transmitted.

When the high voltage ON is sent in the determination of step S64, the high voltage data stored in the RAM 110 is read (S65), the data is set in the PWM output register (S66), and the high voltage is turned on. . Next, in step S67, the A / D conversion value of the signal for monitoring the actual high voltage output is read, and this value and CPU 10
The high-voltage data sent from No. 1 is compared (S6
8).

When it is determined in step S69 that the difference is larger than a predetermined value, the high voltage OFF data is read from the RAM 110 in step S70, and the data is set in the PWM output register in step S71. Turn off. When it is determined in step S69 that the difference is smaller than the predetermined value, the high voltage error bit (5 bits) is cleared and transmitted in (S73), and the process returns with the high voltage output turned on.

This flow is performed for each of the primary high voltage, the transfer high voltage, the developing bias, the pre-transfer high voltage, and the separation high voltage.

FIG. 11 is a control flow chart by the CPU 101 provided in the DC controller 104.

In the copy sequence, it is judged whether the high voltage is turned on or off (S81), and if it is turned off (S81).
86) CP on high voltage ON / OFF command (OFF)
Send to U108. If ON (S82), high pressure O
The N / OFF command (ON) is transmitted to the CPU 108. Next, it is checked whether or not the high voltage error bit sent from the CPU 108 is set (S83), and if it is not an error, the process returns as it is. The error code is displayed (S85).

With the above configuration and control, the high-voltage output can be reliably controlled according to the program, and when an error occurs, the copying operation can be immediately stopped and the like, and image defects and device failures can be suppressed to a minimum.

(Fifth Embodiment) FIG. 12 is a timing chart of high-voltage output, and FIG. 13 is a high-voltage control flowchart of the composite power source. The fifth embodiment will be described with reference to both figures. Since the constituent blocks are the same as those in the third embodiment, the description will be omitted.

As shown in FIG. 12, the high voltage output used in the copying machine is generally turned on and then the desired output voltage (-V
It takes a certain time to reach 1). Therefore, when detecting an abnormality in the high voltage control, assuming that the high voltage ON time is t1 and the abnormality detection timing is t2 as shown in FIG. 12, the abnormality is detected with a delay from the high voltage ON for a period of (t2-t1). There is a need. CPU 10 in this case
FIG. 13 is a flowchart of No. 8.

First, the CPU 1 of the DC controller 104
It is determined whether or not a high-voltage data command is sent from 01 (S81), and if so, the data is stored in the RAM 110 and the process returns. If no data command is sent (S83), turn on high voltage
/ Judge whether the command to turn off is sent,
If it is not sent, it returns as it is. ON / OF
When the F command is sent (S84), it is judged whether the command is ON or OFF, and if it is OFF (S92).
Then, the high voltage OFF data is read from the RAM 110, and the data is set in the PWM output register (S93),
Turn off the high voltage.

When the high voltage ON is sent in the determination of step S84, the high voltage data stored in the RAM 110 is read (S85), the data is set in the PWM output register (S86), and the high voltage is turned on. . Here, an internal timer for measuring a fixed time is set (S8
7) Wait until the time is up (S88). Next, in step S89, the A / D converted value of the signal for monitoring the actual high voltage output is read, and this value is compared with the high voltage data sent from the CPU 101 (S90). When it is determined in step S91 that the difference is larger than a predetermined value, the high voltage OFF data is read from the RAM 110 in step S92, the data is set in the PWM output register in step S93, and the high voltage is turned off. . When it is determined in step S91 that the difference is smaller than the predetermined value, the high voltage output is kept ON and the process returns.

By the above control, the abnormality of the high voltage control can be surely detected and dealt with.

That is, in the third, fourth and fifth embodiments, a microcomputer for controlling the power supply to the load, each high-voltage power supply for image formation, the exposure lamp, and a microcomputer for sequence control. In the copying machine equipped with, the high-voltage control is detected abnormally, the high-voltage output is stopped, and the microcomputer which performs sequence control is notified by communication to stop the copying operation. It is possible to minimize image defects and hardware failures caused by abnormalities. Further, since the fact that the abnormality has occurred is displayed, quick service response can be performed.

(Sixth Embodiment) The block configuration of the sixth embodiment is the same as the block configuration of the third embodiment shown in FIG.
The block configuration and the time chart relating to the high voltage output control are the same as those in the third embodiment shown in FIGS. 7 and 8, and the duplicate description will be omitted.

The operation characteristic of this embodiment will be described with reference to the timing charts of FIGS. 14 and 15 and the flowchart of FIG.

14 and 15 show the monitor signal of each high voltage output, where the vertical axis is voltage and the horizontal axis is time.

This monitor signal is converted into a digital signal by the A / D converters 126 to 130 shown in FIG.
11 is input to the CPU 108. In the examples of FIGS. 14 and 15, the high voltage output is OFF when 5 V is output, and the lower the voltage is, the higher the high voltage output is.

In FIG. 14, 1 is applied to the target value V1 (V).
Noise occurred in the monitor signal on the first copy and an error was detected, but a normal value was detected on the second copy and the error was canceled. On the other hand, in FIG. 15, the monitor signal is V2 (V) in the first copy with respect to the target value V1 (V), and since the difference is large, a high voltage output abnormality is detected and an error flag is set. Further, since the monitor signal was V2 (V) even in the second copy, the high voltage output is stopped and the error code is communicated to the CPU 101.

FIG. 16 is a flow chart showing each high voltage output control of the CPU 108.

First, in step S101, it is determined whether or not a high voltage data command is sent from the CPU 101 of the DC controller 104. If it is sent, the data is stored in the RAM 110 in step S102 and the process returns. If the data command has not been sent, it is determined in step S103 whether or not a command for turning ON / OFF the high voltage has been sent. If it has not been sent, the process directly returns. If the ON / OFF command is sent (S
104) judges whether the command is ON or OFF,
If it is FF (S112), the high voltage OFF data is stored in the RAM.
The data is read from 110, the data is set in the PWM output register (S113), and the high voltage is turned off.

At the determination of step S104, the high voltage is turned on.
Is sent, the high voltage data stored in the RAM 110 is read (S105), the data is set in the PWM output register (S106), and the high voltage is turned on. Next, in step S107, the A / D converted value of the signal for monitoring the actual high voltage output is read, and this value is compared with the high voltage data sent from the CPU 101 (S108). When it is determined in step S109 that the difference is smaller than the predetermined value, the high pressure is normally controlled, and the error flag is reset (S
115). If it is determined that the error flag is large (S110), it is determined whether or not the error flag is set. If not, the error flag is set (S114) and the process returns.

If the error flag is determined in step S110, a high voltage error bit (5 bits) is transmitted to CPU 101, high voltage OFF data is read from RAM 110 in step S112, and the data is set in the PWM output register. (S113), the high voltage is turned off.

The above flow is executed for each of the primary high voltage, the transfer high voltage, the developing bias, the pre-transfer high voltage, and the separation high voltage.

Through the above flow, the CPU 108 makes the CP
The control error of each high voltage is detected by comparing the high voltage data sent from U101 with the target value and the A / D conversion output of the signal for monitoring the actual output, and when the error is detected twice in a row, Stop high or total high pressure.

With the above configuration and control, when the high-voltage power supply is not normally supplied, it is possible to immediately deal with it, and it is possible to suppress image defects, hardware failures, and the like.

(Seventh Embodiment) The block configuration of the seventh embodiment and the blocks and time charts related to high-voltage control are the same as those of the third and sixth embodiments shown in FIGS. 6, 7, and 8. Overlapping description is omitted.

The operation characteristic of this embodiment will be described with reference to the timing charts of FIGS. 17 and 18 and the flowchart of FIG.

In this embodiment, the high-voltage data sent from the CPU 101 of the DC controller 104 is used as a target value, and the A / D conversion output of the signal for monitoring the actual output is compared by the CPU 108 of the composite power source 111 at regular intervals. Each of the high voltage control abnormalities is detected by, and when the abnormalities are detected twice in succession, the high voltage output is turned off by communicating to the CPU 101 by communication.

17 and 18 show the monitor signals of the respective high voltage outputs, where the vertical axis is voltage and the horizontal axis is time.

This signal is converted into a digital signal by the A / D converters 126 to 130 and input to the CPU 108. C
The PU 108 makes a comparison with the target value at regular time intervals T1. In this example, the high voltage output is 0 when 5 V is output.
FF, which indicates that the higher the voltage, the higher the high voltage output.

In FIG. 17, noise is generated in the monitor signal with respect to the target value V1 (V) and an error is detected in the third comparison, but it is normally detected in the fourth comparison and the error is canceled. . On the other hand, in FIG. 18, the target value V
Since the first copy is V2 (V) with respect to 1 (V) and the difference is large, a high-voltage output abnormality is detected in the first comparison,
Set an error flag. In the second comparison, the monitor signal was V2 (V), so the high voltage output was stopped and C
The error code is communicated to the PU 101.

FIG. 19 is a flowchart of the CPU 108.

In step S121, it is determined whether or not a high voltage data command is sent from the CPU 101, and if it is sent (S122), the data is sent to the RAM 110.
Store in and return. If the data command is not sent (S123), it is judged whether or not the command for turning on / off the high voltage is sent. If it is not sent, the process directly returns. When an ON / OFF command is sent (S124), it is determined whether the command is ON or OFF. If it is OFF (S134), the high voltage OFF data is read from the RAM 110, and the data is PWM.
Set to the output register of (S135) and turn off the high voltage
To do.

On the other hand, if the high voltage ON is sent in the judgment of step S124, the high voltage data stored in the RAM 110 is read (S125), and the data is converted into P
Set to the output register of WM (S126)
N Next, set the internal timer (S127),
When the time is up (S128), the A / D conversion value of the signal for monitoring the actual high voltage output is read in step S129, and this value is compared with the high voltage data sent from the CPU 101 (S130). Step S1
If it is determined in step 31 that the difference is smaller than the predetermined value, the high pressure is normally controlled, the error flag is reset (S137), and step S124 is performed.
Return to.

On the other hand, if it is determined in step S131 that the difference is large (S132), it is determined whether or not the error flag is set. If not, the error flag is set (S136), and the process returns to step S124. If the error flag is set in the determination in step S132, the CPU 1
A high voltage error bit (5 bits) is transmitted to 01 (S13
3), the high voltage OFF data is stored in the RAM 1 in step S134.
The data is read from 10, the data is set in the PWM output register (S135), and the high voltage is turned off.

The above flow is executed for each of the primary high voltage, the transfer high voltage, the developing bias, the pre-transfer high voltage, and the separation high voltage.

By the above flow, the CPU 108 makes the CP
The high voltage data sent from U101 is used as the target value and the A / D conversion output of the signal that monitors the actual output is compared at regular intervals to detect each high voltage control abnormality, and the abnormality is detected twice in succession. If so, stop the high pressure or total high pressure.

With the above structure and control, the same effects as those of the sixth embodiment can be exhibited.

(Eighth Embodiment) A block configuration and a high-voltage control block and time chart of the eighth embodiment are shown in FIGS. 6, 7, and 8 in the third embodiment and sixth embodiment.
Since it is similar to the seventh embodiment, duplicated description will be omitted.

Referring to the flowchart of FIG. 20, the eighth embodiment
The characteristic operation of the embodiment will be described.

In the present embodiment, after the high voltage is turned on, data is taken in from the monitor signal several times at regular intervals, and the average value thereof and the high voltage data sent from the CPU 101 of the DC controller 104 are compared by the CPU 108 of the composite power source 111 to obtain a high voltage. The control abnormality of is detected. CPU 10 in this case
FIG. 20 is a flowchart of No. 8.

First, it is judged whether or not a high-voltage data command is sent from the CPU 101 (S141). If it is sent, the data is sent to the RAM1 in step S142.
Store in 10 and return. If the data command is not sent (S143), it is judged whether or not the command for turning on / off the high voltage is sent. If not, the process directly returns. If an ON / OFF command is sent (S144), the command is ON or OF.
If it is OFF, if it is OFF (S152), high pressure OF
F data is read from RAM110 and the data is read as P
Set to the output register of WM (S153)
FF.

In the determination of step S144, the high pressure O
When N is sent, the high voltage data stored in the RAM 110 is read (S145), and the data is PWM.
Is set in the output register of (S146) and the high voltage is turned on. Next, in step S147, the A /
It is determined whether the D value has been stored N times in the RAM 110, and if the storage has not been completed, the internal timer is set (S14).
8) When the time is up (S149), step S1
A / of the signal for monitoring the actual high voltage output at 50
The D conversion value is read and this value is stored in the RAM 110 (S151).

If it is determined in step S147 that the data has been stored, the N pieces of data are averaged (S154), and the average value is compared with the high-voltage data sent from the CPU 101 (S155). When it is determined in step S156 that the difference is smaller than the predetermined value, the high pressure is normally controlled, and the process directly returns. On the other hand, if it is determined to be large, a high voltage error bit (5 bits) is transmitted to the CPU 101 (S157), and step S
At 158, the high voltage OFF data is read from the RAM 110, and the data is set in the PWM output register (S
159), turn off the high pressure.

The above flow is executed for each of the primary high voltage, the transfer high voltage, the developing bias, the pre-transfer high voltage, and the separation high voltage.

Through the above flow, the CPU 108 makes the CP
The voltage data sent from U101 is used as a target value, and the A / D conversion output of the signal for monitoring the actual output is fetched at regular intervals, and the high voltage control abnormality is detected by comparing with its average value. When is detected, the high pressure or the total high pressure is stopped.

With the above configuration and control, the sixth embodiment,
The same effect as the seventh embodiment can be exhibited.

That is, in the sixth embodiment, the seventh embodiment and the eighth embodiment, the microcomputer for controlling the power supply to the load, each high-voltage power supply for image formation, and the exposure lamp, and the microcomputer for performing the sequence control. And a copying apparatus for detecting an abnormality in the high-voltage control,
Even when noise due to high voltage output occurs in the signal around the abnormality detection circuit, normal abnormality detection can be performed.

[0110]

As described above, according to the present invention, there is provided the microprocessor for controlling the series of image forming operations, and the microprocessor equipped with the microprocessor for controlling the electric power supplied to the load. A second control means for controlling and a communication means between the first control means and the second control means are provided, and when the communication abnormality detection means detects an abnormality in communication by the communication means, the load is sent to the load. By performing the control of cutting off the power supply, it is possible to immediately and accurately deal with the detected abnormality, and it is possible to suppress image defects, device failures, etc. as much as possible.

Further, the output abnormality detecting means compares the detection signal obtained by detecting the output value of the high-voltage power to the load with the output target value corresponding to the control signal inputted from the first control means, whereby the output abnormality is detected. Therefore, the detected abnormality can be immediately and accurately dealt with, and image defects, device failures, etc. can be suppressed as much as possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a timing chart of the first embodiment.

FIG. 3 is a communication abnormality detection flowchart of the DC controller according to the first embodiment.

FIG. 4 is a communication abnormality detection flowchart of the composite power source according to the first embodiment.

FIG. 5 is a communication abnormality detection circuit diagram of a second embodiment.

FIG. 6 is a block diagram of a third embodiment.

FIG. 7 is a block diagram of the vicinity of a high voltage output control unit of a third embodiment.

FIG. 8 is a timing chart of the third embodiment.

FIG. 9 is a high-voltage output control flowchart of the third embodiment combined power supply.

FIG. 10 is a high voltage output control flowchart of a composite power supply according to a fourth embodiment.

FIG. 11 is a control flowchart of a DC controller according to a fourth embodiment.

FIG. 12 is a timing chart of high voltage output according to the fifth embodiment.

FIG. 13 is a high voltage output control flowchart of the fifth embodiment combined power source.

FIG. 14 is a timing chart of a high voltage output monitor signal according to the sixth embodiment.

FIG. 15 is a timing chart of a high voltage output monitor signal according to the sixth embodiment.

FIG. 16 is a high voltage output control flowchart of the sixth embodiment combined power source.

FIG. 17 is a timing chart of a high voltage output monitor signal according to the seventh embodiment.

FIG. 18 is a timing chart of a high voltage output monitor signal according to the seventh embodiment.

FIG. 19 is a high voltage output control flowchart of the seventh embodiment combined power source.

FIG. 20 is a high voltage output control flowchart of an eighth embodiment combined power supply.

[Explanation of symbols]

 101 Central Processing Unit (CPU) 104 DC Controller 107 Operating Unit 108 Central Processing Unit (CPU) 111 Complex Power Supply 112 Constant Pressure Power Supply Control Unit 113 High Voltage Power Supply Control Unit 114 Lamp Regulator 115 Halogen Lamp 116 Primary Charger 117 Transfer Charger 118 developing device 119 main switch

Claims (17)

[Claims] 1. A first control means comprising a microprocessor for controlling a series of image forming operations, a second control means comprising a microprocessor for controlling electric power supplied to a load in the apparatus, and the first control means. A communication means between the first control means and the second control means and a communication abnormality detection means for detecting an abnormality in the communication are provided, and when the abnormality in the communication is detected, the control for cutting off the power supply to the load is performed. An image forming apparatus characterized by. 2. The first control means is provided with a communication abnormality detecting means for detecting a communication abnormality, and when the abnormality is detected, the power supply to the load is cut off to control the image forming operation. The image forming apparatus according to claim 1. 3. The second control means includes a communication abnormality detecting means for detecting a communication abnormality, and when the abnormality is detected, the second control means controls to cut off the power supply to the load. Image forming apparatus. 4. The first control means and the second control means are provided with a communication abnormality detecting means for detecting a communication abnormality, and when the abnormality is detected, control is performed to cut off the power supply to the load. The image forming apparatus according to claim 1. 5. An abnormality display means for displaying an abnormality is provided, and when the communication abnormality detection means detects a communication abnormality, the abnormality display means displays the abnormality. An image forming apparatus according to claim 2. 6. A first control means comprising a microprocessor for controlling a series of image forming operations, a second control means comprising a microprocessor for controlling power supplied to a load in the apparatus, and the first control means. An image forming apparatus including a communication unit between the first control unit and the second control unit, wherein the second control unit detects the output value of the high voltage power to the load and the first control unit. It is characterized by having an output abnormality detecting means for detecting an abnormality in the output by comparing it with an output target value corresponding to the input control signal, and performing a control to stop the output of the high voltage power when the abnormality is detected. Image forming apparatus. 7. An abnormality display means for displaying an abnormality, wherein the second control means communicates the abnormality to the first control means when the output abnormality detection means detects the abnormality, and the first control means displays the abnormality. 7. The image forming apparatus according to claim 6, wherein an abnormality is displayed on the means to control the stop of the image forming operation. 8. The second control means has a timer means,
8. The image forming apparatus according to claim 6, wherein the output abnormality detecting unit detects the output abnormality after a predetermined time has elapsed after outputting the high voltage power. 9. The second control means performs the output abnormality detection by the output abnormality detection means for each copy cycle, and when the abnormality is continuously detected, determines the abnormality as the final detection output. 9. The image forming apparatus according to any one of 8 to 8. 10. The second control means performs abnormality detection by the output abnormality detection means every time a designated time elapses during high-voltage output, and when continuous abnormality is detected, determines an abnormality as a final detection output. The image forming apparatus according to claim 6. 11. The second control means performs the abnormality detection by the output abnormality detection means a plurality of times at every elapse of a designated time during high voltage output, and an average value of the plurality of detection signals and a control signal input from the first control means. 9. The image forming apparatus according to claim 6, wherein an output abnormality is detected by comparing the output target values corresponding to. 12. The image forming apparatus according to claim 1, wherein the second control unit controls the primary charging high-voltage power. 13. The image forming apparatus according to claim 1, wherein the second control unit controls the developing high-voltage power. 14. The image forming apparatus according to claim 1, wherein the second control unit controls transfer charging high-voltage power. 15. The image forming apparatus according to claim 1, wherein the second control unit controls pre-transfer charging high-voltage power. 16. The image forming apparatus according to claim 1, wherein the second control unit controls the separated high-voltage power. 17. The image forming apparatus according to claim 1, wherein the second control unit controls the document exposure lamp power.