JP6863073B2 - Control systems, image forming devices, and methods - Google Patents

Description

The present invention relates to control systems, image forming devices, and methods.

Conventionally, an image forming apparatus has a first electronic substrate that controls the whole and a second electronic substrate that controls each part based on an instruction from the first electronic substrate. Communication failures that occur between these masters and slaves are confirmed by error displays and the like, and repairs are performed by service personnel.

In a configuration in which an upper control unit and a plurality of lower control units are connected by an FFC (Flexible Flat Cable) harness, the upper control unit sends a connection state detection signal to each lower control unit through the FFC harness. A technique is disclosed in which a lower control unit transmits a response signal to a detection signal and returns a response signal to each assigned time. In this technique, it is determined whether the connection state with each lower control unit is normal based on whether the upper control unit receives a response signal from each lower control unit within each predetermined time (Patent Document 1). reference).

However, in the conventional technique, if the second electronic board is out of order, the response signal is not returned from the second electronic board to the first electronic board, so that the second electronic board may be out of order. It will be determined that the wire harness connection has failed. In this case, unnecessary repair work such as repair of a part unrelated to the faulty part, that is, replacement of the wire harness is required. Therefore, there is a problem that the repair time and the repair cost are wasted until the actual repair of the failed part is performed.

The present invention has been made in view of the above, and an object of the present invention is to provide a control system, an image forming apparatus, and a method capable of isolating a faulty part.

In order to solve the above-mentioned problems and achieve the object, the control system of one embodiment of the present invention includes a first electronic board on which a processor is mounted, an IC as a communication partner of the processor, the IC, and the processor. the second electronic board having a switching circuit for disconnecting the electrical connection, and a control line for transmitting control signals from said processor to said switching circuit, the electrical connection state by the selector switch and a plurality of communication lines and the processor and the IC communicate, against the front of the plurality of the communication lines of said selector switch from said processor is disposed on the second electronic substrate, delaying each by the delay circuit phase A wire harness that includes a failure diagnosis signal line for inputting a failure diagnosis signal to be input, a plurality of the communication lines, and the failure diagnosis signal line, and connects the first electronic board and the second electronic board. has, the processor, and determines the malfunction determining unit for fault location, have a, and an output unit for outputting a determination result of the fault location according to the failure determination section, the processor is in the switch circuit It is characterized in that a failure location is determined from a plurality of input signals of the communication lines detected by outputting a control signal and outputting high, low, and clock signals to the failure diagnosis signal line, respectively.

According to the present invention, there is an effect that the faulty part can be isolated.

FIG. 1 is a diagram showing an example of an image forming apparatus according to the first embodiment. FIG. 2 is a diagram showing an example of a main configuration of a control system. FIG. 3 is a diagram showing an example of the input / output configuration of the IC. FIG. 4 is a diagram showing an example of the configuration of the connection circuit. FIG. 5 is a diagram showing an example of the configuration of the functional block. FIG. 6 is a diagram showing an example of a failure detection processing flow. FIG. 7 is a diagram showing a continuation of the failure detection processing flow. FIG. 8 is a diagram showing a continuation of the failure detection processing flow. FIG. 9 is a diagram showing an input / output example (No. 1) of a signal during the failure detection process. FIG. 10 is a diagram showing an input / output example (No. 2) of a signal during the failure detection process. FIG. 11 is a diagram showing an input / output example (No. 3) of a signal during the failure detection process. FIG. 12 is a diagram for explaining a change in the Low width. FIG. 13 is a diagram showing an example of the function continuous processing flow. FIG. 14 is a diagram showing another example of the function continuous processing flow.

Embodiments of the control system, the image forming apparatus, and the method will be described in detail below with reference to the accompanying drawings.

(First Embodiment)
FIG. 1 is a diagram showing an example of an image forming apparatus according to the first embodiment. FIG. 1 shows a multifunction device as an example of an image forming apparatus.

The multifunction device 1 shown in FIG. 1 includes an image reading unit (scanner) 10, a recording paper supply unit 20, and an image forming unit (plotter) 30. These are shown in a state where the outer cover is removed and the internal configuration is exposed in order to make the configuration easy to understand.

The multifunction device 1 is provided with an operation panel on the upper part of the housing. The operation panel is, for example, a display input device in which a touch panel is arranged on a liquid crystal display. In addition to the touch panel, the operation panel may be provided with an operation hardware key or the like. The operation panel functions as a user interface that displays operation information and receives operation instructions by the user.

The image reading unit 10 includes a scanner 10a that houses a lighting device, an optical system, a CCD (Charge Coupled Device), and the like. The scanner 10a has a contact glass 11 for arranging the document on the upper surface, illuminates the document through the contact glass 11, and reads the reflected light by an internal CCD through an optical system. An ADF (Auto Document Feeder) 10b is provided above the scanner 10a. The ADF10b automatically conveys the original and sends the original to the reading surface of the contact glass 11.

The image forming unit 30 has a recording paper supply unit 20 at the bottom. The recording paper supply unit 20 feeds the recording paper, which is a recording body, from the recording paper paper feed cassettes 21 and 22 arranged in multiple stages to the image forming unit 30.

The image forming unit 30 includes an optical writing device 31, a tandem type image forming unit 32Y, 32M, 32C, 32K, an intermediate transfer belt 35, a fixing device 37, and the like, from the lower recording paper supply unit 20. An image is formed on the supplied recording paper with toner or the like.

Specifically, the image-forming units 32Y, 32M, 32C, and 32K have four photoconductor drums 33 of yellow (Y), magenta (M), cyan (C), and black (K), respectively. It is provided side by side so as to be rotatable clockwise, and an image forming element including a charging roller, a developing device, a primary transfer roller 34, a cleaner unit, and a static eliminator is provided around each photoconductor drum 33.

The intermediate transfer belt 35 is arranged on the nip between each photoconductor drum 33 and each primary transfer roller 34 by being stretched by a driving roller and a driven roller.

The image forming unit 30 having this configuration charges the surface of each photoconductor drum 33 with a charger, and irradiates, for example, laser light from the optical writing device 31 toward the surface of each charged photoconductor drum 33. By irradiating the laser beam, an electrostatic latent image is formed on the surface of each photoconductor drum 33. Subsequently, the image forming unit 30 supplies the toner of the corresponding color from the developing device toward each photoconductor drum 33 to develop the electrostatic latent image.

Further, the image forming unit 30 primary transfers the developed toner images of each color on the surface of each photoconductor drum 33 to the intermediate transfer belt 35 traveling clockwise in the figure by the primary transfer roller 34. Subsequently, the image forming unit 30 secondarily transfers the primary transferred toner image on the intermediate transfer belt 35 to the recording paper conveyed to the position by the secondary transfer device 36. After that, the image forming unit 30 conveys the recording paper on which the toner image is transferred to the fixing device 37, fixes the toner image of each color on the recording paper as a color image by pressurization or the like in the fixing device 37, and turns the fan. After drying, it is discharged to the output tray outside the machine.

Subsequently, a "control system" for controlling the multifunction device 1 will be described. The control system includes a control board (first electronic board) that controls the overall control of the multifunction device 1 and each control board (second electronic board) such as the image reading unit 10 and the image forming unit 30. The first electronic board and each second electronic board are connected by a wire harness. Here, the "wire harness" is a general term for a group of electric wires having two or more electric wires for transmitting a signal between the first electronic board and the second electronic board.

Each electronic board is housed in a predetermined storage area. For example, they may be collectively stored in one place provided inside the housing of the multifunction device 1, or may be distributed and stored in a plurality of places provided inside the housing of the multifunction device 1.

FIG. 2 is a diagram showing an example of a main configuration of the control system. As shown in FIG. 2, the control system 100 includes a first electronic board 110 and two second electronic boards 120. The first electronic board 110 and the two second electronic boards 120 (120-1, 120-2) are operated by electric power supplied from an AC power source, a battery, or the like via a power supply circuit.

The first electronic board 110 and the two second electronic boards 120 are electrically connected to each other via an FFC (Flexible Flat Cable) 130. FFC is an example of a "wire harness".

The first electronic board 110 includes a CPU (Central Processing Unit) 111, a ROM (Read Only Memory) 112, a RAM (Random Access Memory) 113, and the like. The CPU 111 is an example of a “processor”, and executes a control program to control the entire multifunction device 1 in an integrated manner. The ROM 112 stores the control program. The RAM 113 is used as a work area by the CPU 111.

Each of the two second electronic substrates 120 includes an IC (Integrated Circuit) 121, for example, an ASIC (Application Specific Integrated Circuit) or the like. The CPU 111 and each IC 121 have a master-slave relationship. Each IC 121 is a communication partner of the CPU 111 of the first electronic board 110, and controls a control target based on a signal output from the CPU 111. In the present embodiment, of the two second electronic boards 120, the IC121-1 of the second electronic board 120-1 controls the image reading unit 10 and the IC121- of the second electronic board 120-2. 2 controls the image forming unit 30 (including the recording paper supply unit 20).

FIG. 3 is a diagram showing an example of the input / output configuration of the IC 121. Here, an example of the input / output configuration of IC121-2 that controls the image forming unit 30 (including the recording paper supply unit 20) is shown.

As shown in FIG. 3, the IC121-2 has input ports In1, In2, ... For inputting a control signal from the CPU 111. The control signal is a signal that turns on or off the control target of the image forming unit 30 (including the recording paper supply unit 20), a signal that indicates data to be set in the control target, and the like. The input port includes an input port for inputting a control signal for the optical writing device 31, an input port for inputting a control signal for the image forming units 32Y, 32M, 32C, and 32K, and a control signal for the fixing device 37. An input port for inputting a control signal for a fan 38, an input port for inputting a control signal for a fan 38, an input port for inputting a control signal for a drive motor 39 for various rollers, and the like are included.

Further, the IC121-2 is a control signal for a control target such as an optical writing device 31, an image forming unit 32Y, 32M, 32C, 32K, a fixing device 37, a fan 38, and a drive motor 39 for various rollers. It has output ports Out1, Out2, ...

Subsequently, the configuration of the connection circuit for connecting the CPU 111 of the first electronic board 110 and the IC 121 of the second electronic board 120 will be described. The IC121-1 of the second electronic board 120-1 and the IC121-2 of the second electronic board 120-2 both follow the configuration of the connection circuit shown below.

FIG. 4 is a diagram showing an example of a configuration of a connection circuit for connecting the CPU 111 of the first electronic board 110 and the IC 121 of the second electronic board 120. In FIG. 4, illustrations other than the main components of the connection circuit (ROM 112, RAM 113, etc.) are omitted. The configuration of the connection circuit shown in FIG. 4 will be described in the order of the configuration of the first electronic board 110, the FFC 130, and the second electronic board 120.

On the first electronic board 110, a communication line A1 used for communication with the IC 121 and a signal line A2 for failure diagnosis are wired between the CPU 111 and the connector 115. Here, four communication lines A1 are shown, but this is to make the explanation easier to understand. The number of communication lines A1 may be increased or decreased as appropriate according to the input / output configuration of the IC121-1 or IC121-2 to be communicated.

Each communication line A1 is assigned input / output ports P21, P22, P23, and P24 to predetermined input / output pins of the CPU 111, and each input / output pin and a predetermined connection pin of the connector 115 are wired one-to-one with an electric wire. It is a thing. A pull-up resistor r1 is connected to each electric wire for pull-up connection.

In the signal line A2, one of the input / output pins of the CPU 111 is assigned to the input / output port P11 for failure diagnosis, and the input / output pin and a predetermined connection pin (connection pin assigned for failure diagnosis) in the pin arrangement of the connector 115 are assigned. ) And one-to-one with an electric wire.

The FFC 130 connects the fitting portions (connection portions) at both ends of the FFC 130 to the connector 115 of the first electronic board 110 and the connector 125 of the second electronic board 120, respectively, thereby connecting the first electronic board 110 and the first electronic board 110. The electronic substrate 120 of 2 is electrically connected. The FFC 130 has an electric wire B1 as a communication line and an electric wire B2 as a signal line. The electric wire B1 is electrically connected to the communication line A1 on the first electronic board 110 side, and the electric wire B2 is electrically connected to the signal line A2 on the first electronic board 110 side.

The second electronic board 120 is provided with a switch circuit 122 and a delay circuit 123. The switch circuit 122 is an electronic switch that switches the electrical state of the IC 121 and the CPU 111 to either the connected state or the disconnected state. The switch circuit 122 switches to either a connected state or a disconnected state according to a high level or low level switching signal input from the input terminal E1. Specifically, the switch circuit 122 switches to connection when a High level signal is input to the input terminal E1, and switches to disconnection when a Low level signal is input.

The delay circuit 123 outputs the failure diagnosis signal output by the CPU 111 with the phase shifted toward the input / output pins for each communication of the CPU 111. Specifically, the delay circuit 123 includes four delay blocks 123-1, 123-2, 123-3, and 123-4 having different delay times. Each delay block 123-1, 123-2, 123-3, 123-4 delays each delay diagnosis signal simultaneously input to each delay block 123-1, 123-2, 123-3, 123-4. Delay blocks 123-1, 123-2, 123-3 toward the respective predetermined communication line A1 connected to the output side of blocks 123-1, 123-2, 123-3, 123-4. , 123-4 is output with a different delay time.

As shown in FIG. 4, the delay circuit 123 connects the delay blocks 123-1, 123-2, 123-3, and 123-4 to the connection pins for failure diagnosis in the pin arrangement of the connector 125. Connect in parallel by C2). The output lines C21, C22, C23, and C24 of the delay blocks 123-1, 123-2, 123-3, and 123-4 are wired or connected to the respective electric wires of the communication line C1.

A communication line C1 is wired between the connector 125 and the IC 121 via a switch circuit 122. Each of the four lines of the communication line C1 is an electric wire, and is electrically connected to each line of the communication line A1 of the input / output ports P21, P22, P23, and P24 via the FFC 130. On the IC121 side, a predetermined input / output pin and each line of the communication line C1 are connected.

In the present embodiment, the CPU 111 and the switch circuit 122 are further wired by the control line A3. Specifically, one of the output pins of the CPU 111 is assigned as an output port P31 for controlling the switch circuit 122, and the output pin and the input terminal E1 of the switch circuit 122 are wired by an electric wire (control line A3). A pull-up resistor r2 is connected to the control line A3. Further, in the second electronic board 120, the signal line C2 is wired or connected to the control line A3.

In the present embodiment, the communication line A1, the electric wire B1, and the communication line C1 mainly correspond to the "communication line". Mainly, the signal line A2, the electric wire B2, the signal line C2, and the output lines C21 to C24 correspond to the "fault diagnosis signal line".

Next, the function of isolating the failure and the procedure for isolating the failure will be described. Here, an example of a case where the CPU 111 isolates a failure by executing a predetermined program will be shown.

FIG. 5 is a diagram showing an example of a configuration of a functional block realized by the CPU 111 executing a program. FIG. 5 mainly shows the functional unit related to the isolation of the failure. As shown in FIG. 5, the CPU 111 includes a service call unit 300 and a failure detection unit 400 that isolates failures.

The service call unit 300 issues a predetermined service call. For example, when the service call unit 300 receives an interrupt signal notifying that there is an abnormality in communication with the IC 121, the service call unit 300 issues a service call for processing to detect the faulty part.

The failure detection unit 400 includes a mode switching unit 401, a first signal output unit 402, a second signal output unit 403, a signal reading unit 404, a failure determination unit 405, a notification unit 406, and a flag area operation. It has a part 407 and.

The mode switching unit 401 switches the mode. For example, the mode is switched to a mode in which a predetermined restriction is released so that control for identifying a faulty part can be performed.

The first signal output unit 402 sets the signal level (High or Low) of the output signal, and outputs the output signal from the output port P31.

The second signal output unit 403 switches the input / output port P11 to output, sets the signal level (High or Low) of the output signal or the repetitive pattern signal (clock signal, etc.), and sets the output signal to the input / output port P11. Output from.

The signal reading unit 404 appropriately switches the input / output ports P11 and P21 to P24 to input, and reads the input signal (signal level and the like) from the input / output ports P11 and P21 to P24 for a predetermined time.

The failure determination unit 405 determines the failure location by comparing the read value of the signal level read by the signal reading unit 404 with a predetermined threshold value.

The notification unit 406 notifies the operation panel of the result information indicating the failure location. The flag area operation unit 407 provides a flag area indicating a failure location in a register or the like, and sets a flag value (a value “1” indicating a failure or a value “0” indicating normality) in the flag area. In the present embodiment, the "open failure flag", "GND (sheet metal, etc.) short failure flag", "failure flag of the second electronic board 120", and "short failure between wires" are used in units of the second electronic board 120. A setting area for "flag" is provided. The types of these failure flags are examples, and only a part of them may be provided, or other types of failure flags may be provided.

In the present embodiment, the operation panel or the like mainly corresponds to the “display unit”. Further, mainly, the flag area of the register and the like correspond to the "storage unit", and the flag area operation unit 407 and the like correspond to the "reading unit". The “output unit” includes, for example, a notification unit 406 and an operation panel, and outputs a determination result of a failure location to the operation panel based on the notification of the notification unit 406. Further, the "output unit" includes the "storage unit" and the "reading unit", stores the determination result in the "storage unit", and the "reading unit" outputs the determination result of the "storage unit". The “output unit” may have another configuration as long as it can output the determination result of the faulty part.

6 to 8 are diagrams showing an example of a failure detection processing flow showing a procedure for isolating a failure. 9 to 12 are diagrams showing an example of signal input / output in the CPU 111 during the failure detection process. The processing flow of FIGS. 6 to 8 will be described with reference to FIGS. 9 to 12 as appropriate.

First, the service call unit 300 determines whether or not a communication abnormality has occurred (S1). For example, the service call unit 300 receives an interrupt signal indicating a communication failure between the CPU 111 and the IC 121 when or after the multifunction device 1 is started. Then, when the service call unit 300 receives the interrupt signal, it determines that a communication abnormality has occurred (S1: Yes determination). In the Yes determination in step S1, the service call unit 300 issues a service call for processing to detect the failure location, and in response to this, the failure detection unit 400 performs the failure detection process as follows.

First, the mode switching unit 401 switches the processing mode being processed to the failure detection mode (S2). The failure detection mode is, for example, an administrator mode in which a predetermined user restriction is released.

Subsequently, in a state where the first signal output unit 402 outputs a high level signal (high level switch control signal) from the output port P31 (S3), the signal reading unit 404 sends the signal reading unit 404 to the input / output port P11 at that time. The signal level of the input signal (fault diagnosis signal) is read (S4). FIG. 9 shows an input / output example of the signal at that time. As shown in FIG. 9, a high level signal L1 connecting the switch circuit 122 is output from the output port P31 to the switch circuit 122. In this state, the signal reading unit 404 reads the signal level of the signal L11 that loops back from the output port P31 to the input / output port P11.

Subsequently, the failure determination unit 405 compares the signal level read by the signal reading unit 404 with a predetermined threshold value, and determines whether the signal level is High (S5).

When the signal level is not High, that is, when it is lower than a predetermined threshold value (S5: No determination), the failure determination unit 405 determines that the FFC 130 has failed (S6), and the notification unit 406 instructs the replacement of the FFC 130. Is notified (S7).

When the high level signal L1 does not return to the input / output port P11 in this way, it is considered that the FFC 130 connecting the first electronic board 110 and the second electronic board 120 has failed, and the notification unit 406 replaces the FFC 130. Notify the information to be instructed. By this notification, the notification information indicating the failure location is displayed on the screen of the operation panel.

In this way, the failure detection unit 400 isolates the FFC 130 as a failure location when the determination in step S5 is No.

On the other hand, when the signal level is High (S5: Yes determination), that is, when the High level signal L1 returns to the input / output port P11, it cannot be separated. In this case, the separation is performed according to the following procedure.

First, the first signal output unit 402 outputs a Low level signal (Low level switch control signal) from the output port P31 (S8). That is, the low level signal is input to the switch circuit 122 to electrically disconnect the IC 121 from the circuit including the CPU 111 and the FFC 130.

Subsequently, the second signal output unit 403 outputs a Low level signal (Low level failure diagnosis signal) from the input / output port P11 (S9), and the signal reading unit 404 outputs the input / output ports P21, P22, P23 at that time. , Read the signal level of the signal input to P24 (S10). FIG. 10 shows an example of input / output of a signal after the switch circuit 122 is disconnected. As shown in FIG. 10, the Low level signal L2 is output from the input / output port P11, and the signal reading unit 404 inputs the signals L21, L22, L23, and L24 to the input / output ports P21, P22, P23, and P24. Load the level.

Subsequently, the failure determination unit 405 determines whether each signal level of the signals L21, L22, L23, and L24 is Low by comparing with the threshold value (S11).

When there is a signal level that is not Low (S11: No determination), the input / output port from which the non-Low signal is read is determined to be an open failure (S12), and the setting area of the "open failure flag" in the flag area is set. Set "1" (S13).

Then, the notification unit 406 notifies the information instructing the replacement of the FFC 130 (S14).

When all the signal levels of the signals L21, L22, L23, and L24 are Low (S11: Yes determination), the second signal output unit 403 outputs a High level signal (High level failure diagnosis signal) from the input / output port P11. The signal is output (S15), and the signal reading unit 404 reads the signal level of the signal input to the input / output ports P21, P22, P23, and P24 at that time (S16). FIG. 11 shows an input / output example of the signal at that time. As shown in FIG. 11, the high level signal L3 is output from the input / output port P11, and the signal reading unit 404 inputs the signals L31, L32, L33, and L34 to the input / output ports P21, P22, P23, and P24. Load the level.

Subsequently, the failure determination unit 405 determines whether each signal level of the signals L31, L32, L33, and L34 is High by comparing with the threshold value (S17).

When there is a non-High signal level (S17: No determination), the input / output port from which the non-High signal is read is determined to be a GND short failure (S18), and the "GND short failure flag" in the flag area is set. “1” is set in the area (S19).

Then, the notification unit 406 notifies the information instructing the replacement of the FFC 130 (S20).

When all the signal levels of the signals L31, L32, L33, and L34 are High (S17: Yes determination), the second signal output unit 403 outputs a repetitive pattern signal from the input / output port P11 (S21), and signals. The reading unit 404 reads the input signals of the input / output ports P21, P22, P23, and P24 at that time (S22). Here, as an example, it is assumed that a clock signal (clock waveform failure diagnosis signal) is output as a repetitive pattern signal and the Low level width (Low width) of the signal waveform is read.

FIG. 12 is a diagram for explaining a change in the Low width. FIG. 12A shows the Low width in the normal state, and FIG. 12B shows the Low width when a short circuit occurs between the communication lines of the FFC 130.

Assuming that a clock signal having a Low width of t (ms) is output from the input / output port P11, under normal conditions, as shown in FIG. 12A, each of the input / output ports P21, P22, P23, and P24 The width of the Low level of the input waveform becomes the same. On the other hand, for example, when a short circuit occurs between the input / output port P21 and the input / output port P22, as shown in FIG. 12B, the input waveforms of the input / output port P21 and the input / output port P22 are different. It becomes a composite waveform of the input waveform of the input / output port P21 and the input waveform of the input / output port P22 slightly delayed from it, and the Low level of each input waveform (composite input waveform) of the input / output port P21 and the input / output port P22. The width is larger than that of the normal input / output ports P23 and P24.

Following step S22, the failure determination unit 405 compares the Low width with the threshold value t + β (ms) for each input signal, and determines whether the Low width is equal to or greater than the threshold value t + β (ms) (S23). Note that β is a positive value that satisfies β <α.

When all of the input signals have a Low width of less than the threshold value t + β (ms) (S23: No determination), it is determined that the second electronic board 120 (IC121) has failed (S24), and the “second second” in the flag area. “1” is set in the setting area of the “failure flag of the electronic board 120” (S25).

Then, the notification unit 406 notifies the information instructing the replacement of the second electronic board 120 (S26).

When there is an input signal whose Low width is equal to or greater than the threshold value t + β (ms) (S23: Yes determination), it is determined that the lines are short-circuited in the communication line A1 (S27), and the “line-to-line short circuit” in the flag area is determined. “1” is set in the setting area of the “failure flag” (S28).

Then, the notification unit 406 notifies the information instructing the replacement of the FFC 130 (S29).

In this way, the failure detection unit 400 isolates the failure between the FFC 130 and the second electronic board 120.

The serviceman identifies the faulty part from the notification information screen displayed on the operation panel, and replaces the parts of that part. If the serviceman is absent at that time, the flag area operation unit 407 is made to read each set value of the flag area by operating the operation panel after the serviceman arrives. The serviceman confirms each set value read by the flag area operation unit 407 on the operation screen or the like, and identifies the faulty part.

If all the functions of the multifunction device 1 are stopped until the arrival of the serviceman when the serviceman is absent, the work is interrupted until the multifunction device 1 is restored, and the workability and productivity are lowered. Therefore, it is preferable that the multifunction device 1 can be continuously used without stopping, except for the portion specified as a failure. Such a sustainable control method is shown below.

The control system 100 of the composite machine 1 shown as an example in the present embodiment includes a second electronic board (referred to as “reading board” or “scan control board”) 120-1 for controlling the image reading unit 10 and an image forming unit. A second electronic substrate (referred to as an "image forming substrate" or a "plotter control substrate") 120-2 for controlling 30 is provided. The second electronic substrate 120-1 has a function of generating image data of a document (so-called scanning function), and the second electronic substrate 120-2 has a function of forming an image on a recording paper. Therefore, even if one of the second electronic boards 120 (120-1, 120-2) fails, the non-failed electronic board is operated normally and the functions possessed by the failure are continued to be used. It is possible.

FIG. 13 is a diagram showing an example of a function sustaining processing flow that sustains the function of the other when one of the two second electronic substrates 120-1 and 120-2 fails. First, the mode switching unit 401 determines whether the failure detection process is completed (S51).

When the failure detection process is completed (S51: Yes determination), the mode switching unit 401 determines whether there is a failure with the image forming substrate 120-2 (S52). Specifically, the mode switching unit 401 forms an image from the processing results (set values of the flag area) of the failure detection processing flow of FIGS. 6 to 8 for each of the reading board 120-1 and the image forming board 120-2. It is determined whether there is a failure with the substrate 120-2. For example, when the mode switching unit 401 reads the failure of the wiring between the image forming board 120-2 and the image forming board 120-2 from the set value of the flag area, the failure with the image forming board 120-2 is found. It is determined that there is (S52: Yes determination).

When the mode switching unit 401 determines that there is a failure with the image forming substrate 120-2 (S52: Yes determination), it further determines whether there is a failure with the reading substrate 120-1 (S53). .. Here, when the mode switching unit 401 determines from the set value of the flag area that there is a failure between the reading board 120-1 (S53: Yes determination), the reading board 120-1 and the image forming board 120-2 (S54), and shifts to the function stop mode for stopping the scanner operation and the plotter operation of the multifunction device 1 (S55). When it is determined in step S53 that there is no failure with the reading board 120-1 (S53: No determination), the mode switching unit 401 shifts to the scanner operable mode in which the plotter operation is stopped and the scanner operation is enabled. (S56).

On the other hand, when it is determined in step S52 that there is no failure with the image forming substrate 120-2 (S52: No determination), does the mode switching unit 401 subsequently have a failure with the reading substrate 120-1? Is determined (S57). Here, when the mode switching unit 401 determines that there is a failure with the reading board 120-1 (S57: Yes determination), the mode switching unit 401 stops the scanner operation and shifts to the plotter operable mode that enables the plotter operation (S57: Yes determination). S58).

When it is determined that there is no failure between the image forming substrate 120-2 and the reading substrate 120-1 (S57: No determination), the mode switching unit 401 sets the image between the reading substrate 120-1 and the image. It is determined that there is a failure in a place other than the forming substrate 120-2 (S59), and the process shifts to the machine stop mode of the multifunction device 1 (S60).

In the configuration example of the multifunction device 1 shown in the present embodiment, even if a part of the wires of the FFC 130 is broken, the second electronic substrate to which the wires are connected according to the faulty wire is connected. It may be possible to continue to use the 120 functions. Therefore, in order to maintain the function in the event of a failure, a flag area is provided in the flag area to specifically indicate the location of the failure and the content of the failure, such as an open failure of a fan control signal. In addition, the corresponding data in which the failure and the setting of the avoidance pattern for sustaining the function are associated with each other are stored together with the program. For example, the setting of the avoidance pattern that sustains the function when the fan control signal is an open failure is associated. In the following, the function sustaining process will be described as an example of an avoidance pattern that sustains the function when the fan control signal is an open failure.

FIG. 14 is a diagram showing an example of a function continuation processing flow for sustaining the function of the second electronic substrate 120 in which a failure occurs in a part of the lines of the FFC 130.

First, the mode switching unit 401 determines whether the failure detection process is completed (S71).

When the failure detection process is completed (S71: Yes determination), the mode switching unit 401 confirms the setting state of the flag area indicating the failure location (S72). Specifically, the mode switching unit 401 acquires the set value of the flag area from the flag area operation unit 407 and confirms the set state of the flag area.

Subsequently, the mode switching unit 401 determines whether the fan control signal is an open failure (S73). Specifically, the mode switching unit 401 determines whether the fan control signal is an open failure in the set value acquired from the flag area.

When the fan control signal has an open failure (S73: Yes determination), the mode switching unit 401 performs the next avoidance process based on the avoidance pattern when the fan control signal has an open failure.

First, the mode switching unit 401 determines whether the control signal (fixing control signal) for the fixing device 37 is normal (S74). Specifically, the mode switching unit 401 determines from the flag area whether the fixing control signal is normal. Subsequently, when the fixing control signal is normal (S74: Yes determination), the mode switching unit 401 shifts to the plotter intermittent operation mode (S75). The plotter intermittent operation mode is an operation in which the operation until the recording paper after image formation is discharged to the discharge port is performed with a time interval of the drying time of natural drying between the front and rear recording papers.

As described above, when the failure content is an open failure of the fan control signal, the function can be maintained in the plotter intermittent operation mode if the fixing control signal is normal. By setting this condition as the corresponding data or the like as an avoidance pattern corresponding to the open failure of the fan control signal, the mode switching unit 401 executes the avoidance process according to the setting.

On the other hand, when the fixing control signal is not normal (S74: No determination), the mode switching unit 401 determines that the fixing is abnormal (the conditions of the avoidance pattern do not match) (S76), and stops the plotter operation of the multifunction device 1 as per the basics. (S77).

If the fan control signal is not an open failure (S73: No determination), the mode switching unit 401 determines that a part other than the fan control signal is out of order (S78), and describes the details of the failure in other failure points. Avoidance processing (processing of avoidance patterns set in corresponding data and the like) is performed (S79).

In the present embodiment, an example in which two second electronic boards serving as communication partners of the first electronic board are provided has been shown, but it is possible to carry out a process of isolating the faulty part with one or three or more. It is possible.

In the present embodiment, the delay circuit 123 is provided to detect a short circuit between one line and another line, but when the short circuit between one line and another line is not detected, the delay circuit 123 is excluded. You may.

In the present embodiment, an example of the control system mounted on the image forming apparatus is shown, but the control system may be applied to an apparatus other than the image forming apparatus. When applied to other devices, the first electronic board is incorporated as a control board for the entire application device, and the second electronic board is incorporated as a control board for each unit to be controlled included in the application device.

The multifunction device shown as an example in the present embodiment can be applied to a multifunction device having at least two functions of a copy function, a printer function, a scanner function, and a facsimile function.

As described above, by applying the control system of the present embodiment, it is possible to isolate the faulty part.

110 1st electronic board 111 CPU
115 Connector 120 Second Electronic Board 121 IC
122 Switch circuit 123 Delay circuit 125 Connector 130 FFC
300 Service call unit 400 Failure detection unit 401 Mode switching unit 402 First signal output unit 403 Second signal output unit 404 Signal reading unit 405 Failure judgment unit 406 Notification unit 407 Flag area operation unit A1 Communication line A2 Signal line A3 Control Wire B1 Wire B2 Wire C1 Communication line C2 Signal line E1 Input terminal P11 Input / output port P21, P22, P23, P24 Input / output port P31 Output port r1 Pull-up resistor r2 Pull-up resistor

Japanese Unexamined Patent Publication No. 2013-234992

Claims (12)

The first electronic board with the processor and
A second electronic board on which an IC to be a communication partner of the processor and a switch circuit for disconnecting the electrical connection state between the IC and the processor are mounted.
A control line that transmits a control signal from the processor to the switch circuit,
A plurality of communication lines through which the processor and the IC communicate in an electrically connected state by the switch circuit, and
A failure diagnosis signal line for inputting a failure diagnosis signal input by a delay circuit with a phase delayed from each of the plurality of communication lines in the previous stage of the switch circuit arranged on the second electronic board from the processor.
A wire harness that includes a plurality of the communication lines and the failure diagnosis signal line and connects the first electronic board and the second electronic board.
Have,
The processor
A failure judgment unit that determines the location of a failure,
An output unit that outputs the determination result of the failure location by the failure determination unit, and an output unit that outputs the determination result of the failure location.
Have,
The processor determines a failure location from a plurality of input signals of the communication line detected by outputting a control signal to the switch circuit and outputting high, low, and clock signals to the failure diagnosis signal line, respectively. ,
A control system characterized by that. The failure diagnosis signal line is wired or connected to the communication line on the second electronic board.
The control system according to claim 1. The processor outputs a Low level signal or a High level signal as the failure diagnosis signal, and outputs the Low level signal or the High level signal.
When the communication line is pulled-up connected to the processor, the failure determination unit may perform a pull-up connection.
Based on the output of the Low level signal, it is determined whether or not the failure is open, and the failure is determined.
Based on the output of the High level signal, it is determined whether or not there is a GND short failure.
The control system according to claim 1 or 2. The processor outputs a clock signal as the failure diagnosis signal, and determines whether or not there is a short-circuit failure between communication lines based on the input signal waveform of the clock signal.
The control system according to any one of claims 1 to 3, wherein the control system is characterized in that. The processor reads the input level of the failure diagnosis signal line during the period of outputting the control signal for switching the switch circuit to the connected state to the control line.
A control signal for switching the switch circuit to the disconnected state is output to the control line according to the read input level.
The control system according to any one of claims 1 to 4. The output unit
A notification unit that notifies the determination result of the failure location by the failure determination unit, and a notification unit.
A display unit that displays the determination result by notification from the notification unit, and
Have,
The control system according to any one of claims 1 to 5, wherein the control system is characterized in that. The output unit
A storage unit that stores the determination result of the failure location by the failure determination unit, and a storage unit.
A reading unit that reads out the determination result stored in the storage unit,
Have,
The control system according to any one of claims 1 to 5, wherein the control system is characterized in that. The first electronic board with the processor and
A second electronic board on which an IC to be a communication partner of the processor and a switch circuit for disconnecting the electrical connection state between the IC and the processor are mounted.
A control line that transmits a control signal from the processor to the switch circuit,
A plurality of communication lines through which the processor and the IC communicate in an electrically connected state by the switch circuit, and
A failure diagnosis signal line for inputting a failure diagnosis signal input by a delay circuit with a phase delayed from each of the plurality of communication lines in the previous stage of the switch circuit arranged on the second electronic board from the processor.
A wire harness that includes a plurality of the communication lines and the failure diagnosis signal line and connects the first electronic board and the second electronic board.
Have,
The processor
A failure judgment unit that determines the location of a failure,
An output unit that outputs the determination result of the failure location by the failure determination unit, and an output unit that outputs the determination result of the failure location.
Have,
The processor determines a failure location from a plurality of input signals of the communication line detected by outputting a control signal to the switch circuit and outputting high, low, and clock signals to the failure diagnosis signal line, respectively. ,
An image forming apparatus characterized in that. In addition
It has a mode switching unit that maintains a function that can operate according to the determination result of the failure location by the failure determination unit.
The image forming apparatus according to claim 8. As the second electronic board, at least two types of a scanner control board for controlling a scanner and a plotter control board for controlling a plotter are provided.
The processor outputs a control signal to the control line to switch the switch circuit of the scanner control board and the plotter control board to the disconnected state.
The processor outputs the failure diagnosis signal to the failure diagnosis signal line, and outputs the failure diagnosis signal.
The processor reads the failure diagnosis signal output to the failure diagnosis signal line from the communication line corresponding to each of the scanner control board and the plotter control board.
The failure determination unit determines the failure location based on the read failure diagnosis signal, and determines the failure location.
When there is a failure in either the scanner control board or the plotter control board, the mode switching unit continues the operation of the scanner control board and the plotter control board in which there is no failure. ,
The image forming apparatus according to claim 9. When there is a failure between the scanner control board and the plotter control board, the mode switching unit continues the operation possible for the person with the failure.
The image forming apparatus according to claim 10. The first electronic board with the processor and
A second electronic board on which an IC to be a communication partner of the processor and a switch circuit for disconnecting the electrical connection state between the IC and the processor are mounted.
A control line that transmits a control signal from the processor to the switch circuit,
A plurality of communication lines through which the processor and the IC communicate in an electrically connected state by the switch circuit, and
A failure diagnosis signal line for inputting a failure diagnosis signal input by a delay circuit with a phase delayed from each of the plurality of communication lines in the previous stage of the switch circuit arranged on the second electronic board from the processor.
A wire harness that includes a plurality of the communication lines and the failure diagnosis signal line and connects the first electronic board and the second electronic board.
Control system,
The processor
A step of outputting a control signal to the switch circuit and outputting a High, Low, and clock signals to the failure diagnosis signal line, respectively.
A step of determining a failure location from the input signals of a plurality of the communication lines,
The step of outputting the judgment result and
How to include.

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