JPH06308170A - Comparator circuit - Google Patents

Abstract

PURPOSE:To provide a comparator circuit having no misoperation even when a minus input is applied thereto. CONSTITUTION:At a point between an emitter terminal of an input transistor Q4 that receives an input signal and a base terminal of a control transistor Q3, a compensation transistor Q9 of which base terminal is connected thereto is provided. The emitter terminal of the compensation transistor Q9 is connected to the ground and the collector terminal is connected to a collector terminal of an inverting transistor Q7. As a result, even when the transistor Q7 turns off, the transistor Q9 prevents a voltage of the collector terminal of the transistor Q7 from rising up, thereby preventing an output transistor Q8 from turning on caused by a misoperation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit, and more particularly to an improvement of a comparator circuit suitable for a differential amplifier or the like which can perform a comparing operation without malfunction even when an input signal fluctuates over a wide range.

[0002]

2. Description of the Related Art A comparison circuit for comparing two signal inputs with each other and performing an inversion operation is widely used. For example, as a level comparison circuit, a differential amplifier, or a threshold comparison circuit with one input potential fixed. It is used.

FIG. 3 shows a conventional comparison circuit, which has a first input signal V supplied to a first input terminal 10.
The second input signal V supplied to the _first and second input terminals 20
₂ is compared.

The first input signal V ₁ is supplied to the base of the first input transistor 11, and the emitter of the first input transistor 11 has a first control transistor 12
Connected to the base of.

The collector of the input transistor 11 is directly grounded, and the collector of the control transistor 12 is grounded via the collector / emitter of the transistor 13 forming a current mirror circuit. The collector-base of this transistor 13 is rendered conductive, and as will be described later, a current mirror circuit suppresses the opposite side comparison circuit branch to the off state.

On the other hand, the second input terminal 20 is connected to the base of the second input transistor 21, and the emitter of this input transistor 21 is the second control transistor 2.
It is connected to the base of 2. The collector of the input transistor 21 is grounded, and the collector of the control transistor 22 is grounded via the collector / emitter of the transistor 23. The transistor 23 has a base in common with the transistor 13 and constitutes a current mirror circuit.

The emitters of both control transistors 12 and 22 are commonly connected, and the constant current circuit 30 controls the control current I ₁
Is being supplied.

The emitter of the second control transistor 22 is connected to the base of the inverting transistor 31, and the emitter of the inverting transistor 31 is grounded.
The collector is connected to the power supply V _CC via the constant current circuit 32. The collector of the inverting transistor 31 is connected to the base of the output transistor 33, the emitter of the output transistor 33 is grounded, and the collector is connected to the output terminal 40. In the figure, power supply and output terminal 4
A load R _L is connected between 0 and 0 as required.

The comparison operation when the _first input signal V ₁ is fixed to a constant value will be described below with reference to FIG.

When the second input signal V ₂ is smaller than the fixed value V ₁ (V ₂ <V ₁ ), the “H” signal is output to the output terminal 40.

That is, since the second input signal V ₂ is low, the input transistor 21 and the control transistor 22 are
Is turned on, while the first input transistor 11
Also, the control transistor 12 is turned off. Therefore,
The control current I ₁ flows to the second control transistor 22 side. As a result, a current is supplied to the base of the inverting transistor 31 and the transistor 31 is turned on. As a result, the constant current I ₂ flows to the collector / emitter of the inverting transistor 31, so that the output transistor 33 is turned off.
Therefore, as described above, the "H" level is output to the output terminal 40.

On the other hand, when the second input signal V ₂ rises and exceeds the first input signal V ₁ , the first input transistor 11 and the control transistor 12 are turned on. Then, the second input transistor 21 and the control transistor 22 are inverted to the off state, and this state is surely held by the current mirror circuit.

Therefore, the inverting transistor 31 is inverted to the off state, and as a result, the output transistor 33 is turned on to invert the output terminal to the "L" level.

[0014]

As described above, according to the conventional comparison circuit, a desired comparison and inverting action can be obtained, but when the input signal becomes a negative input level, a malfunction occurs. was there.

Such a negative input signal is generated, for example, when noise is mixed in the input terminal, and the input signal may temporarily drop to a negative potential. Further, such a situation also occurs due to the fluctuation of the ground potential, and the conventional comparison circuit described above has a problem that it is weak against noise or fluctuation of the ground potential.

Now, in FIG. 3, the second input transistor 21 and the control transistor 22 are in the ON state (V ₂ <V
₁ ). At this time, the control transistor 2
The emitter potential (point A) of ₂ becomes V ₂ + 2V _BE (V _BE : base-emitter voltage).

At this time, since the inverting transistor 31 is in the ON state, the collector of the control transistor 22 (point B).
The potential is V _BE . It is assumed that the characteristics of each transistor are almost constant.

Therefore, when the second input signal V ₂ becomes negative, the potential at the point A indicated by V ₂ + 2V _BE becomes V _BE.
The potential difference between points A and B, that is, V _{CE of the} control transistor 22 is reduced.
At some point, the control transistor 22 will be cut off.

In such a case, the inverting transistor 3
Since the current supply to the base of No. 1 is cut off and the inverting transistor 31 is turned off, the output transistor 33
Is turned on, and a malfunction occurs in which an “L” level signal is output to the output terminal 40.

In order to solve such a problem, for example, Japanese Unexamined Patent Publication No. 4-225618 discloses a comparator in which predetermined resistors are connected to the base terminals of the input transistor and the control transistor.

A circuit diagram of the comparator described herein is shown in FIG. As shown in FIG. 5, the difference between this comparator and the comparator shown in FIG. 3 is that the input resistors 14 and 24 and the level-up resistors 15 and 2 are different.
5 is connected.

Therefore, according to the comparator described here, when the negative input signal is applied, the collector-base of the input transistor is made conductive, and the base potential is fixed to the collector-base potential (V _F ). To do. Then, when the control transistor 22 is cut off, the current flowing from the control transistor to the input transistor passes through the level-up resistance, so that the emitter potential of the control transistor can be maintained at a value sufficiently higher than its collector potential, unlike the conventional case. It is possible to surely prevent the temporary reversal of the control transistor by both clamping the base potential of the input transistor and raising the emitter potential of the control transistor.

However, this comparator has a problem that the number of resistance elements increases. In addition, in forming the transistors 12 and 22, D
A new eep n ⁺ diffusion step is required.

That is, normally, the transistors 12 and 22 are
For this purpose, L-PNP is used, but when saturated, most of the current flowing from the emitter flows out to the substrate (GND). Therefore, in order to efficiently supply current to the resistor 25 from the base terminal of the transistor 22 which is saturated at the time of negative input, the transistors 12 and 22 are deep n ^+.
Hfe of the parasitic PNP transistor
To lower the current flowing out to the substrate (GND).

The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a comparator circuit which does not cause a malfunction even when a negative input signal is applied and is excellent in stability. And to provide a comparison circuit that is easy to manufacture.

[0026]

In order to achieve the above object, a first aspect of the present invention provides a first input transistor whose base is supplied with a first input signal, and an emitter of the first input transistor. A first control transistor having a base connected to the second control transistor, and a second control transistor having a second input signal supplied to the second control signal.
Constant current circuit for supplying a control current to the input transistor, the second control transistor whose base is connected to the emitter of the second input transistor, and the common-connected emitter of the first and second control transistors. A base connected to the collector of the second control transistor and an emitter connected to the ground; and an inversion transistor connected to the collector to the base and an emitter connected to the ground. An output transistor that outputs a signal indicating the comparison result of the magnitudes of the first and second input signals from the collector of the output transistor, and a base is provided at the emitter of the second input transistor. Connected,
An emitter is connected to the base of the output transistor,
It is a comparison circuit including a compensation transistor whose collector is connected to the ground.

In order to achieve the above object, in the second aspect of the present invention, a base is connected to a first input transistor to which a first input signal is supplied to the base, and an emitter of the first input transistor. A first control transistor and a second
Second input transistor whose base is connected to the emitter of the second input transistor, a second control transistor whose base is connected to the emitter of the second input transistor, and common connection of the first and second control transistors. A constant current circuit for supplying a control current to the emitter, a base connected to the collector of the second control transistor, an emitter connected to the ground, and a base connected to the collector of the inversion transistor An output transistor having an emitter connected to ground, and a comparator circuit for outputting a signal representing the comparison result of the magnitudes of the first and second input signals from the collector of the output transistor, A resistor whose one end is connected to the base of the output transistor and whose other end is connected to the power supply current terminal The base to the emitter of the second input transistor is connected, an emitter connected to the other end of said resistor, a comparator circuit, characterized in that it comprises a compensation transistor, the collector is connected to ground.

[0028]

According to the first aspect of the present invention, the compensation transistor prevents the voltage of the base terminal of the output transistor from rising. Therefore, even if the inverting transistor is turned off, the output transistor is turned on. There is no.

According to the second aspect of the present invention, since the collector terminal of the compensation transistor is connected to the collector terminal of the inverting transistor via the resistor, the output transistor is less likely to be turned on, and malfunction of the output transistor is prevented. .

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows a circuit diagram of a comparison circuit which is a preferred embodiment of the present invention. As shown in FIG. 1, the comparison circuit according to this embodiment has almost the same configuration as the conventional comparison circuit shown in FIG. As in the conventional case, the transistors Q1, Q2, Q3 and Q4 form a differential amplifier section, and the transistors Q5 and Q6 form a current mirror circuit. Further, the output signal of the collector of the transistor Q3 is supplied to the output transistor Q8 via the output inverting transistor Q7.

A feature of this embodiment is that the compensation transistor Q9 is provided. This compensation transistor is a PNP type transistor, the emitter terminal of which is connected to the base terminal of the output transistor Q8. The base terminal of the compensation transistor Q9 is connected to the base terminal of the control transistor Q3, and its collector terminal is grounded.

As described above, in this embodiment, the input signal Vin which is the voltage at the base terminal of the input transistor Q4.
Even if the voltage of − is lowered and the inverting transistor Q7 is turned off, the collector terminal of the inverting transistor Q7 does not fall below a certain voltage. The reason is as follows. Since the voltage Vin- ', which is the voltage at the emitter terminal of the input transistor Q4, is applied to the base terminal of the compensating transistor Q9, the emitter terminal of this compensating transistor Q9 can only be at a voltage higher than Vin-' by approximately 0.6 volts. I won't. Therefore, the collector terminal of the inverting transistor Q7 to which the emitter terminal of the compensation transistor Q9 is connected is
Even if 7 is turned off, it is only below a certain potential,
The output transistor Q8 does not turn on.

The detailed operation of the present invention will be described below.

The voltage V _{BEQ9 (ON)} (base-emitter voltage) at which the compensation transistor Q9 is turned on, which is a characteristic feature of the present embodiment, is the voltage V _{BEQ8 (ON) at which} the output transistor Q8 is turned on (base _). -Emitter voltage). For example, in the present embodiment shown in FIG. 1, the output transistor is an NPN type and the compensation transistor Q9 is an L-PNP type, but in general, when comparing the NPN type and the L-PNP type, -P
Generally, the NP type has a lower on-operation voltage. Therefore, as in the present embodiment, it is easy to set the voltage at which the compensation transistor Q9 turns on to be low. Further, by increasing the emitter area of the compensation transistor Q9, it is possible to further reduce the on-operation voltage.

In the present embodiment, when the relationship of Vin +> Vin− is established between two input signals, further, the input signal Vin− becomes lower than the ground potential, so that Vin− ′ becomes approximately. When the voltage reaches "0", the transistor Q7 is turned off. Where Vi
n− ′ is the voltage of the emitter terminal of the input transistor Q4, that is, the voltage of the base terminal of the control transistor Q3.

For example, when Vin- becomes approximately "0.6" volts, Vin- 'becomes approximately "0" volts,
As a result, the voltage at the emitter terminal of the control transistor Q3 is approximately "0.6" volt. Therefore, in order for the control transistor Q3 to maintain the ON operation, at least the voltage at the collector terminal of the control transistor Q3 is
It must be lower than the voltage at the emitter terminal, so that the voltage at the base terminal of the inverting transistor Q7 is approximately "0.
It will be about 6 "volts.

In this way, Vin- is approximately "0.
Below 6 "volts, the inverting transistor Q7 will be turned off. However, according to this embodiment, the voltage of the collector terminal of the inverting transistor Q7 is prevented from rising due to the function of the compensation transistor Q9. That is, since the base terminal of the compensation transistor Q9 is connected to the base terminal of the control transistor Q3, even if the voltage of the base terminal of the control transistor Q3 (that is, Vin− ′) becomes about “0” volt,
The transistor Q9 does not turn off, and the compensation transistor Q9
The emitter terminal of 9 is maintained at about "0.6" volts.

This is exactly what is characteristic of this embodiment. In this way, even if the inverting transistor Q7 turns off, the collector terminal voltage can be prevented from rising, so that it is possible to prevent the output transistor Q8 from turning on and its output becoming "L". It is possible.

In this embodiment, the input voltage Vin- in the range in which the output signal can be maintained at "H" by the function of the compensation transistor Q9 is calculated as follows.

V _{CEQ3 (SAT)} ≈ “0” volt, V
_{If BEQ1 (ON) to} V _{BEQ8 (ON)} ≈V _BE , then {V _{BEQ8 (ON)} -V _{BEQ9 (ON)} }-V _{BEQ4 (ON)} =-V _{BEQ9 (ON)} . That is, the input signal voltage Vin-<-V
_{As long as} it is _{BEQ9 (ON)} , the output signal can maintain "H". As described above, according to this embodiment, it is possible to sufficiently perform the operation up to the ground level, which is the purpose of this comparator.

Embodiment 2 In the embodiment shown in FIG. 1, the compensation transistor Q
Although the emitter terminal of 9 is directly connected to the collector terminal of the inverting transistor Q7 (and the base terminal of the output transistor Q8), it is also preferable to connect it through a resistor of a certain size. FIG. 2 shows a circuit diagram in the case where the connection is made through the resistors as described above. FIG. 2 shows only a circuit diagram of a portion including the compensation transistor Q9, the inverting transistor Q7, the output transistor Q8, and the constant current source I. As shown in FIG. 2, the constant current source I
The current from the output transistor Q8 and the collector terminal of the inverting transistor Q7 through the resistor R of a certain size.
It is connected to the base terminal of. The collector terminal of the compensation transistor Q9 is connected to the constant current source side of the resistor R (point indicated by "B" in the figure).

As described above, since the collector terminal of the compensation transistor Q9 is connected to the base terminals of the inverting transistor Q7 and the output transistor Q8 via the resistor R, malfunction can be prevented more reliably than in the first embodiment. Is.

In the circuit shown in FIG. 2, the voltage at the point B must rise to RI + V _{BEQ8 (ON)} in order for the output transistor Q8 to turn on. In comparison, the compensation transistor Q9 is turned on at a base voltage sufficiently lower than the output transistor Q8 is turned on. Therefore, as compared with the circuit shown in FIG. 1, malfunction can be surely prevented.

In the case of the circuit shown in FIG. 2, the voltage range of the input signal at which the output signal is "H" is calculated as follows. As described above, if V _{CEQ3 (SAT)} ≈ “0” volt and V _{BEQ1 (ON) to} V _{BEQ8 (ON)} ≈V _BE , then {V _{BEQ8 (ON)} + RI−V _{BEQ9 (ON)} } − V _{BEQ4 (ON)} =-V _{BEQ9 (ON)} + RI. That is, if the resistance R satisfies −V _{BEQ9 (ON)} + RI <0 R <V _{BEQ9 (ON)} / I, the operation up to the ground level is sufficiently possible. As described above, according to the present embodiment, it is possible to reliably prevent malfunction even when the voltage of the input signal falls below the ground level.

Further, in both the first and second embodiments, the base terminal of the compensation transistor Q9 is the emitter terminal of the input transistor Q4 and the control transistor Q9.
Since it is connected to the point connecting to the base terminal of No. 3, the input current offset caused by the leak current due to the provision of the compensation transistor Q9 hardly appears.

[0047]

As described above, according to the present invention, the compensation transistor is added so that the output transistor does not turn on even when the inverting transistor turns off. Therefore, the input signal is lower than the ground level. It is possible to provide a stable comparison circuit that does not malfunction even in the case of a failure.

Further, by connecting the emitter terminal of the compensation transistor to the collector terminal of the inverting transistor via a resistor, it is possible to provide a comparison circuit which can prevent malfunction more reliably.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a comparison circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of a comparison circuit according to the present invention.

FIG. 3 is a circuit diagram of a conventional comparison circuit.

FIG. 4 is an explanatory diagram showing a conventional comparison / determination operation.

FIG. 5 is a circuit diagram of a conventional improved comparison circuit.

[Explanation of symbols]

 Q1 First input transistor Q2 First control transistor Q3 Second control transistor Q4 Second input transistor Q5, Q6 Transistor forming current mirror circuit Q7 Inversion transistor Q8 Output transistor Q9 Compensation transistor

Claims (2)

[Claims] 1. A first input transistor having a base supplied with a first input signal, a first control transistor having a base connected to an emitter of the first input transistor, and a second input signal A second input transistor supplied to the base, a second control transistor whose base is connected to the emitter of the second input transistor, and a commonly connected emitter of the first and second control transistors A constant current circuit for supplying a current, a base of the second control transistor is connected to the collector of the second control transistor, an inverting transistor of which the emitter is connected to the ground, and a base of the inverting transistor is connected to the collector of the inverting transistor, An output transistor whose emitter is connected to ground, and And a comparison circuit which outputs a signal indicating the comparison result of the magnitudes of the second input signals, wherein a base is connected to the emitter of the second input transistor, an emitter is connected to the base of the output transistor, and a collector is connected to the ground. And a compensation transistor to which is connected. 2. A first input transistor having a base to which a first input signal is supplied, a first control transistor having a base connected to an emitter of the first input transistor, and a second input signal A second input transistor supplied to the base; a second control transistor whose base is connected to the emitter of the second input transistor; and a common control emitter of the first and second control transistors A constant current circuit for supplying a current, a base of the second control transistor is connected to the collector of the second control transistor, an inverting transistor of which the emitter is connected to the ground, and a base of the inverting transistor is connected to the collector of the inverting transistor, An output transistor whose emitter is connected to ground, and And a second output circuit that outputs a signal indicating the comparison result of the magnitudes of the input signals, the resistor having one end connected to the base of the output transistor and the other end connected to a power supply current terminal; A comparator circuit comprising a compensation transistor having a base connected to the emitter of the second input transistor, an emitter connected to the other end of the resistor, and a collector connected to the ground.