JPH06177661A - Operational amplifier - Google Patents

Abstract

PURPOSE:To realize an operational amplifier whose output minimum voltage is not limited by a short-circuit protection circuit for a high level output of the operational amplifier. CONSTITUTION:An operational amplifier is provided with an inverting input terminal 101, a noninverting input terminal 102, an output terminal 103, a load resistor 13, an input stage differential amplifier circuit 1, a gain circuit 2, a phase compensation capacitor 3 connected in parallel with the gain circuit 2, and an output circuit 4 having a current source 5, diodes 6, 7, PNP transistors(TRs) 8, 10, NPN TRs 9, 10, 11 and a resistor 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier, and more particularly to an operational amplifier having an output short circuit protection circuit for high potential.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit operational amplifier, an output circuit may be provided with an output short-circuit protection circuit corresponding to a high potential. FIG. 3 is a circuit diagram showing an example of the operational amplifier, but such a conventional operational amplifier has a bias supply circuit corresponding to the inverting input terminal 107, the non-inverting input terminal 108, the output terminal 109 and the load resistor 68. 41, resistors 42, 48 and 49, PNP transistors 43 to 45, and an input stage differential amplifier circuit 40 including NPN transistors 46 and 47, and a gain including NPN transistors 51 and 52, a current source 53, and resistors 54 and 55. A circuit 50, a phase compensation capacitor 56 connected in parallel to the gain circuit 50, a current source 58,
Diodes 59 and 60, PNP transistor 61,
63 and 65, NPN transistors 62, 66 and 67, and an output circuit 57 including a resistor 64.

[0003] In FIG. 3, the high-level power supply + V _cc and the positive power source and the low-potential power supply -V _cc and the negative power supply. A bias voltage for setting the current value of the differential amplifier circuit 40 is applied to the PNP transistor 43 from the bias supply circuit 41, and the input signals input from the inverting input terminal 106 and the non-inverting input terminal 108 are The signal is amplified by the differential amplifier circuit 40 and input to the gate of the NPN transistor 51 included in the gain circuit 50. The output terminal of the differential amplifier circuit 40 is connected to the collector of the NPN transistor 66 included in the output circuit 57. Gain circuit 50
Between the input and output ends of the phase compensation capacitor 5
6 is connected, a signal of a predetermined level is output through the gain circuit 50, and P included in the output circuit 57 is connected.
It is input to the gate of the NP transistor 61.

In the output circuit 57, the resistor 64 and the PNP transistor 6 included in the output circuit 57 are included.
3, an output short circuit for a high potential is formed by the NPN transistors 66 and 67, and the resistor 64 functions as a resistor for detecting an output short circuit current corresponding to the high potential. The resistance value R 64 of the resistor ₆₄ is obtained by the following equation, but is usually set to a value of about 20 to 50Ω.

R ₆₄ = V _{BE63 (ON)} / I _oshort …………………… (1) However, V _{BE63 (ON)} : _{P BE} transistor turns ON V _BE
Value _I oshort: the value of the output short-circuit current above I _Oshort corresponding to the high potential is set to several times the current value of the value of the output current I _L flowing through the load resistor 68 in normal use.

When the output terminal 103 is at a potential lower than the ground potential, the output current I _L flows through the resistor 64,
Since it is smaller than the current value of _{Ioshort in} a normal state, the voltage drop V ₆₄ due to the resistor ₆₄ is given by the following equation.

V ₆₄ = R ₆₄ · I _L <V _{BE63 (ON)} (2) Therefore, the existence of the PNP transistor 63 can be ignored.

Next, when the potential of the output terminal 103 is set to a high potential such that the emitter current does not flow in the NPN transistor 62 in the output circuit 57, for example, in the state where it is short-circuited to the high potential side power supply + _Vcc , the output The current I _L increases to reach I _oshort , and the voltage drop V due to the resistor 64
₆₄ becomes as follows. V ₆₄ = R ₆₄ · I _oshort = V _{BE63 (ON)} (3) As a result, the PNP transistor 63 is turned on. NPN transistor 66 and NPN transistor 67
Forms a current mirror circuit, a current of the same magnitude as the collector current of the PNP transistor 63
The base current of NPN transistor 51, which flows as the collector current of NPN transistors 66 and 67 and forms the input portion of gain circuit 40, is extracted. As a result, the NPN transistors 51 and 52 and the PNP transistors 61 and 65 are turned off, and the PNP transistor 65 is prevented from being destroyed when the output terminal 103 is short-circuited to a high potential.

Now, when the input voltage V _I and the output voltage V _O are set as shown in FIG. 3 and the input voltage V _I is decreased from 0 V, the output voltage V _O is given by the following equation.

V _O = (V _I + V _BE61 + V _BE65 ) _RL / (R ₆₄ + _RL ) ... (4) where V _{BE61 is} the value of V _BE of the PNP transistor 61 V _{BE65 is} the value of the PNP transistor 65 the value of V _bE Therefore, the inclination becomes a straight line _{R L / (R 64 + R} L) in equation (4). The minimum value V _OMIN of the output voltage V _O when the input voltage V _{I is set} to the lower power supply −V _cc is given by the following equation.

[0011] _{V OMIN = (+ V cc +} V BE61 + V BE65) R L / (R 64 + R L) ...... (5)

In the operational amplifier provided with the conventional output short-circuit protection circuit described above, the lower limit of the output voltage is limited by the resistor 64 as shown in the equation (5). As is clear from the equation (5), this has a drawback that it further increases as the resistance value _RL of the load resistor 68 becomes smaller, and the dynamic range of the operational amplifier is reduced.

[0012]

An operational amplifier according to a first aspect of the present invention includes a differential amplifier circuit that forms an input stage, an amplifier circuit that amplifies and outputs a signal output from the differential amplifier circuit.
In an operational amplifier including an output circuit that receives a signal output from the amplifier circuit and outputs the signal to a predetermined load circuit,
The output circuit has a first NPN transistor having a collector connected to a high-potential side power supply and an emitter connected to an output terminal connected to the load circuit; and an emitter connected to the output terminal and a collector having a predetermined resistance. Connected to the low-side power supply via the and functioning as an output transistor
PNP transistor, high side power supply and the first NP
A current source inserted between the base of the N-transistor, the base of the first NPN transistor and the first
And a diode connected in a forward direction between the base and the base of the PNP transistor of
Second PNP transistor connected to the base of the PNP transistor, the base of which is connected to the output terminal of the amplifier circuit, and the collector of which is connected to the lower power supply, and the collector of which is connected to the output terminal of the differential amplifier circuit. A second NPN transistor whose base is connected to the collector of the first PNP transistor and whose emitter is connected to the lower power supply.

The operational amplifier of the second invention is a differential amplifier circuit which forms an input stage, an amplifier circuit which amplifies and outputs a signal output from the differential amplifier circuit, and is output from the amplifier circuit. An operational amplifier including an output circuit that receives a signal and outputs the signal to a predetermined load circuit, wherein the differential amplifier circuit has a emitter connected to a high-potential side power supply through a first resistor and functions as a current source. And a second PNP transistor at the base of the first PNP transistor.
And a bias supply circuit for supplying a bias voltage to the base of the first PNP transistor, and the emitter thereof are commonly connected to the collector of the first PNP transistor, and the bases are respectively inverting input terminals and A second and a third connected to the non-inverting input terminal to form a pair of amplifier circuit elements in the differential amplifier circuit.
And a collector and a base are both connected to the collector of the second PNP transistor,
A first NPN transistor having an emitter connected to a low-potential side power source through a third resistor, and a collector having the third PPN transistor.
A second connected to the collector of the NP transistor, a base connected to the base of the first NPN transistor, and an emitter connected to the lower power supply through a fourth resistor;
The NPN transistor of the third PNP transistor is connected to the collector of the second NPN transistor as an output point of the differential amplifier circuit, and the output circuit has a high-potential-side power supply. And a collector connected to the base of the first PNP transistor, an emitter connected to a high-potential side power supply, and a base and a collector connected to the fourth PNP transistor.
Connected to the base of a PNP transistor of
A fifth PNP transistor forming a current mirror circuit with the PNP transistor of No. 3, a third NPN transistor having a collector connected to the high-potential side power supply and an emitter connected to an output terminal connected to the load circuit, and an emitter A sixth PNP transistor connected to the output terminal and having a collector connected to a low-potential side power source through a resistor to function as an output transistor; a high-potential side power source and a base of the third NPN transistor. A current source inserted between and a diode connected in a forward direction between the base of the third NPN transistor and the base of the sixth PNP transistor;
An emitter is connected to the base of the sixth PNP transistor, and the base is connected to the output terminal of the amplifier circuit,
A seventh PNP transistor having a collector connected to the low-potential power supply, a collector connected to the bases of the fourth and fifth PNP transistors, and a base connected to the sixth PN transistor.
A fourth NPN transistor connected to the collector of the P transistor and having its emitter connected to the lower power supply.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment corresponds to the inverting input terminal 101, the non-inverting input terminal 102, the output terminal 103, and the load resistor 13, and the differential amplifier circuit 1 at the input stage.
A gain circuit 2, a phase compensation capacitor 3 connected in parallel to the gain circuit 2, a current source 5, diodes 6 and 7, PNP transistors 8 and 10, NPN transistors 9, 10 and 11, and a resistor 12. And an output circuit 4 including

In FIG. 1, a resistor 1 included in the output circuit
Reference numeral 2 denotes a resistor for detecting the collector current of the PNP transistor 10 at the time of output short circuit corresponding to a high potential, and its resistance value R ₁₂ is set by the following equation.

R ₁₂ = V _{BE11 (ON)} / I _cshort (6) where V _{BE11 (ON)} : collector current of NPN transistor 11 I _cshort : output short circuit corresponding to high potential The collector current of the PNP transistor 10 at the time when the voltage drop V ₁₂ across the resistor ₁₂ is normally NPN.
Since the collector current I _C1 of the transistor 10 is smaller than I _cshort , it is given by
The existence of the PN transistor 11 can be ignored.

V ₁₂ = R ₁₂ · I _C1 <V _{BE11 (ON)} (7) When the output terminal 103 is set to a high potential such that the emitter current of the NPN transistor 9 does not flow, For example, when the output terminal 103 is short-circuited to the high potential side power supply + V _cc , the collector current I _C of the PNP transistor 10 increases to reach I _cshort , and the voltage drop V ₁₂ due to the resistor 12 _occurs.
Is as follows. V ₁₂ = R ₁₂ · I _cshort = V _{BE11 (ON)} (8) As a result, the PNP transistor 11 is turned on, and the collector current I _C11 flows through the PNP transistor 11. As a result, the input current in the input section of the gain circuit 2 is drawn out, and the PN is input as in the case of the above-mentioned conventional example.
The output current of the P-transistor 10 is prevented from increasing and breaking.

When the input voltage V _I and the output voltage V _O are set as shown in FIG. 1 and the input voltage V _I is decreased from 0 V, the output voltage V _O is given by the following equation.

V _O = V _I + V _BE8 + V _BE10 ………………………………
(9) where, V _BE8: value of V _BE of the PNP transistor 8 V _BE10: value of V _BE of the PNP transistor 10 thus, (9) the slope becomes a first straight line in V _O in the equation, the output short-circuit protection circuit Not equivalent to a circuit. The minimum value V _OMIN of the output voltage V _O when the input voltage V _I is set to the low-potential-side power supply −V _cc is _given by the following equation.

V _OMIN ≈ (−V _cc ) + V _BE8 + V _BE10 ) ……………… (1
0) That is, the minimum value V _OMIN of the output voltage V _O is, in the case of the above-mentioned conventional example, as is clear from the above equation (10).
The term of the coefficient R _L / (R ₆₄ + R _L ) shown in the equation (5) is eliminated, and in the present invention, a circuit not provided with an output short-circuit protection circuit corresponding to a high potential and an output voltage. The minimum value of is equal. For example, the resistance value R of the load resistor 13
_{When L} is 220Ω and the resistance values R12 and R64 of the resistors 12 and 64 (conventional example) are respectively 25Ω, in the present invention, the minimum output voltage is 11.4% compared to the conventional example. Be improved.

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing this embodiment. As shown in FIG. 2, in the present embodiment, the inverting input terminal 104, the non-inverting input terminal 105, the output terminal 106 and the load resistor 39.
Corresponding to the bias supply circuit 16, resistors 17, 18,
24 and 25, an input stage differential amplifier circuit 15 including PNP transistors 19 to 21, and NPN transistors 22 and 23, a gain circuit 37, and a phase compensation capacitor 38 connected in parallel to the gain circuit 37. PN
P-transistors 27, 28, 32 and 34, current source 2
9, diodes 30 and 31, NPN transistor 3
3 and 35, and an output circuit 26 including a resistor 36.

In FIG. 2, the resistance value of the resistor 18 included in the differential amplifier circuit 15 is set to such a value that the voltage drop due to the base current of the PNP transistor 19 which normally functions as a current source is negligible. . The other circuit configuration of the differential amplifier circuit 15 is the same as that of the first embodiment. In the output circuit 26, FIG.
When the output terminal 106 is short-circuited to a high potential and the collector current I _C of the PNP transistor 34 reaches the current value of I _cshort , as in the case of the first embodiment, the above equation (8) is established. The NPN transistor 35 is turned on,
A collector current I _C35 flows through the NPN transistor 35 to form a PNP forming a current mirror circuit.
The collector current T is applied to the transistors 27 and 28.
_A collector current equal to _C35 flows, and V _BE11 of the PNP transistor 19 for the current source rises by the potential shown by the following equation.

ΔV _BE11 = R ₁₈ · I _C35 (11) In the above equation, R ₁₈ is the resistance value of the resistor 18. As a result, the collector current of the PNP transistor 18 for the current source is reduced, so that the current flowing through the differential amplifier circuit 15 is also reduced, and the operation in the gain circuit 37 and thereafter is
This is the same as in the case of the first embodiment described above, and the output PN
The increase and breakdown of the output current in the P-transistor 34 are prevented in advance. In addition, the maximum value V of the output voltage V _O
The value of _OMAX is also equal to that in the first embodiment shown in FIG.

[0025]

As described above, the present invention has an effect that the lower limit of the output voltage by the short-circuit protection circuit corresponding to the high potential can be eliminated and the reduction of the amplification dynamic range can be eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 15, 40 Differential amplifier circuit 2, 37, 50 Gain circuit 3, 38, 56 Phase compensation capacitor 4, 26, 57 Output circuit 5, 29, 53, 58 Current source 6, 7, 30, 31, 59 , 60 Diodes 8, 10, 19-21, 27, 28, 32, 34, 43
~ 45, 61, 63, 65 PNP transistors 9, 11, 22, 23, 33, 35, 46, 47, 5
1, 52, 62, 66, 67 NPN transistor 12, 17, 18, 24, 25, 36, 42, 48, 4
9, 54, 55, 64 resistance 13, 39, 68 load resistance 16, 41 bias circuit

Claims (2)

[Claims] 1. A differential amplifier circuit that forms an input stage, an amplifier circuit that amplifies and outputs a signal output from the differential amplifier circuit, and a signal output from the amplifier circuit,
An operational amplifier including an output circuit for outputting to a predetermined load circuit, wherein the output circuit has a first NPN transistor having a collector connected to a high-potential side power supply and an emitter connected to an output terminal connected to the load circuit. A first PNP transistor having an emitter connected to the output terminal and a collector connected to a low-potential side power supply through a predetermined resistor to function as an output transistor; and a high-potential side power supply and the first NPN transistor. A current source inserted between the base and the base, the base of the first NPN transistor and the first P
A diode connected to the base of the NP transistor in the forward direction, an emitter connected to the base of the first PNP transistor, and a base connected to the output terminal of the amplifier circuit,
A second PNP transistor having a collector connected to the low potential side power source; a collector connected to the output terminal of the differential amplifier circuit; a base connected to the collector of the first PNP transistor; Second NPN connected to
An op amp characterized by comprising a transistor and. 2. A differential amplifier circuit forming an input stage, an amplifier circuit for amplifying and outputting a signal output from the differential amplifier circuit, and a signal output from the amplifier circuit,
An operational amplifier including an output circuit for outputting to a predetermined load circuit, wherein the differential amplifier circuit has a first P whose emitter is connected to a high-potential side power supply through a first resistor and which functions as a current source.
An NP transistor, a bias supply circuit connected to the base of the first PNP transistor via a second resistor, and supplying a bias voltage to the base of the first PNP transistor, and the emitter of the first PNP transistor. Second and third P transistors which are commonly connected to the collectors of the transistors and whose bases are respectively connected to the inverting input terminal and the non-inverting input terminal to form a pair of amplifier circuit elements in the differential amplifier circuit.
An NP transistor, a first NPN transistor whose collector and base are both connected to the collector of the second PNP transistor, and whose emitter is connected to a lower power supply through a third resistor; A second NPN transistor connected to the collector of the PNP transistor, the base of which is connected to the base of the first NPN transistor, and the emitter of which is connected to the low potential side power supply through the fourth resistor; A connection point between the collector of the third PNP transistor and the collector of the second NPN transistor is configured as an output point of the differential amplifier circuit, and the output circuit has an emitter connected to a high-potential side power supply and a collector connected to the first power source. The 4th PNP transistor connected to the base of the 1st PNP transistor, and the emitter to the high side power supply. Is continued, the base and collector connected to the base of the fourth PNP transistor,
A fifth PNP transistor forming a current mirror circuit together with the fourth PNP transistor, and a third NPN transistor having a collector connected to a high-potential side power source and an emitter connected to an output terminal connected to the load circuit. A sixth PNP transistor having an emitter connected to the output terminal and a collector connected to the fifth-side low-side power source through a resistor to function as an output transistor; a high-side-side power source and the third NPN transistor. A current source inserted between the base and the base of the third NPN transistor and the sixth P
A diode connected to the base of the NP transistor in the forward direction, an emitter connected to the base of the sixth PNP transistor, and a base connected to the output terminal of the amplifier circuit,
A seventh PNP transistor having a collector connected to the low-side power supply, a collector connected to the bases of the fourth and fifth PNP transistors, a base connected to the collector of the sixth PNP transistor, and an emitter An operational amplifier comprising: a fourth NPN transistor connected to a lower power supply.