JP2845065B2 - Operational amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier, and more particularly to an operational amplifier having an output short-circuit protection circuit for a high potential.

[0002]

2. Description of the Related Art In a conventional operational amplifier of a semiconductor integrated circuit, an output circuit may be provided with an output short-circuit protection circuit corresponding to a high potential. FIG. 3 is a circuit diagram showing an example of the operational amplifier. Such a conventional operational amplifier includes a bias supply circuit corresponding to an inverting input terminal 107, a non-inverting input terminal 108, an output terminal 109, and a load resistor 68. 41, resistors 42, 48 and 49, PNP transistors 43 to 45, and an input stage differential amplifier circuit 40 including NPN transistors 46 and 47, and NPN transistors 51 and 52, a current source 53, and a gain including resistors 54 and 55. A circuit 50, a phase compensation capacitor 56 connected in parallel to the gain circuit 50, a current source 58,
Diodes 59 and 60, PNP transistor 61,
63 and 65, NPN transistors 62, 66 and 67, and an output circuit 57 including a resistor 64.

[0003] In FIG. 3, the high-level power supply + V _cc and the positive power source and the low-potential power supply -V _cc and the negative power supply. A bias voltage for setting the current value of the differential amplifier circuit 40 is supplied to the PNP transistor 43 from the bias supply circuit 41, and the input signals input from the inverting input terminal 106 and the non-inverting input terminal 108 Is amplified by the differential amplifier circuit 40 and input to the gate of the NPN transistor 51 included in the gain circuit 50. The output terminal of the differential amplifier circuit 40 is connected to the collector of the NPN transistor 66 included in the output circuit 57. Gain circuit 50
Between the input terminal and the output terminal of the
6 is connected, a signal of a predetermined level is output through the gain circuit 50, and P
The signal is input to the gate of the NP transistor 61.

In the output circuit 57, a resistor 64 and a PNP transistor 6 included in the output circuit 57 are used.
3. An output short circuit for a high potential is formed by the NPN transistors 66 and 67, and the resistor 64 functions as a resistor for detecting an output short circuit current corresponding to the high potential. The resistance value R 64 of the resistor ₆₄ is obtained by the following equation, and is usually set to a value of about 20 to 50Ω.

R ₆₄ = V _{BE63 (ON)} / I _oshort (1) where V _{BE63 (ON)} : V _{BE at which the} PNP transistor is turned on
Value _I oshort: the value of the output short-circuit current above I _Oshort corresponding to the high potential is set to several times the current value of the value of the output current I _L flowing through the load resistor 68 in normal use.

[0006] When the output terminal 103 is at a lower potential than the ground potential, the output current I _L has a resistance 64 flows,
In a normal state, _since the current value is smaller than the current value of I _oshort, the voltage drop V ₆₄ due to the resistor ₆₄ is given by the following equation.

[0007] _{V 64 = R 64 · I L} <V BE63 (ON) ..................... (2) Therefore, it is possible to present the PNP transistor 63 is negligible.

Next, when the potential of the output terminal 103 is set to a high potential that does not allow an emitter current to flow through the NPN transistor 62 in the output circuit 57, for example, when the potential is short-circuited to the higher power supply + _Vcc , The current I _L increases to reach I _oshort , and the voltage drop V
₆₄ is as follows. V ₆₄ = R ₆₄ · I _oshort = V _{BE63 (ON)} (3) As a result, the PNP transistor 63 is turned on. NPN transistor 66 and NPN transistor 67
Since a current mirror circuit is formed, a current having the same magnitude as the collector current of the PNP transistor 63 is
The base current of NPN transistor 51, which flows as the collector current of NPN transistors 66 and 67 and forms the input of gain circuit 40, is drawn. As a result, the NPN transistors 51 and 52 and the PNP transistors 61 and 65 are turned off, and the PNP transistor 65 is prevented from being destroyed when the output terminal 103 is short-circuited to a high potential.

[0009] Now, set the input voltage V _I and the output voltage V _O, as shown in FIG. 3, lowering the input voltage V _I from 0V, the output voltage V _O is given by the following equation.

V _O = (V _I + V _BE61 + V _BE65 ) R _L / (R ₆₄ + R _L ) (4) where V _{BE61 is} the value of V _BE of the PNP transistor 61 and V _{BE65 is} the value of the _{VNP of the} PNP transistor 65. the value of V _bE Therefore, the inclination becomes a straight line _{R L / (R 64 + R} L) in equation (4). Minimum value V _OMIN the output voltage V _O when the input voltage V _I and the low-potential power supply -V _cc is represented by the following equation.

V _OMIN = (+ _Vcc + _VBE61 + _VBE65 ) R _L / (R ₆₄ + R _L ) (5)

In the above-mentioned operational amplifier provided with the conventional output short-circuit protection circuit, the lower limit of the output voltage is limited by the resistor 64 as shown in the above equation (5). As is apparent from the equation (5), this becomes more intense particularly as the value of the resistance value _RL of the load resistor 68 becomes smaller, and has a disadvantage that the dynamic range of the operational amplifier is reduced.

[0012]

According to a first aspect of the present invention, there is provided an operational amplifier comprising: a differential amplifier circuit forming an input stage; an amplifier circuit for amplifying and outputting a signal output from the differential amplifier circuit;
And an output circuit that receives a signal output from the amplifier circuit and outputs the signal to a predetermined load circuit.
The output circuit includes a first NPN transistor having a collector connected to the higher power supply, an emitter connected to an output terminal connected to the load circuit, an emitter connected to the output terminal, and a collector connected to a predetermined resistor. Is connected to the lower power supply through the first terminal and functions as an output transistor.
PNP transistor, a higher power supply, and the first NP
A current source inserted between the base of the N-type transistor and the base of the first NPN transistor;
A diode connected in a forward state between the base of the PNP transistor and an emitter connected to the first PNP transistor.
A second PNP transistor having a base connected to the output terminal of the amplifier circuit, a collector connected to the lower power supply, and a collector connected to the output terminal of the differential amplifier circuit. A second NPN transistor having a base connected to the collector of the first PNP transistor and an emitter connected to the lower power supply.

According to a second aspect of the present invention, there is provided an operational amplifier, comprising: a differential amplifier circuit forming an input stage; an amplifier circuit for amplifying and outputting a signal output from the differential amplifier circuit; And an output circuit for receiving a signal and outputting the signal to a predetermined load circuit, wherein the differential amplifier circuit has an emitter connected to a higher power supply via a first resistor and functions as a current source. One PNP transistor and a second PNP transistor at the base of the first PNP transistor.
, A bias supply circuit for supplying a bias voltage to the base of the first PNP transistor, and an emitter both commonly connected to the collector of the first PNP transistor; Second and third pairs connected to a non-inverting input terminal to form a pair of amplifier circuit elements in the differential amplifier circuit;
And a collector and a base are both connected to the collector of the second PNP transistor,
A first NPN transistor having an emitter connected to the lower power supply through a third resistor, and a collector connected to the third PPN transistor;
A second terminal connected to the collector of the NP transistor, a base connected to the base of the first NPN transistor, and an emitter connected to the lower power supply via a fourth resistor.
And a connection point between the collector of the third PNP transistor and the collector of the second NPN transistor as an output point of the differential amplifier circuit, wherein the output circuit has an emitter having a higher power supply. A fourth PNP transistor having a collector connected to the base of the first PNP transistor, an emitter connected to a higher power supply, and a base and a collector connected to the fourth PNP transistor.
Connected to the base of the PNP transistor of
A fifth PNP transistor that forms a current mirror circuit together with the PNP transistor, a third NPN transistor whose collector is connected to the higher power supply, and whose emitter is connected to an output terminal connected to the load circuit, and whose emitter is A sixth PNP transistor connected to the output terminal and having a collector connected to the lower power supply through a fifth resistor and functioning as an output transistor; a sixth PNP transistor that functions as an output transistor; and a sixth power supply and a base of the third NPN transistor. A current source inserted therebetween, a diode connected in a forward state between the base of the third NPN transistor and the base of the sixth PNP transistor,
An emitter is connected to a base of the sixth PNP transistor, and a base is connected to an output terminal of the amplifier circuit;
A seventh PNP transistor having a collector connected to the lower power supply, a collector connected to bases of the fourth and fifth PNP transistors, and a base connected to the sixth PN transistor;
A fourth NPN transistor connected to the collector of the P transistor and having an emitter connected to the lower power supply.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the differential amplifier circuit 1 of the input stage corresponds to the inverting input terminal 101, the non-inverting input terminal 102, the output terminal 103, and the load resistor 13.
A gain circuit 2, a phase compensation capacitor 3 connected in parallel to the gain circuit 2, a current source 5, diodes 6 and 7, PNP transistors 8 and 10, NPN transistors 9, 10 and 11, and a resistor 12 And an output circuit 4 including

In FIG. 1, a resistor 1 included in an output circuit
2 is a resistor for detecting the collector current of the PNP transistor 10 at the time of output short circuit corresponding to the high potential, the resistance value R ₁₂ is set by the following equation.

R ₁₂ = V _{BE11 (ON)} / I _cshort (6) where V _{BE11 (ON)} : collector current of NPN transistor 11 I _cshort : output short-circuit corresponding to high potential collector current the voltage drop V ₁₂ in the resistor 12 of the PNP transistor 10 of the time, usually NPN
Since the collector current I _C1 of the transistor 10 is smaller than I _cshort , it is given by the following equation.
The presence of the PN transistor 11 can be ignored.

V ₁₂ = R ₁₂ · I _C1 <V _{BE11 (ON)} (7) When the output terminal 103 is set to a high potential at which the emitter current of the NPN transistor 9 does not flow, For example, when the output terminal 103 is short-circuited to the higher power supply + _Vcc , the collector current I _C of the PNP transistor 10 increases to reach I _cshort , and the voltage drop V ₁₂ due to the resistor _12.
Becomes as follows. _{V 12 = R 12 · I cshort} = V BE11 (ON) ............... (8) Accordingly, the PNP transistor 11 is turned ON state, flows a collector current I _C11 to PNP transistor 11. As a result, the input current at the input section of the gain circuit 2 is extracted, and the PN current is reduced in the same manner as in the above-described conventional example.
The increase and the breakdown of the output current in the P transistor 10 are prevented.

[0019] Now, set the input voltage V _I and the output voltage V _O, as shown in FIG. 1, when Yuku reduce the input voltage V _I from 0V, the output voltage V _O is given by the following equation.

V _O = V _I + V _BE8 + V _BE10 ……………………………
(9) where, V _BE8: value of V _BE of the PNP transistor 8 V _BE10: value of V _BE of the PNP transistor 10 thus, (9) the slope becomes a first straight line in V _O in the equation, the output short-circuit protection circuit It is equivalent to no circuit. The minimum value V _OMIN of the output voltage V _O when the input voltage V _I is set to the low-potential-side power supply −V _cc is _expressed by the following equation.

V _OMIN ≒ (−V _cc ) + V _BE8 + V _BE10 )... (1)
0) That is, the minimum value V _OMIN of the output voltage V _O is, as _apparent from the above equation (10),
The term of the coefficient R _L / (R ₆₄ + R _L ) shown in the equation (5) is eliminated, and in the present invention, a circuit having no output short-circuit protection circuit corresponding to a high potential and an output voltage Are equal. For example, the resistance value R of the load resistor 13
_{When L} is 220Ω and the resistance values R12 and R64 of the resistors 12 and 64 (conventional example) are each 25Ω, in the present invention, the minimum value of the output voltage is 11.4% as compared with the conventional example. Be improved.

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing the present embodiment. As shown in FIG. 2, the present embodiment has an inverting input terminal 104, a non-inverting input terminal 105, an output terminal 106, and a load resistor 39.
Corresponding to the bias supply circuit 16, the resistors 17, 18,
24 and 25, a PNP transistor 19 to 21, and an input stage differential amplifier circuit 15 including NPN transistors 22 and 23; a gain circuit 37; a phase compensation capacitor 38 connected in parallel to the gain circuit 37; PN
P transistors 27, 28, 32 and 34, current source 2
9, diodes 30 and 31, NPN transistor 3
3 and 35, and an output circuit 26 including a resistor 36.

In FIG. 2, the resistance value of the resistor 18 included in the differential amplifier circuit 15 is set to a value which is so small that the voltage drop due to the base current of the PNP transistor 19 which normally functions as a current source can be ignored. . The other circuit configuration of the differential amplifier circuit 15 is the same as that of the first embodiment. In the output circuit 26, FIG.
Similarly to the first embodiment, when the output terminal 106 is short-circuited to a high potential and the collector current I _C of the PNP transistor 34 reaches the current value of I _cshort , the above-mentioned expression (8) is established. NPN transistor 35 is turned on,
When the collector current I _C35 flows through the NPN transistor 35, the PNP
The transistors 27 and 28 have the collector current T
_A collector current equal to _C35 flows, and V _BE11 of the current source PNP transistor 19 rises by the potential shown by the following equation.

ΔV _BE11 = R ₁₈ · I _C35 (11) In the above equation, R ₁₈ is the resistance value of the resistor 18. As a result, the collector current of the current source PNP transistor 18 is reduced, so that the current flowing in the differential amplifier circuit 15 is also reduced.
This is the same as the case of the first embodiment, and the PN
The output current of the P transistor 34 is prevented from being increased and destroyed. Also, the maximum value V of the output voltage V _O
The value of _OMAX is also equal to that of the first embodiment shown in FIG.

[0025]

As described above, the present invention eliminates the limitation of the lower limit of the output voltage by the short-circuit protection circuit corresponding to the high potential, and has the effect of eliminating the reduction of the amplification dynamic range.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 15, 40 Differential amplifier circuit 2, 37, 50 Gain circuit 3, 38, 56 Capacitor for phase compensation 4, 26, 57 Output circuit 5, 29, 53, 58 Current source 6, 7, 30, 31, 59 , 60 Diodes 8, 10, 19-21, 27, 28, 32, 34, 43
~ 45, 61, 63, 65 PNP transistors 9, 11, 22, 23, 33, 35, 46, 47, 5
1, 52, 62, 66, 67 NPN transistors 12, 17, 18, 24, 25, 36, 42, 48, 4
9, 54, 55, 64 resistor 13, 39, 68 load resistor 16, 41 bias circuit

Claims (2)

(57) [Claims] 1. A differential amplifier circuit forming an input stage, an amplifier circuit for amplifying and outputting a signal output from the differential amplifier circuit, and receiving a signal output from the amplifier circuit,
An output circuit for outputting to a predetermined load circuit, the output circuit comprising: a first NPN transistor having a collector connected to a higher power supply and an emitter connected to an output terminal connected to the load circuit; An emitter is connected to the output terminal, a collector is connected to a lower power supply via a predetermined resistor, and a first PNP transistor functioning as an output transistor; A current source inserted between the base and the base of the first NPN transistor and the first PPN transistor;
A diode connected in a forward state between the base of the NP transistor, an emitter connected to the base of the first PNP transistor, and a base connected to an output terminal of the amplifier circuit;
A second PNP transistor having a collector connected to the lower power supply; a collector connected to the output terminal of the differential amplifier circuit; a base connected to the collector of the first PNP transistor; Second NPN connected to
An op-amp, comprising: a transistor; 2. A differential amplifier circuit forming an input stage, an amplifier circuit for amplifying and outputting a signal output from the differential amplifier circuit, and receiving a signal output from the amplifier circuit,
An output circuit for outputting to a predetermined load circuit, wherein the differential amplifier circuit has a first P-type transistor having an emitter connected to a higher power supply via a first resistor and functioning as a current source.
An NP transistor, a bias supply circuit connected to the base of the first PNP transistor via a second resistor, and supplying a bias voltage to the base of the first PNP transistor; The second and third Ps are connected in common to the collectors of the transistors, and the bases are respectively connected to the inverting input terminal and the non-inverting input terminal to form a pair of amplifier circuit elements in the differential amplifier circuit.
An NP transistor, a first NPN transistor having both a collector and a base connected to the collector of the second PNP transistor and an emitter connected to a lower power supply via a third resistor, and a collector connected to the third PNP transistor. A second NPN transistor connected to a collector of the PNP transistor, a base connected to a base of the first NPN transistor, and an emitter connected to a lower power supply via a fourth resistor; A connection point between a collector of a third PNP transistor and a collector of the second NPN transistor is configured as an output point of the differential amplifier circuit. The output circuit has an emitter connected to a higher power supply, and a collector connected to the second power supply. A fourth PNP transistor connected to the base of one PNP transistor, and an emitter connected to the higher power supply Is continued, the base and collector connected to the base of the fourth PNP transistor,
A fifth PNP transistor forming a current mirror circuit together with the fourth PNP transistor; a third NPN transistor having a collector connected to the higher power supply and an emitter connected to an output terminal connected to the load circuit; A sixth PNP transistor having an emitter connected to the output terminal, a collector connected to the lower power supply via a fifth resistor via a resistor, and functioning as an output transistor; a sixth PNP transistor functioning as a higher power supply and the third NPN transistor; A current source inserted between the base and the base of the third NPN transistor;
A diode connected in a forward state between the base of the NP transistor, an emitter connected to the base of the sixth PNP transistor, and a base connected to an output terminal of the amplifier circuit;
A seventh PNP transistor having a collector connected to the lower power supply; a collector connected to the bases of the fourth and fifth PNP transistors; a base connected to the collector of the sixth PNP transistor; And a fourth NPN transistor connected to the lower power supply.