JPH0630440B2 - Semiconductor switch - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switch, and more particularly to a semiconductor switch suitable for opening / closing control of a circuit handling an AC signal.

[Background of the Invention]

Generally, a thyristor, a transistor or the like is used as a semiconductor switch for controlling the opening / closing (ON / OFF) of the circuit. In this case, a control current for operating the thyristor or the transistor flows out to the circuit. The outflow of the control current may cause a problem in the circuit operation. In such a case, a voltage control type semiconductor switch is used.

As the simplest configuration of the voltage control type semiconductor switch, it can be considered to use a single field effect transistor (hereinafter abbreviated as MOS transistor), but normally the control voltage is a low voltage such as TTL level and the load current of the MOS transistor. Is not suitable for a circuit in which a relatively large amount of current flows.

As a means for improving the current driving capability, there is a configuration in which a MOS transistor and a bipolar transistor are combined. As an example of this, a combination of an N-channel type MOS transistor and an NPN transistor is shown in FIG. 5 (JP-A-55-154826).

In FIG. 5, N-channel type MOS transistor M ₁
Is connected to the collector terminal 1 and the base terminal 4 of the NPN transistor B ₁ , respectively, and the substrate (region) of the MOS transistor M ₁ is connected to the source. In addition, the base terminal 4 of the bipolar transistor B ₁ ,
The resistor R ₁ is connected between the emitter terminals 2. Resistance R
_The numeral ₁ is provided for stabilizing the operation of the bipolar transistor B ₁ and ensuring the withstand voltage reliability.

The gate terminal 3 of the MOS transistor M ₁ is connected to the source (B ₁
If a bias of more than the threshold voltage (hereinafter referred to as V _TH ) of the MOS transistor M ₁ is applied to the terminal 4 of the
The S transistor M ₁ is turned on, and a current flows from the terminal 1 to the terminal 2 through the MOS transistor M ₁ → the resistor R ₁ (provided that the terminal 1 is biased at a higher potential than the terminal 2). At this time, if the potential drop across the resistor R ₁ is larger than the base-emitter building voltage of the bipolar transistor B ₁ (hereinafter referred to as V _BE ), the bipolar transistor B ₁ is turned on. That is, only the MOS transistor M ₁ operates in the small current region where the potential drop in the resistor R ₁ becomes V _BE or less, and both transistors M ₁ and B ₁ simultaneously operate in the large current region. ing.

Now, consider application of the above semiconductor switch to an AC circuit. In order to pass an AC signal, it must be possible to pass current in both directions from terminal 1 to terminal 2 and from terminal 2 to terminal 1. Further, in the OFF state, the withstand voltage in both directions is required. A circuit devised by the inventors in order to satisfy the above is shown in FIG.

In FIG. 6, N-channel type MOS transistor M ₁
Are connected to the collector terminal 1 and the base terminal 4 of each NPN bipolar transistor B ₁ , and the substrate (region) of the MOS transistor M ₁ is connected to the source. The anode of the diode D ₁ is connected to the emitter of the bipolar transistor B ₁ , and the cathode of the diode D ₁ is connected to the terminal 2. A resistor R ₁ is connected between the anode of the diode D ₁ and the base of the bipolar transistor B ₁ . The base of the NPN transistor B ₂ is the bipolar transistor B ₁
Connected to the base terminal 4 of the N-channel MOS transistor M _{2 and} the drain and source of the N-channel MOS transistor M ₂ are respectively the collector terminal 2 and the base terminal 4 of the NPN bipolar transistor B _2.
And the substrate (region) of the MOS transistor M ₁ is connected to the source. Bipolar transistor B ₂
The anode of the diode D ₂ is connected to the emitter of
The cathode of the diode D ₂ is connected to the terminal 1.
A resistor R ₂ is connected between the anode of the diode D ₂ and the base of the bipolar transistor B ₂ .

The circuit shown in FIG. 6 includes diodes D ₁ and D ₂ on the emitter side of the bipolar transistor of the semiconductor switch shown in FIG.
Is inserted in series and connected in anti-parallel,
This diode has the potential of terminal 2 at terminal 1 in FIG.
When it becomes higher, the resistance R ₁ → MOS transistor M
It is intended to prevent current flowing _first substrate (region) → MOS transistor M ₁ drain or the resistor R ₁ → bipolar transistor B ₁ based → in path of the collector of the bipolar transistor B _1, circuit breakdown voltage diode It is determined by the breakdown voltage of D ₁ and D ₂ .

External output terminals (hereinafter abbreviated as terminals) 1 and 2 in FIG.
Consider the operation when an AC signal is applied during.
The ON state of the semiconductor switch in FIG. 6 is M as in the case of FIG.
The gate terminals 3 of the OS transistors M ₁ and M ₂ may be biased with respect to the source terminal 4 to V _TH or more. At this time the MOS transistor _{M 1} or _{M 2} is ON and the resistor _{R 1} or _{R 2} to the potential drop in the flow of communication flow resistance _{R 1} or _{R 2} is bipolar transistor _{B 1} or _{B 2} becomes equal to or greater than V _BE is ON Univ Enables current drive.

When an AC voltage that rises (or falls) from 0 V is applied between the terminals 1 and 2 while the semiconductor switch is ON-driven, the terminals 1 and 2 due to the diodes D ₁ and D ₂ .
The potential difference between the _{two is} the forward voltage of the diodes D ₁ and D ₂ (hereinafter V
_The semiconductor switch cannot be turned on unless it is more than _FD . This state is shown in FIG.

In FIG. 7, the horizontal axis represents the potential of terminal 1 (or 2) with respect to terminal 2 (or 1), and the vertical axis represents the current flowing between terminals 1 and 2. Point A in the figure is the voltage at which the diode D ₁ or D ₂ in FIG. 6 is turned on, that is, V _FD . When the voltage is lower than the point A, the semiconductor switch maintains the OFF state even though it is driven ON. When the potential difference between the terminals 1 and 2 becomes larger than V _FD , the diode D ₁ or D ₂ becomes O.
A current starts to flow through the MOS transistor M ₁ or M ₂ and the resistor R ₁ or R ₂ . When the potential difference further increases, the current flowing through the resistor R ₁ or R ₂ increases,
There potential drop in the bipolar transistor _{B 1} or _{B 2} at the time point when the bipolar transistor _{B 1} or _{B 2} of V _BE above is turned ON. It is point B in the figure at this point. Therefore, point B becomes V _FD + V _BE . The slope of the characteristic graph from the point A to the point B is the MOS transistor M ₁ or M
It is determined by the ON resistance of ₂ and the resistance R ₁ or R ₂ . The characteristics after point B depend on the bipolar transistor B ₁ or B ₂ .

When an AC signal is applied to the semiconductor switch of FIG. 6 having the above characteristics, the AC signal passing through the semiconductor switch is V
There is a problem that components below _FD are cut and distortion, so-called distortion occurs. This is due to the diodes D ₁ and D ₂ in FIG.

Therefore, a circuit excluding the diodes D ₁ and D ₂ is shown in FIG. In the semiconductor switch of FIG. 8, since the diodes D ₁ and D ₂ are not provided, when the reverse voltage (direction from the emitter to the collector) is applied to the bipolar transistor B ₁ or B ₂ , the resistances R ₁ and R in FIG. _{If 2} is included, a current will flow to the external output terminal on the opposite side through this resistor, so it is omitted in FIG.

In FIG. 8, N-channel type MOS transistor M ₁
Drain and source of the NPN bipolar transistor B ₁ are respectively connected to the collector and the base of the NPN bipolar transistor B ₁ , and the collector and the emitter of the bipolar transistor B ₁ are connected to the external output terminals 1 and 2, respectively.
The drain and source of the transistor M ₂ are connected to the collector and base of the NPN bipolar transistor B ₂ , respectively, and the collector and base of the bipolar transistor B ₂ are connected to the external output terminals 1 and 2, respectively. Also M
Gates and sources of the OS transistors M ₁ and M ₂ are commonly connected to input terminals (hereinafter abbreviated as terminals) 3 and 4, respectively.

When the semiconductor switch of FIG. 8 is turned on, the MOS transistor M is connected between the terminals 3 and 4 as in the case of FIGS.
Bias above V _{TH of 1} and M ₂ . At this time, the MOS
Transistors _M 1, _{M 2} since although ON entering the base of the current bipolar transistor _{B 1} or _{B 2} flowing them, MOS transistors _M 1, bipolar transistor _{B 1} are connected in series to the source of _{M 2} or _{B 2} Will flow through the diode formed by the base and emitter of the. Therefore, the semiconductor switch shown in FIG. 8 cannot be turned on unless the potential difference between the terminals 1 and 2 becomes not less than V _{BE of the} bipolar transistor B ₁ or B ₂ . Therefore, the current-voltage characteristics are almost the same as in FIG. 7, and the distortion of the AC signal is generated as in the case of FIG. Further, in FIG. 8, the withstand voltage is determined by the emitter-base voltage V _EB0 of the bipolar transistors B ₁ and B ₂ , and cannot be increased so much.

[Object of the Invention]

An object of the present invention is to provide a semiconductor switch capable of preventing distortion of an AC signal and capable of driving a large current with a high breakdown voltage.

[Outline of Invention]

A feature of the present invention that achieves the above object is that a first field effect transistor whose source is connected to a substrate region is connected in parallel with either a bipolar transistor or a thyristor, and one of the bipolar transistor and the thyristor is connected. A pair of second field effect transistors whose source is connected to the substrate region is connected between the main terminal and the control terminal of the bipolar transistor and the thyristor so as to be in anti-series. One of the main terminals of the transistor and the thyristor is used as an external output terminal, and the first and second
The gate of the field effect transistor and the other main terminal of each of the bipolar transistor and the thyristor are used as external input terminals.

Example of Invention

 A first embodiment of the present invention is shown in FIG.

In FIG. 1, an external output terminal (hereinafter abbreviated as terminal) 1 has an N-channel MOS field effect transistor (hereinafter referred to as M
Abbreviated as OS transistor) drains of M ₁₁ and M ₁₂ , and N
The collectors of the PN bipolar transistors B ₁ are commonly connected, the source of the MOS transistor M ₁₁ is connected to the base of the bipolar transistor B ₁ , and the source of the MOS transistor M ₁₂ is connected to the emitter of the bipolar transistor B ₁ . A resistor R ₁ is connected between the base and emitter of the bipolar transistor B ₁ . Similarly, the drains of the N-channel MOS field effect transistors (hereinafter abbreviated as MOS transistors) M ₂₁ and M ₂₂ and the collector of the NPN bipolar transistor ₂ are commonly connected to the output external terminal (hereinafter abbreviated as terminal) 2.
The sources of the S transistors M ₂₁ and M ₂₂ are connected to the base and emitter of the bipolar transistor B ₂ , respectively. The between the base and emitter of the bipolar transistor B ₂ bipolar transistor B ₁ same resistance R ₂ is connected. The emitters of the bipolar transistors B ₁ and B ₂ and the sources of the MOS transistors M ₂₁ and M ₂₂ are commonly connected to an external input terminal (hereinafter abbreviated as terminal) 4,
Gates of the OS transistors M ₁₁ , M ₁₂ , M ₂₁ , and M ₂₂ are commonly connected to an external input terminal (hereinafter abbreviated as a terminal) 3. Further, the MOS transistors M ₁₁ , M ₁₂ , M ₂₁ , M
_In all _22, the substrate area is connected to the source.

When turning on this semiconductor switch, connect terminal 3 to terminal 4.
With respect to the positive potential direction. As for the MOS transistors M ₁₂ and M ₂₂ , it can be turned on when the terminal 3 becomes higher than the threshold voltage (hereinafter V _TH ) with respect to the terminal 4. However, regarding the MOS transistors M ₁₁ and M ₁₂ , each source has a bipolar transistor B.
_Since the bases of ₁ and B ₂ are connected and the terminal 4 is connected to the emitters of the bipolar transistors ₁ and B ₂ , it is necessary to turn ON the bipolar transistors B ₁ or M ₂₁ and B _{2 of} the MOS transistor M _{11 at} the same time. Terminal 3 must be biased with respect to terminal 4 above V _th + V _BE . Where V _BE is a bipolar transistor B
₁ and B ₂ are building voltages between the base and the emitter.

When an AC voltage that rises (or falls) from 0 V is applied between terminals 1 and 2 while a voltage of V _th + V _BE or more sufficient to turn on the semiconductor switch is applied between terminals 3 and 4. FIG. 2 shows the current-voltage characteristics of the above. In FIG. 2, the horizontal axis represents the potential of terminal 1 (or 2) with respect to terminal 2 (or 1), and the vertical axis represents the current flowing between terminals 1 and 2.

Although FIG. 2 has an inflection point A, the MOS transistors M ₁₂ and M ₂₂ in FIG. 1 operate in the potential region below this point A. This will be described with reference to FIGS. 3 and 4.

FIG. 3 shows the MOS transistors M ₁₂ , M _{22 in} FIG.
The drains of the MOS transistors M ₁₂ and M ₂₂ are connected to terminals 1 and 2, respectively, and
The gates and sources of the OS transistors M ₁₂ , M ₂₂ are connected to the terminals 3 and 4, respectively, and the two MOS transistors M ₁₂ , M ₂₂ are connected in anti-series.
The substrate regions of both MOS transistors M ₁₂ and M ₂₂ are connected to the sources.

FIG. 4 is a sectional view of a semiconductor substrate when the circuit of FIG. 3 is manufactured as a semiconductor switch.

In FIG. 4, 7 and 8 are MOS transistors M ₁₂ , M
₂₂ drains, 9 and 10 sources, 5 and 6 gates, 1
Reference numerals 1 and 12 are P-type substrate regions.

With the terminals 3 and 4 biased to V _th or more and the MOS transistors M ₁₂ and M ₂₂ being ON-driven,
The operation when the potential difference between the two exceeds 0 V will be described below.

Now, consider the case where the potential of the terminal 1 rises from 0 V to the positive side with respect to the terminal 2. At this time, the MOS transistor M ₁₂ ,
Since the gate-source of M ₂₂ is biased to V _th or more, both MOS transistors M ₁₂ and M ₂₂ are in the ON state, and a current flows through MOS transistors M ₁₂ and M ₂₂ as the potential of terminal 1 rises. start. This is the region from 0 V to point A in FIG. 2, and the slope of the current-voltage is MO
It is determined by the ON resistance of the S transistors M ₁₂ and M ₂₂ . When the potential of the terminal 1 further rises, the source-drain voltage (hereinafter referred to as V _DS ) of the MOS transistors M ₁₂ and M ₂₂ increases as the current increases. Where each M
Since the substrate regions of the OS transistors M ₁₂ and M ₂₂ are connected to the sources, a diode is formed in parallel with the source / drain as shown in FIG.
The anodes of the 1 and 12 diodes and the drains 7 and 8 are the cathodes. Therefore, V of MOS transistor M ₂₂
Forward voltage of the diode (hereinafter referred to as V _FD ) increases due to increase in _DS
When it is above, this diode works and it looks like MO
The on resistance of the S transistor M ₂₂ is reduced. This is the inflection point A in FIG. At this time, since the currents flowing through the MOS transistors M ₁₂ and M ₂₂ are the same, the V _{DS of the} MOS transistor M ₁₂ is about the same as that of the MOS transistor M _22. Therefore, the output terminal potential at the inflection point A is shown in FIG. Is 2 × V _FD . Although the case where the potential of the terminal 1 rises positively with respect to the output terminal 2 has been considered above, the MOS transistors M ₁₂ and M ₂₂ are configured symmetrically even when a reverse voltage is applied. It becomes the operation of. However, in that case, the built-in diode on the MOS transistor M ₁₂ side operates.

Next, the area after point A in FIG. 2 will be described.

In FIG. ₁ , when the building voltage between the base and emitter of the bipolar transistors B ₁ and B ₂ is V _BE , the bipolar transistors B ₁ and B ₂ are turned on as described with reference to FIGS. 5 and 6. For that collector
The emitter-to-emitter voltage must be V _BE or higher. Now V
_{If BE} ≈ V _FD (forward voltage of the built-in diode formed between the substrate region and the drain of the MOS transistor M ₁₂ or M ₂₂ ), at point A in FIG.
_12, M ₂₂ are both between for the collector and emitter of the bipolar transistor B ₁ or B ₂ is decreased to V _FD is also biased to V _FD, bipolar transistor B ₁ or B ₂ becomes operable. Therefore, after the point A in FIG. 2, the bipolar transistor B ₁ and the MOS transistor M ₁₂ , or B
₂ and M ₂₂ are ON at the same time. Since the bipolar transistors B ₁ and B ₂ have a larger current driving capability than the MOS transistors M ₁₂ and M ₂₂ , the characteristics after the point A are almost determined by the bipolar transistor B ₁ or B ₂ . In the above region, the bipolar transistor B ₁ and the MOS
MOS transistor M when transistor M ₁₂ is ON
_{When 22} or B ₂ and M ₂₂ are ON, a current flows through the built-in diode of M ₁₂ .

As described above, according to the first embodiment of the present invention, as shown in FIG. 2, the current can flow even when the applied voltage is near 0V, so that the distortion is prevented even for the AC signal passing through 0V. It is possible to drive a large current because it has a built-in bipolar transistor.

Now, the transistors B ₁ , B ₂ , M ₁₁ , M ₁₂ , M ₂₁ ,
Regarding prevention of the voltage of M ₂₂ , the bipolar transistors B ₁ and B ₂ have a high breakdown voltage between the collector and the base and a low breakdown voltage between the base and the emitter. The MOS transistors M ₁₁ , M ₁₂ , M ₂₁ , and M ₂₂ have a high breakdown voltage between the substrate region and the drain, but no breakdown voltage between the substrate region and the source.

Here, when there is no input between the terminals 3 and 4 and a voltage with which the terminal 1 is positive is applied to the terminal 2, most of the voltage is applied to the bipolar transistor B ₁ and the MOS transistor M.
₁₁ and M ₁₂ will be paid. Further, when a voltage that makes the terminal 2 positive is applied to the terminal 1, the bipolar transistor B ₂
The MOS transistors M ₂₁ and M ₂₂ bear most of the voltage, and a high voltage can be maintained regardless of whether the voltage is applied to the terminals 1 or 2. The characteristic when there is no input between terminals 3 and 4 is shown by the dotted line in FIG. The inflection point B that causes breakdown is determined by the avalanche voltage of any one of the bipolar transistors B ₁ and B ₂ and the MOS transistors M ₁₁ , M ₁₂ , M ₂₁ and M ₂₂ .

FIG. 9 shows a second embodiment of the present invention.

In this embodiment, the bipolar transistors B ₁ and B ₂ in the first embodiment are replaced with thyristors S ₁ and S ₂ ,
This is a further improvement of the large current drive capability. In FIG. 9, the drains of the MOS transistors M ₁₁ and M ₁₂ and the anode of the thyristor S ₁ are commonly connected to the terminal 1, and the source of the MOS transistor M ₁₁ is the thyristor S _1.
A cathode gate (hereinafter gates hereinafter), the source of the MOS transistor M ₁₂ is connected to the cathode of the thyristor S _11. A resistor R ₁ is connected between the gate and cathode of the thyristor S ₁ . Similarly, M at terminal 2
OS transistor M _21, the anode of the drain and thyristor S ₂ of M ₂₂ are commonly connected, the sources of the MOS transistors M ₂₁ and M ₂₂ are connected to each gate of the thyristor S _2, the cathode. A resistor R ₂ is connected between the gate and cathode of the thyristor S ₂ , like the thyristor S ₁ . The cathodes of the thyristors S ₁ and S ₂ and the sources of the MOS transistors M ₁₂ and M ₂₂ are commonly connected to the terminal 4, and the MOS transistors M ₁₁ , M ₁₂ , M ₂₁ and M ₂₂ are connected.
The gates of ₂₂ are commonly connected to terminal 3. Also above M
The substrate regions of all the OS transistors M ₁₁ , M ₁₂ , M ₂₁ , and M ₂₂ are connected to their sources.

The embodiment shown in FIG. 9 improves the current driving capability by using the thyristor as described above. Its operation and characteristics are the same as those in the case of FIG. 1, and the same effect can be obtained.
However, since a thyristor is used, turning off the semiconductor switch requires that the applied voltage be 0 V or the thyristor S ₁ , S ₂
By reverse-biasing the thyristors S ₁ and S _{2 so} that the current flowing through the thyristors S ₁ and S ₂ is equal to or less than the holding current of the thyristors S ₁ and S ₂ .

〔The invention's effect〕

According to the present invention, even a minute signal near 0 V can be passed, distortion of an AC signal can be prevented, and a large drive current can be obtained by incorporating a bipolar element transistor or a thyristor.
A high voltage semiconductor switch can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor switch of the present invention, FIG. 2 is a characteristic diagram of the semiconductor switch of FIG. 1, and FIG. 3 is a circuit diagram showing a part of the semiconductor switch of FIG.
FIG. 4 is a schematic sectional view of a semiconductor substrate when the circuit of FIG. 3 is embodied, FIGS. 5 and 6 are circuit diagrams of a conventional semiconductor switch, and FIG. 7 is a characteristic of the semiconductor switch of FIG. Figure, 8th
FIG. 9 is a circuit diagram of another conventional semiconductor switch, and FIG. 9 is a circuit diagram showing another embodiment of the present invention. 1 to 4 ... terminals, B ₁ , B ₂ ... bipolar transistors, M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ ... MOS transistors,
S ₁ , S ₂ ... Thyristor, R ₁ , R ₂ ... Resistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadaaki Kariya 3-1-1, Saiwaicho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi factory (72) Inventor Eitoshi Okubo 3-chome, Saiwaicho, Hitachi, Ibaraki No. 1 Hitachi Ltd., Hitachi Works (72) Inventor Koji Kawamoto 3-1-1, Saiwaicho, Hitachi City, Ibaraki Hitachi Ltd. (72) Inventor, Shigeru Aoki Shigeru Aoki, Ibaraki Prefecture 3-1-1, Machi, Hitachi Ltd. Hitachi factory

Claims (1)

[Claims] 1. A first field effect transistor whose source is connected to a substrate region is connected in parallel with a bipolar transistor or thyristor, and the source is the substrate between the collector and base of the bipolar transistor or between the anode and gate of the thyristor. A second field effect transistor connected to the region is connected, and a resistor is connected between the base and the emitter of the bipolar transistor or between the gate and the cathode of the thyristor. And the collector of each bipolar transistor or the anode of each thyristor connected in anti-series is used as an external output terminal, and the gates of the first and second field effect transistors and the emitter of each bipolar transistor or the cathode of each thyristor are connected. External input Semiconductor switches, characterized in that a child.