JPH0630410B2 - Signal processing circuit device - Google Patents

Signal processing circuit device

Info

Publication number
JPH0630410B2
JPH0630410B2 JP59099214A JP9921484A JPH0630410B2 JP H0630410 B2 JPH0630410 B2 JP H0630410B2 JP 59099214 A JP59099214 A JP 59099214A JP 9921484 A JP9921484 A JP 9921484A JP H0630410 B2 JPH0630410 B2 JP H0630410B2
Authority
JP
Japan
Prior art keywords
attenuator
signal
output
transistor
processing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59099214A
Other languages
Japanese (ja)
Other versions
JPS60240202A (en
Inventor
弘光 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59099214A priority Critical patent/JPH0630410B2/en
Publication of JPS60240202A publication Critical patent/JPS60240202A/en
Publication of JPH0630410B2 publication Critical patent/JPH0630410B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00Demodulation of angle-, frequency- or phase- modulated oscillations

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Circuits Of Receivers In General (AREA)
  • Stereo-Broadcasting Methods (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、テレビジョン受像機等の信号処理回路に関
し、特にその音声FM検波器と減衰器の間の接続を改良
し、少ない素子と端子数で、音声直接出力端子をもった
音声回路を構成できるようにした信号処理回路装置に関
する。
Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a signal processing circuit for a television receiver or the like, and more particularly, by improving the connection between an audio FM detector and an attenuator to reduce the number of elements and the number of terminals. Then, the present invention relates to a signal processing circuit device capable of forming an audio circuit having an audio direct output terminal.

〔従来技術〕[Prior art]

従来、この主の信号処理回路装置例えば集積回路として
の信号処理回路装置として第1図及び第2図に示すもの
があった。第1図において、1はFM音声信号を検波す
るFM検波器、RLは負荷抵抗、DOは音声直接出力端
子、Cは外付けコンデンサ、AIは減衰器入力端子、R
1,R2は抵抗、D1はダイオード、2は減衰器であ
り、該減衰器2において、Q1,Q2、Q3はトランジ
スタ、R3は抵抗、V1は参照電圧源(定電圧源)、Z
は出力手段、Oは出力端子、Vcc電源端子、GNDは
接地端子、VCは音量制御端子、Vcは音量調整用の制
御電源(可変直流電圧源)である。また第2図におい
て、D2はダイオード、Q4はトランジスタである。な
お音声直接出力端子DOはFM検波器1の出力を直接外
部に出力するためのもので、テレビジョン音声の録音等
に利用される。また、図示から明らかな如く、第1図に
示したものにおいて、実線の枠にて囲まれた中にあるF
M検波器1、減衰器2、負荷抵抗RL、抵抗R1、R2
及びダイオードD1は、例えば、集積回路として形成さ
れているものであり、第2図に示したものにおいて、実
線の枠にて囲まれた中にあるFM検波器1、減衰器2、
負荷抵抗RL、抵抗R2、ダイオードD1、D2及びト
ランジスタQ4は、例えば、集積回路として形成されて
いるものである。
Conventionally, as the main signal processing circuit device, for example, a signal processing circuit device as an integrated circuit, there is one shown in FIGS. 1 and 2. In FIG. 1, 1 is an FM detector for detecting an FM audio signal, RL is a load resistance, DO is an audio direct output terminal, C is an external capacitor, AI is an attenuator input terminal, R
1, R2 is a resistor, D1 is a diode, 2 is an attenuator, and in the attenuator 2, Q1, Q2 and Q3 are transistors, R3 is a resistor, V1 is a reference voltage source (constant voltage source), Z
Is an output means, O is an output terminal, Vcc power supply terminal, GND is a ground terminal, VC is a volume control terminal, and Vc is a control power source (variable DC voltage source) for volume adjustment. Further, in FIG. 2, D2 is a diode and Q4 is a transistor. The audio direct output terminal DO is for directly outputting the output of the FM detector 1 to the outside, and is used for recording television sound and the like. Further, as is apparent from the drawing, in the structure shown in FIG. 1, the F inside the frame surrounded by the solid line is shown.
M detector 1, attenuator 2, load resistor RL, resistors R1, R2
The diode D1 and the diode D1 are formed, for example, as an integrated circuit, and in the structure shown in FIG. 2, the FM detector 1, the attenuator 2, and the
The load resistor RL, the resistor R2, the diodes D1 and D2, and the transistor Q4 are formed, for example, as an integrated circuit.

次に第1図の回路動作について説明する。FM検波器1
の検波動作により負荷抵抗RLより電流がひき込まれ、
該負荷抵抗RLの両端に音声信号が発生する。この音声
信号は音声直接出力端子DO,外付けコンデンサC,減
衰器入力端子AIを介して抵抗R1,ダイオードD1の
接続点に入力され、この音声信号は該抵抗R1,R2及
びダイオードD1により直接電流に重畳されて減衰器2
に入力される。
Next, the circuit operation of FIG. 1 will be described. FM detector 1
The current is drawn from the load resistance RL by the detection operation of
A voice signal is generated across the load resistor RL. This audio signal is input to the connection point of the resistor R1 and the diode D1 via the audio direct output terminal DO, the external capacitor C, and the attenuator input terminal AI, and this audio signal is directly supplied to the current by the resistors R1 and R2 and the diode D1. Attenuator 2 superimposed on
Entered in.

減衰器2のトランジスタQ3のコレクタ電流は上記端子
AIより入力された音声信号に応じて変化し、該電流が
トランジスタQ1,Q2に両トランジスタQ1,Q2の
ベース電圧に応じて分配される。ここで出力端子Oのボ
リウムを上げたい時は制御電源Vc電圧を参照電圧V1
よりも大きくすればよく、逆にボリウムを下げたい時は
制御電源Vc電圧を参照電源V1よりも小さくすればよ
い。
The collector current of the transistor Q3 of the attenuator 2 changes according to the audio signal input from the terminal AI, and the current is distributed to the transistors Q1 and Q2 according to the base voltage of both transistors Q1 and Q2. Here, when it is desired to raise the volume of the output terminal O, the control power supply Vc voltage is set to the reference voltage V1.
The control power supply Vc voltage may be set lower than the reference power supply V1 to lower the volume.

次に第2図の回路動作について説明する。第1図同様、
FM検波器1の検波動作によりダイオードD2より電流
がひき込まれ、その両端に音声信号が発生する。この音
声信号はダイオードD2とトランジスタQ4によりカレ
ントミラーにより負荷抵抗RL,ダイオードD1,抵抗
R2を流れ、該抵抗RL,R2およびダイオードD1に
よりDCバイアスされて音声直接出力端子DOより出力
されるとともにダイオードD1とトランジスタQ3とか
らなるカレントミラーにより減衰器2に入力される。
Next, the circuit operation of FIG. 2 will be described. Similar to Figure 1.
A current is drawn from the diode D2 by the detection operation of the FM detector 1, and a voice signal is generated at both ends thereof. This audio signal flows through the load resistor RL, the diode D1, and the resistor R2 by the current mirror by the diode D2 and the transistor Q4, is DC biased by the resistors RL, R2, and the diode D1, and is output from the audio direct output terminal DO and the diode D1. Is input to the attenuator 2 by a current mirror including a transistor Q3.

従来の信号処理回路装置は以上のように構成されてお
り、第1図の従来例ではFM検波器1の出力DC電圧と
減衰器2の入力バイアスが異なるため、外部で容量結合
しなければならず、そのため2つの外部接続端子DO,
AIが必要となる。また電源が変動した場合、負荷抵抗
RLとGND間に変動電圧が生じその電圧が減衰器2を
通って出力端子Oに出力されてしまう欠点がある。
The conventional signal processing circuit device is configured as described above. In the conventional example shown in FIG. 1, since the output DC voltage of the FM detector 1 and the input bias of the attenuator 2 are different from each other, capacitive coupling must be performed externally. Therefore, two external connection terminals DO,
AI is required. Further, when the power supply fluctuates, a fluctuating voltage is generated between the load resistance RL and the GND, and the voltage is output to the output terminal O through the attenuator 2.

また第2図の従来例では、ダイオードD2とトランジス
タQ4でFM検波器1の出力電流をカレントミラーによ
り負荷抵抗RLとダイオードD1,抵抗R2に流すの
で、電源電圧変動が直接出力端子DOに生じないが、し
かしながら、音声直接出力を十分大きな振巾で取出そう
とするとDC電圧が上ってしまい、ダイナミックレンジ
がとれなくなるという欠点がある。
Further, in the conventional example of FIG. 2, the output current of the FM detector 1 is passed through the load resistor RL and the diodes D1 and R2 by the current mirror by the diode D2 and the transistor Q4, so that the power supply voltage does not directly change at the output terminal DO. However, there is a drawback in that if a direct sound output is taken out with a sufficiently large amplitude, the DC voltage rises and the dynamic range cannot be obtained.

〔発明の概要〕[Outline of Invention]

この発明は、上記のような従来の欠点を除去するために
なされたもので、FM検波器の差動出力電流の交流電流
のみを抵抗に流し音声直接出力をとり出すとともに、そ
の抵抗を減衰器を構成する差動アンプの共通エミッタに
接続することにより、簡単な回路構成でダイナミックレ
ンジが広くしかも電源電圧変動の影響を受けにくい音声
直接出力が得られる信号処理回路装置を提供することを
目的としている。
The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, in which only the alternating current of the differential output current of the FM detector is passed through the resistor to directly output the voice and the resistor is also used as the attenuator. For the purpose of providing a signal processing circuit device capable of obtaining a direct audio output having a wide dynamic range with a simple circuit configuration and being hardly affected by power supply voltage fluctuations, by connecting to the common emitter of the differential amplifier constituting There is.

〔発明の実施例〕Example of Invention

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第3図は本発明の一実施例による信号処理回路装置例え
ば集積回路としての信号処理回路装置を示す。図におい
て、第1,2図と同一符号は同一のものを示す。本実施
例回路において、FM検波器1の差動出力はダイオード
D2,D3のカソードに各々接続される(第3図参照)
とともにトランジスタQ4,Q5のベースに各々接続さ
れている。またダイオードD2,D3のアノード、トラ
ンジスタQ4,Q5のエミッタは電源に接続され、Q5
のコレクタはダイオードD4とトランジスタQ6のベー
スに接続され、Q4のコレクタはQ6のコレクタと抵抗
RLと音声直接出力端子DOに接続され、更に、ダイオ
ードD4のカソードとトランジスタQ6のエミッタは接
地端子GNDに接続される。そして上記ダイオードD2
〜D4,トランジスタQ4〜Q6により減算手段3が構
成されている。
FIG. 3 shows a signal processing circuit device according to an embodiment of the present invention, for example, a signal processing circuit device as an integrated circuit. In the figure, the same reference numerals as those in FIGS. In the circuit of this embodiment, the differential output of the FM detector 1 is connected to the cathodes of the diodes D2 and D3 (see FIG. 3).
Together, they are connected to the bases of the transistors Q4 and Q5, respectively. The anodes of the diodes D2 and D3 and the emitters of the transistors Q4 and Q5 are connected to the power source, and Q5
Is connected to the diode D4 and the base of the transistor Q6, the collector of Q4 is connected to the collector of Q6, the resistor RL, and the audio direct output terminal DO, and the cathode of the diode D4 and the emitter of the transistor Q6 are connected to the ground terminal GND. Connected. And the diode D2
~ D4, transistors Q4 to Q6 form a subtraction means 3.

またトランジスタQ1のベースは参照電圧源V1に接続
され、取扱いQ2のベースは音量制御入力端子VCを通
して可変直流電圧源Vcに接続され、トランジスタQ1
とQ2のエミッタは共通接続され定電流源Ioと負荷抵
抗RLに接続される。更にトランジスタQ1またはQ2
のコレクタは出力手段(出力負荷)Zに接続され、出力
端子Oより音量制御された音声が出力される。なお、図
示から明らかな如く、実線の枠にて囲まれた中にあるF
M検波器1、減衰器2、減算手段3及び負荷抵抗RL
は、例えば、集積回路として形成されているものであ
る。
Further, the base of the transistor Q1 is connected to the reference voltage source V1, the base of the handle Q2 is connected to the variable DC voltage source Vc through the volume control input terminal VC, and the transistor Q1 is connected.
The emitters of Q2 and Q2 are commonly connected to the constant current source Io and the load resistor RL. Further, the transistor Q1 or Q2
The collector of is connected to the output means (output load) Z, and the sound whose volume is controlled is output from the output terminal O. As is clear from the figure, the F inside the frame surrounded by the solid line
M detector 1, attenuator 2, subtraction means 3 and load resistance RL
Are, for example, formed as an integrated circuit.

次に動作について説明する。Next, the operation will be described.

第4図に示すようにFM検波器1の2つの出力電流とし
てはDCバイアス電流I1に音声信号に相当する振巾Δ
IのAC電流が差動で重畳されたものが出力されてい
る。
As shown in FIG. 4, the two output currents of the FM detector 1 include the DC bias current I1 and the amplitude Δ corresponding to the audio signal.
The AC current of I is superposed differentially and is output.

この2つの出力電流はD3,Q5,D4,Q6で構成さ
れるカレントミラーとD2,Q4で構成されるカレント
ミラーによりDCバイアス電流分I1がキャンセルさ
れ、その結果負荷抵抗RLには2ΔIの交流電流が流れ
る。そして参照電圧V1及び音量制御電圧Vcには交流
分が含まれていないため、音声直接出力端子DOにはト
ランジスタQ1とQ2の共通エミッタ電圧をDCバイア
ス電圧とし、これにRL×2ΔIの交流信号電圧が重畳
した電圧が出力される。
The two output currents are canceled by the current mirror composed of D3, Q5, D4 and Q6 and the current mirror composed of D2 and Q4, and the DC bias current component I1 is canceled. As a result, the load resistor RL has an AC current of 2ΔI. Flows. Since the reference voltage V1 and the volume control voltage Vc do not include an AC component, the sound direct output terminal DO uses the common emitter voltage of the transistors Q1 and Q2 as a DC bias voltage, and an AC signal voltage of RL × 2ΔI. The superimposed voltage is output.

一方、トランジスタQ1とQ2の共通エミッタ点を流れ
る電流は定電流源IoよりのDCバイアス電流Ioと負
荷抵抗RLよりの2ΔIのAC電流の和となり、トラン
ジスタQ1とQ2のベースに加えられるDC電圧の差に
応じて、電流が分配され、トランジスタQ2に分配され
た電流はそのコレクタにつながれた出力手段Zに流れ、
出力端子Oからは音量制御された信号が取出される。
On the other hand, the current flowing through the common emitter point of the transistors Q1 and Q2 is the sum of the DC bias current Io from the constant current source Io and the AC current of 2ΔI from the load resistor RL, and the DC voltage applied to the bases of the transistors Q1 and Q2. According to the difference, the current is distributed, the current distributed to the transistor Q2 flows to the output means Z connected to its collector,
A volume-controlled signal is taken out from the output terminal O.

このように、本実施例の構成では、外部接続端子が少な
くて済む。しかもカレントミラーにより交流信号電流の
差のみをとって抵抗に出力するようにしたので、ダイナ
ミックレンジが広く、電源電圧変動をうけにくい音声直
接出力が得られる効果がある。
As described above, the configuration of the present embodiment requires less external connection terminals. Moreover, since the current mirror is used to output only the difference between the AC signal currents and output to the resistor, there is an effect that a wide dynamic range is provided and a direct audio output that is less susceptible to power supply voltage fluctuations is obtained.

なお第5図に示すように負荷抵抗RLと定電流源Ioの
接続点とトランジスタQ1とQ2の共通エミッタ接続点
の間にベース接地トランジスタQ7を挿入しそのベース
に定電圧源V2をつないでも良い。又、トランジスタQ
7の代わりに、第6図に示すように抵抗R1を挿入して
もよく、上記実施例と同様の効果を奏する。
As shown in FIG. 5, a grounded base transistor Q7 may be inserted between the connection point of the load resistor RL and the constant current source Io and the common emitter connection point of the transistors Q1 and Q2, and the constant voltage source V2 may be connected to the base. . Also, the transistor Q
Instead of 7, a resistor R1 may be inserted as shown in FIG. 6, and the same effect as in the above embodiment can be obtained.

〔発明の効果〕〔The invention's effect〕

本発明は、以上に述べたように、FM検波器及び減衰器
を備えた信号処理回路装置において、FM検波器の差動
出力電流の交流成分のみを抵抗に流して音声直接出力を
とり出すとともに減衰器を構成する差動アンプの共通エ
ミッタに伝達するようにしたので、外部接続端子を極力
少なくして、簡単な回路構成で広い出力ダイナミックレ
ンジをもち、十分大きな出力をとりだすことができ、し
かも電源電圧変動をうけにくい音声直接出力が得られる
信号処理回路装置を構成できる効果がある。
As described above, according to the present invention, in the signal processing circuit device including the FM detector and the attenuator, only the AC component of the differential output current of the FM detector is passed through the resistor to directly output the sound. Since it is transmitted to the common emitter of the differential amplifier that constitutes the attenuator, the number of external connection terminals is reduced as much as possible, the output dynamic range is wide with a simple circuit configuration, and a sufficiently large output can be taken out. There is an effect that it is possible to configure a signal processing circuit device that can obtain a voice direct output that is less susceptible to power supply voltage fluctuations.

【図面の簡単な説明】[Brief description of drawings]

第1図および第2図は従来の信号処理回路の回路図、第
3図は本発明の一実施例による信号処理回路の回路図、
第4図は第3図の各部の波形図、第5図および第6図は
本発明の他の実施例による信号処理回路の回路図であ
る。 図において、1はFM検波器、2は減衰器、3は減算手
段、RLは負荷抵抗、DOは音声直接出力端子、Ioは
定電流源、Q1,Q2,Q7は第1,第2,第3のトラ
ンジスタ、V1,V2は第1,第2の定電圧源、Vcは
可変直流電圧源、Zは出力手段である。 なお図中同一符号は同一又は相当部分を示す。
1 and 2 are circuit diagrams of a conventional signal processing circuit, FIG. 3 is a circuit diagram of a signal processing circuit according to an embodiment of the present invention,
FIG. 4 is a waveform diagram of each part of FIG. 3, and FIGS. 5 and 6 are circuit diagrams of a signal processing circuit according to another embodiment of the present invention. In the figure, 1 is an FM detector, 2 is an attenuator, 3 is subtraction means, RL is a load resistor, DO is a voice direct output terminal, Io is a constant current source, Q1, Q2 and Q7 are first, second and second. 3 is a transistor, V1 and V2 are first and second constant voltage sources, Vc is a variable DC voltage source, and Z is an output means. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】FM音声信号を検波し、音声信号の振幅に
基づいた交流電流を互いに逆極性で直流バイアス電流に
重畳した2つの出力電流を出力するFM検波器、 上記FM検波器からの2つの出力電流を受け、これら2
つの出力電流を減算して直流バイアス電流がキャンセル
された信号電流を出力ノードに出力するための減算手
段、 この減算手段の出力ノードに接続され、音声信号を外部
へ出力するための音声直接出力端子、 ベースに参照電圧が印加される第1のトランジスタと、
この第1のトランジスタのエミッタにエミッタが接続さ
れる第2のトランジスタとを有した減衰器、 この減衰器の第2のトランジスタのベースに接続され、
外部から制御電圧が印加される音量制御入力端子、 上記減衰器の第2のトランジスタのコレクタに接続さ
れ、上記減衰器にて音量制御された音声信号を外部へ出
力するための音声出力端子、 上記減算手段の出力ノードと上記減衰器における第1及
び第2のトランジスタのエミッタの共通接続ノードとの
間に接続され、上記減算手段からの信号電流を上記減衰
器における第1及び第2のトランジスタのエミッタの共
通接続ノードに伝達するとともに、上記減算手段からの
信号電流に基づいた交流信号電圧として上記音声直接出
力端子への音声信号とするための抵抗を備えた信号処理
回路装置。
1. An FM detector that detects an FM audio signal and outputs two output currents in which alternating currents based on the amplitude of the audio signal are superimposed on a DC bias current with opposite polarities, and 2 from the FM detector. Receiving two output currents, these two
Subtracting means for subtracting two output currents and outputting a signal current in which the DC bias current has been canceled to the output node; a direct audio output terminal for outputting an audio signal to the outside, which is connected to the output node of the subtracting means. , A first transistor to which a reference voltage is applied to the base,
An attenuator having a second transistor whose emitter is connected to the emitter of this first transistor, connected to the base of the second transistor of this attenuator,
A volume control input terminal to which a control voltage is applied from the outside, an audio output terminal connected to the collector of the second transistor of the attenuator, for outputting an audio signal whose volume is controlled by the attenuator to the outside, The signal current from the subtracting means is connected between the output node of the subtracting means and the common connection node of the emitters of the first and second transistors in the attenuator, and the signal current from the subtracting means is connected to the first and second transistors in the attenuator. A signal processing circuit device provided with a resistor for transmitting the signal to a common connection node of the emitters and for converting it into an audio signal to the audio direct output terminal as an AC signal voltage based on a signal current from the subtracting means.
【請求項2】抵抗の一端は減衰器における第1及び第2
のトランジスタのエミッタの共通接続ノードに直接接続
されていることを特徴とする特許請求の範囲第1項記載
の信号処理回路装置。
2. One end of the resistor is the first and second ends of the attenuator.
The signal processing circuit device according to claim 1, wherein the signal processing circuit device is directly connected to a common connection node of the emitters of the transistors.
【請求項3】減衰器は、第1及び第2のトランジスタの
エミッタの共通接続ノードと抵抗の一端との間に接続さ
れ、ベースに所定電位が印加される第3のトランジスタ
を有していることを特徴とする特許請求の範囲第1項記
載の信号処理回路装置。
3. The attenuator has a third transistor connected between a common connection node of the emitters of the first and second transistors and one end of the resistor, and having a predetermined potential applied to the base. The signal processing circuit device according to claim 1, wherein
【請求項4】減衰器は、第1及び第2のトランジスタの
エミッタの共通接続ノードと抵抗の一端との間に接続さ
れた抵抗を有していることを特徴とする特許請求の範囲
第1項記載の信号処理回路装置。
4. The attenuator has a resistor connected between a common connection node of the emitters of the first and second transistors and one end of the resistor. The signal processing circuit device according to the item.
JP59099214A 1984-05-15 1984-05-15 Signal processing circuit device Expired - Lifetime JPH0630410B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59099214A JPH0630410B2 (en) 1984-05-15 1984-05-15 Signal processing circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59099214A JPH0630410B2 (en) 1984-05-15 1984-05-15 Signal processing circuit device

Publications (2)

Publication Number Publication Date
JPS60240202A JPS60240202A (en) 1985-11-29
JPH0630410B2 true JPH0630410B2 (en) 1994-04-20

Family

ID=14241400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59099214A Expired - Lifetime JPH0630410B2 (en) 1984-05-15 1984-05-15 Signal processing circuit device

Country Status (1)

Country Link
JP (1) JPH0630410B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916441A (en) * 1982-07-20 1984-01-27 Nec Corp Scrambler

Also Published As

Publication number Publication date
JPS60240202A (en) 1985-11-29

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