JPH06303223A - Data transmission device - Google Patents

Abstract

PURPOSE:To reduce the average power consumption of LSI for subscriber line data transmission (TLSI) and to reduce the power consumption of ISDN including LSI for subscriber line data transmission. CONSTITUTION:In LSI for subscriber line data transmission, which is included in the subscriber line device of ISDN, a line state monitor circuit TED judges the error rate of received data and monitors the transmission quality of a subscriber line LINE. When transmission quality is satisfactory and the output signal, namely, a mode control signal LPM is a high level, the output amplitude of a transmission circuit TDRV is reduced, the operation of one unit A/D conversion circuit in differential type A/D conversion circuits A/D is stopped and the operation of a boosting circuit HVCG is stopped. The number of the dynamic steps of a digital signal processing unit DSP is reduced or the frequency of a clock signal CP outputted from a phase locked loop circuit PLL is lowered and LSI for subscriber line data transmission is selectively set to be a low consumption power mode in accordance with the transmission quality of the subscriber line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, for example, a technique which is particularly effective when used for an LSI (Large Scale Integrated Circuit) for subscriber line data transmission of ISDN (Integrated Service Digital Network). Is.

[0002]

2. Description of the Related Art There is an ISDN for transmitting voice, data, image information, etc. by integrating them in a digital format. Further, in such ISDN and the like, there is a subscriber line device for coupling between a switching center and a terminal device coupled to the switching center via a telephone line, and is included in such a subscriber line device. There is a subscriber line data transmission LSI.

Regarding the subscriber line data transmission LSI included in the ISDN subscriber line device, for example, in May 1990, "Motorola Semiconductor Technical Data (Motorola Semiconductor Technical Data)" issued by Motorola, Inc. in the United States was published.
technical Data) Advanced Information ISDN U-Interface Transceiver (Advance Information ISD)
N U-Interface Transceive
r) MC145472 ”and the like.

[0004]

Prior to the present invention, the inventors of the present application developed a subscriber line data transmission LSI for use in an ISDN subscriber line device as shown in FIG. In the figure, the subscriber line data transmission LSI is a stored program type digital signal processing unit DSP.
, A phase locked loop circuit PLL which forms a clock signal CP based on the external clock signal CK and supplies it to the digital signal processing unit DSP, and a hybrid circuit HYB which converts a transmission digital signal into an analog signal.
From the transmission circuit TDRV to the subscriber line LINE from
A (analog) / D (digital) conversion circuit A / D for converting a received analog signal input from the subscriber line LINE via the hybrid circuit HYB into a digital signal
And a booster circuit VCHG that forms a relatively high positive potential internal voltage VCH based on the power supply voltage VCC and supplies it to analog circuits such as the transmission circuit TDRV and the A / D conversion circuit A / D.
With. One of the subscriber line data transmission LSIs has a subscriber line L via a hybrid circuit HYB.
Bound to INE. On the other hand, it is connected to the line state monitoring circuit TD, and the terminal device TERM
Alternatively, it is coupled to the exchange EX.

As is well known, the subscriber line L in the telephone network is
INE has an extension distance of 0 km (km).
~ 5.5km is assumed, subscriber line data transmission LSI
The various parts of 9 are responsible for changing the conditions of the subscriber line LINE.
It is designed to be compatible with 9% or more. That is, each part of the subscriber line data transmission LSI is designed under the worst condition of the subscriber line LINE, that is, the extension distance of 5.5 km.
For example, in the transmission circuit TDRV, the output amplitude is sufficiently large, in the A / D conversion circuit A / D, the number of bits of the digital output signal is sufficiently large to improve the resolution, and in the digital signal processing unit DSP. The device is devised such that the number of dynamic steps is sufficiently increased by adding processes for the backward tap calculation of the transversal filter and the fine adjustment of the phase-locked loop circuit.

On the other hand, in the telephone network forming the ISDN, the operating power source of the subscriber line data transmission LSI is the subscriber line LIN.
Since it is supplied from the exchange EX through E, the maximum allowable power consumption is specified in the design specifications of the subscriber line data transmission LSI. As described above, since each part of the subscriber line data transmission LSI is designed on the assumption of the worst condition of the subscriber line LINE, conversely, when the subscriber line LINE is relatively short, so-called over-spec is required. The above power is consumed. As a result, the amount of power supplied to the exchange is increased, which hinders the reduction of power consumption as ISDN.

An object of the present invention is to reduce the average power consumption of a subscriber line data transmission LSI or the like, and promote low power consumption of ISDN or the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in the subscriber line data transmission LSI included in the ISDN subscriber line device, the transmission quality of the subscriber line is monitored based on the error rate of the received data, and if the transmission quality is good, for example, The output amplitude of the transmission circuit is reduced, the operation of one unit A / D conversion circuit of the differential A / D conversion circuit is stopped, the operation of the booster circuit is stopped, and the number of dynamic steps of the digital signal processing unit is reduced. Then, the frequency of the clock signal formed by the phase locked loop circuit is lowered to selectively set the subscriber line data transmission LSI to the low power consumption mode.

[0010]

According to the above means, for example, over-spec can be prevented when the extension distance of the subscriber line is relatively short, and the power consumption of each part can be selectively reduced.
The average power consumption of the subscriber line data transmission LSI can be reduced, and the low power consumption of ISDN including the subscriber line data transmission LSI can be promoted.

[0011]

1 is a block diagram of an embodiment of a subscriber line data transmission LSI (TLSI) to which the present invention is applied. An outline of the configuration and operation of the subscriber line data transmission LSI of this embodiment will be described with reference to FIG. In addition, L for subscriber line data transmission of this embodiment is used.
SI is included in the subscriber line device of ISDN, and FIG. 1 also shows another part of the subscriber line device including the subscriber line data transmission LSI. The circuit elements forming each block of the subscriber line data transmission LSI are
Although not particularly limited, it is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, an LS for subscriber line data transmission
I has a stored program type digital signal processing unit DSP as its basic component. A predetermined clock signal CP is supplied from the phase locked loop circuit PLL to the digital signal processing unit DSP, and the digital signal processing unit DSP receives the clock signal C.
It operates synchronously according to P. The digital signal processing unit DSP also includes a read-only memory (not shown), and operates in steps according to a control program stored in the read-only memory. As a result, the digital signal processing unit DSP performs communication control processing, filter arithmetic processing on received data, and the like, and also controls each part of the subscriber line data transmission LSI.

The phase-locked loop circuit PLL is based on an external clock signal CK supplied from a clock generation circuit (not shown) of the subscriber line device, and is clocked in phase with this external clock signal and having a frequency several times higher than that of the external clock signal CK. The signal CP is formed and supplied to the digital signal processing unit DSP.

The digital signal processing unit DSP is, on the one hand, coupled to the transmission circuit TDRV and the A / D conversion circuit A / D. In the other side, the line state monitoring circuit T is connected via an interface circuit (not shown).
In addition to being coupled to the ED, it is coupled to the terminal device TERM or the exchange EX. Transmission circuit TDRV and A / D
The conversion circuit A / D is coupled to the subscriber line LINE via the hybrid circuit HYB. Needless to say, the subscriber line device including the subscriber line data transmission LSI is provided on both the terminal device side and the switching center side of the subscriber line LINE, and the other of the digital signal processing units DSP is a subscriber. When the trunk line equipment is installed on the terminal equipment side, it is connected to the terminal equipment TERM, and when it is installed on the exchange office side, it is connected to the exchange office EX. A predetermined internal voltage VCH is supplied from the booster circuit VCHG to the analog circuit of the subscriber line data transmission LSI including the A / D conversion circuit A / D, and the booster circuit VCHG supplies a power supply (not shown) of the subscriber line device. A predetermined power supply voltage VCC is supplied from the circuit. Although the power supply voltage VCC is not particularly limited, it is a positive power supply voltage having a relatively small absolute value such as + 3V.

As will be described later, the transmission circuit TDRV includes a so-called charge redistribution type D (digital) / A (analog) conversion circuit D / A and an amplifier circuit for driving a line,
The transmission digital signal transmitted from the digital signal processing unit DSP is converted into a predetermined analog signal according to the transmission characteristic of the telephone line, and then output to the subscriber line LINE via the hybrid circuit HYB.

As will be described later, the A / D conversion circuit A / D is composed of a so-called differential A / D conversion circuit, and has a pair of unit A / D conversion circuits ADC1 and ADC2 and these unit A / D conversion circuits. And a subtraction circuit SUB for receiving the output signal of the circuit. Of these, the unit A / D conversion circuits ADC1 and A
DC2 is from the subscriber line LINE to the hybrid circuit HY
The non-inverted and inverted reception analog signals input via B are respectively converted into digital signals, and the subtraction circuit SUB
Forms a received digital signal by taking the difference between the output signals of these unit A / D conversion circuits.

The booster circuit VCHG forms a positive potential internal voltage VCH having a relatively large absolute value such as + 5V based on the power supply voltage VCC, and includes a subscriber line including an A / D conversion circuit A / D. It is supplied to the analog circuit of the data transmission LSI. That is, the subscriber line data transmission LS of this embodiment
I is a power supply voltage V having a relatively small absolute value such as + 3V
Despite using CC as an operating power source, the analog circuit represented by the A / D conversion circuit A / D is supposed to use an internal voltage VCH having a relatively large absolute value such as + 5V as an operating power source. As a result, the conversion accuracy is improved.

On the other hand, the line status monitoring circuit TED is a so-called CRC (Cyclic Redundancy Check).
By adopting the method, the transmission error of the received digital signal obtained from the A / D conversion circuit A / D via the digital signal processing unit DSP is identified. Further, the transmission quality of the subscriber line LINE is determined based on the result, that is, the transmission error rate, and if the transmission error rate is below a predetermined value, in other words, the extension distance is short, for example Party line L
The output signal, that is, the mode control signal LPM, is selectively set to the high level on the condition that the transmission characteristics of the INE are in a good state. The mode control signal LPM is transmitted to the transmission line TDRV and A / D conversion circuit A of the subscriber line data transmission LSI.
/ D, the booster circuit VCHG, the digital signal processing unit DSP, and the phase-locked loop circuit PLL. As will be described later, this mode control signal LP
When M is set to high level, L for subscriber line data transmission
Each part of SI is selectively set to a low power consumption mode.

FIG. 2 shows L for subscriber line data transmission of FIG.
The conceptual diagram of one Example for demonstrating the mode switching of SI is shown. Further, FIGS. 3 and 4 show a transmitting circuit TDRV included in the subscriber line data transmission LSI of FIG.
1 and a partial circuit diagram and a block diagram of an embodiment of the A / D conversion circuit A / D, respectively. FIG. 5 shows a digital signal processing unit DSP included in the subscriber line data transmission LSI of FIG. A program configuration diagram and a process flow diagram of one embodiment are shown. Based on these figures, the configuration and mode switching of each part and software of the subscriber line data transmission LSI of this embodiment, and the features thereof will be described.

As described above, the subscriber line device including the subscriber line data transmission LSI of this embodiment determines the error rate of the received data by the CRC check and determines the subscriber line LINE.
A line state monitoring circuit TED for identifying the transmission quality of
The output signal of the line state monitoring circuit TED, that is, the mode control signal LPM, is used as a transmission circuit TDRV, an A / D conversion circuit A / D, a booster circuit VCHG, a digital signal processing unit DSP and a phase which constitute a subscriber line data transmission LSI. It is supplied to the locked loop circuit PLL. The mode control signal LPM is not particularly limited, but is set to a low level when the transmission error rate of the received data is larger than a predetermined value and is set to a high level when it is set to a predetermined value or less, as shown in FIG. It When this mode control signal LPM is at low level, the subscriber line data transmission LSI is in the so-called high power consumption mode for the following reasons, and when it is at low level it is in the low power consumption mode.

First, referring to FIG. 3, the transmission circuit TDRV is shown.
Is not particularly limited, but includes an operational amplifier circuit OA1 forming a charge redistribution type D / A conversion circuit D / A and another operational amplifier circuit OA2 forming an amplifier circuit for line drive. Of these, a predetermined bias voltage VB is supplied to the non-inverting input terminal + of the operational amplifier circuit OA1, and the inverting input terminal-of the operational amplifier circuit OA1 has a parallel form of the capacitor C1 and the switch S1.
Is coupled to the output terminal thereof through and to internal node n3. The output terminal of the operational amplifier circuit OA1 is coupled to the non-inverting input terminal + of the operational amplifier circuit OA2 via the switch S2, and the internal node n3 is commonly coupled to the upper electrodes of the n capacitors CS1 to CSn. The electrodes below these capacitors are the corresponding switches SA1-SA.
It is coupled to internal node n1 via n, that is, the ground potential of the circuit, and is coupled to internal node n2 via corresponding switches SB1 to SBn. This internal node n2
Of the reference voltage Vref1 via a switch S3 that is selectively switched according to the mode control signal LPM.
Alternatively, Vref2 is selectively supplied.

In this embodiment, the reference voltage Vref1
Is a constant voltage of positive potential having an absolute value larger than the reference voltage Vref2. Further, the internal node n3 receives the reference voltage V when the mode control signal LPM is at a low level.
ref1 is supplied, and the reference voltage Vref2 is supplied when it is set to the high level. Furthermore, the transmission circuit TDRV
Includes a decoder (not shown) for receiving a transmission digital signal, and includes switches SA1 to SAn and SB1 to SB.
n is selectively turned on or off according to the output signal of this decoder, that is, the transmitted digital signal.

When the D / A conversion circuit D / A constituting the transmission circuit TDRV is set to the reset cycle, the switch S
1 and SA1 to SAn are both turned on, and switches S2 and SB1 to SBn are all turned off. Therefore, the lower electrodes of the capacitors CS1 to CSn are reset to the ground potential of the circuit, that is, 0V, and the upper electrodes thereof are biased to the bias voltage VB by the virtual ground of the operational amplifier circuit OA1. Further, the non-inverting input terminal + of the operational amplifier circuit OA2 is supplied with a potential corresponding to the electric charge accumulated in the capacitor C2, and this potential is applied to the operational amplifier circuit O2.
Transmit analog signal TS as it is by virtual grounding of A2
Is transmitted to the output terminal.

On the other hand, when the D / A conversion circuit D / A is set to the D / A conversion cycle, the switch S1 is turned off,
Instead, the switch S2 is turned on. The switches SA1 to SAn and SB1 to SBn are selectively and complementarily turned on or off according to an output signal of a decoder (not shown), that is, a transmission digital signal. Therefore, the electrodes below the capacitors CS1 to CSn corresponding to the switches that are turned on among the switches SB1 to SBn are pushed up to the reference voltage Vref1 or Vref2, and the capacitance between these capacitors and the capacitor C1 is increased. The charge is distributed according to. As a result, at the output terminal of the operational amplifier circuit OA1, that is, the non-inverting input terminal + of the operational amplifier circuit OA2, the charge distribution, that is, the analog potential corresponding to the transmission digital signal is obtained, and a new transmission analog signal TS is obtained.

By the way, the electric potential of the transmission analog signal TS obtained as the output signal of the operational amplifier circuit OA2 which constitutes the line driving amplifier circuit is proportional to the electric potential of the reference voltage supplied to the internal node n2, and the electric potential of the transmission circuit TDRV is increased. Power consumption increases in proportion to the potential of the transmission analog signal TS, that is, its amplitude. As described above, the reference voltage Vr of a relatively high potential is applied to the internal node n2 when the mode control signal LPM is set to the low level, in other words, when the transmission error rate of the received data exceeds the predetermined value and is large.
ef1 is supplied. Therefore, the transmission analog signal TS
Is correspondingly large, which increases the amount of analog signal transmitted via the subscriber line LINE. On the other hand, when the mode control signal LPM is set to the high level, in other words, when the transmission error rate of the received data is less than or equal to the predetermined value, the internal node n2 is
The reference voltage Vref2 having a relatively low potential is supplied. For this reason, the amplitude of the transmitted analog signal TS is correspondingly small, whereby the signal amount of the analog signal transmitted via the subscriber line LINE is reduced to a necessary and sufficient value. As a result, the transmission circuit TDRV is set to the high power consumption mode to suppress the transmission error rate and the mode control signal LPM is set to the high level when the mode control signal LPM is set to the low level as shown in FIG. In this case, the low power consumption mode is set without unnecessarily reducing the transmission error rate.

The A / D conversion circuit A / D is a differential type A / D conversion circuit, and as shown in FIG. 4, a unit A / D that receives a non-inverted reception analog signal ARSP via a hybrid circuit HYB. It includes a conversion circuit ADC1 and a unit A / D conversion circuit ADC2 that receives the inverted reception analog signal ARSN. Of these, the i + 1-bit digital signal output from the unit A / D conversion circuit ADC1 is the subtraction circuit SU.
The i + 1-bit digital signal supplied to the non-inverting input terminal + of B and output from the unit A / D conversion circuit ADC2 is supplied to the inverting input terminal − of the subtraction circuit SUB. The unit A / D conversion circuit ADC2 has the mode control signal L
PM is supplied.

The unit A / D conversion circuit ADC1 is constantly in the operating state when the subscriber line data transmission LSI is in the operating state, and converts the non-inverted reception analog signal ARSP into a digital signal, and the subtraction circuit. It is transmitted to the non-inverting input terminal + of the SUB. Further, the unit A / D conversion circuit ADC2
Is selectively activated when the mode control signal LPM is set to low level when the subscriber line data transmission LSI is activated, and the inverted reception analog signal A
The RSN is converted into a digital signal and transmitted to the inverting input terminal-of the subtraction circuit SUB. When the mode control signal LPM is at a high level, the unit A / D conversion circuit ADC2 is in a non-operation state, and its digital output signal is all bit logic "0".

The subtraction circuit SUB is a unit A / D conversion circuit A.
The difference between the digital signals output from DC1 and ADC2 is calculated, and the result is received digital signals DRS0-D
It is transmitted to the digital signal processing unit DSP as RSi. As described above, when the mode control signal LPM is set to the low level, in other words, when the transmission error rate of the received data exceeds the predetermined value and is large, the A / D conversion circuit A /
In D, the unit A / D conversion circuits ADC1 and ADC2 are simultaneously operated, and high-precision conversion processing is performed by a differential operation, but the power consumption is such that two unit A / D conversion circuits operate simultaneously. Being in a state makes it relatively large. On the other hand, when the mode control signal LPM is set to the high level, in other words, when the transmission error rate of the received data is less than or equal to the predetermined value, in the A / D conversion circuit A / D, only the unit A / D conversion circuit ADC1 is operated. It is put into an operating state, and its conversion accuracy is lowered to a required minimum value, but its power consumption is approximately one half that in the case where two unit A / D conversion circuits are placed into an operating state at the same time. . As a result, A
As shown in FIG. 2, when the mode control signal LPM is at a low level, the / D conversion circuit A / D is in a high power consumption mode to suppress the transmission error rate, and the mode control signal LPM is at a high level. In this case, the low power consumption mode is set without unnecessarily reducing the transmission error rate.

As described above, the analog circuit of the subscriber line data transmission LSI including the A / D conversion circuit A / D uses the internal voltage VCH output from the booster circuit VCHG as its operating power source. This booster circuit VCHG is shown in FIG.
As shown in FIG. 5, when the mode control signal LPM is at a low level, in other words, it is activated only when the transmission error rate of the received data exceeds a predetermined value and is large. At this time, the conversion accuracy of the analog circuit including the A / D conversion circuit A / D is increased by setting the internal voltage VCH to a relatively high potential such as +5 V, and thereby the subscriber line data transmission LSI. That is, the transmission error rate as a subscriber line device is increased. When the mode control signal LPM is set to a high level, in other words, when the transmission error rate of received data is less than or equal to a predetermined value, the booster circuit VCH
G is in a non-operating state, and the potential of the internal voltage VCH is set to the same potential as the power supply voltage VCC. At this time, the conversion accuracy of the analog circuit including the A / D conversion circuit A / D is lowered to the minimum required value, but the power consumption of the A / D conversion circuit A / D is reduced because the booster circuit VCHG is not operated. Made smaller. As a result, the booster circuit VCHG is set to the high power consumption mode to suppress the transmission error rate when the mode control signal LPM is set to the low level, as shown in FIG.
When the mode control signal LPM is set to the high level, the low power consumption mode is set without unnecessarily reducing the transmission error rate.

Next, the digital signal processing unit DSP
5A, as shown in FIG. 5A, addresses H “0000” to H “FFFF” of the built-in read-only memory.
(Here, the address of the read-only memory is displayed in so-called hexadecimal notation) and the step operation is performed according to the control program stored therein. Of these, the address H "000
For 0 "to H" 7FFE ", the processing A to be executed regardless of the transmission error rate, that is, the transmission quality of the subscriber line LINE.
Or processing E is included, and addresses H “8000” to H
"FFFE" includes processing F or processing I which is required when the transmission error rate is high, and which includes, for example, backward tap calculation processing of the adaptive transversal filter and fine adjustment processing of the phase locked loop circuit PLL. Then, at the address H “7FFF”, the mode control signal LP
When M is set to high level and the corresponding return flag LPM is set to logic "1", the address H "000 is selectively selected.
The conditional return instruction for returning to 0 "is stored, and the address H" 000 "is unconditionally stored in the address H" FFFF ".
A return instruction for returning to 0 "is stored.

When the mode control signal LPM is set to the low level, in other words, when the error rate of the received data exceeds the predetermined value and is large, the digital signal processing unit DS.
At P, the return flag LPM is reset to be logical "0". Therefore, the step operation of the digital signal processing unit DSP started in the process A of the address H "0000", as shown in FIG. 5B, proceeds from the process E of the address H "7FFE" to the address H "8000".
The processing shifts to the processing F. Then, the address H “FFFE”
After the processing I is completed, the process returns to the processing A at the address H “0000” by the return instruction at the address H “FFFF”. Therefore, the number of dynamic steps of the digital signal processing unit DSP is from the address H "0000" to
The H "FFFF" step corresponds to the H "FFFF" instruction. As a result, the digital signal processing unit D
The SP is in a so-called full-operation mode and consumes a large amount of power. However, since the dynamic step includes the processes F and I, the subscriber line data transmission LSI
The transmission error rate is suppressed to a small value.

On the other hand, when the mode control signal LPM is at a high level, in other words, when the error rate of the received data is below a predetermined value, the digital signal processing unit D
At SP, the return flag LPM is set to be logical "1". Therefore, the step operation of the digital signal processing unit DSP started in the processing A of the address H “0000” is performed by the conditional return instruction of the address H “7FFF” after finishing the processing E of the address H “7FFE”. It returns to the processing A of "0000". Therefore, the number of dynamic steps of the digital signal processing unit DSP is the address H "0000" to H "7F.
This is the H "7FFF" step corresponding to the FF "command, which is one half of the above full operation.
Although not particularly limited, the digital signal processing unit DSP is in a so-called halt state before returning to the processing A of the address H "0000", and is in a suspended state for a predetermined period. Therefore, the digital signal processing unit DSP
However, since the dynamic step does not include the processing F or the processing I, the transmission error rate of the subscriber line data transmission LSI is suppressed to a necessary minimum. As a result, as shown in FIG. 2, the digital signal processing unit DSP is in the high power consumption mode to suppress the transmission error rate when the mode control signal LPM is low level, and the mode control signal LPM is high level. In this case, the low power consumption mode is set without unnecessarily reducing the transmission error rate.

By the way, the power consumption of the digital signal processing unit DSP when the mode control signal LPM is set to the high level and the number of dynamic steps of the digital signal processing unit DSP is approximately halved, selects the frequency of the clock signal CP. It is also possible to selectively reduce the size by selectively switching. That is, when the mode control signal LPM is set to the low level, as shown in FIG. 2, for example, the phase locked loop circuit PLL
When the frequency control circuit LPM is set to the high level by decreasing the frequency division ratio of the frequency dividing circuit included in the above and increasing the frequency of the clock signal CP, the phase locked loop circuit P
It suffices to increase the frequency division ratio of the frequency divider circuit included in LL to lower the frequency of the clock signal CP.

As described above, in the subscriber line data transmission LSI of this embodiment, the line state monitoring circuit TED for identifying the transmission error rate of the received data is used to transmit the subscriber line data transmission L.
Transmission circuit TDRV, A / D conversion circuit A /
D, booster circuit VCHG, digital signal processing unit D
The output signal, that is, the mode control signal LPM is commonly supplied to the SP and the phase locked loop circuit PLL, and the power consumption of these circuits is such that the transmission error rate of the subscriber line LINE becomes a predetermined value or less and the mode control signal LPM is It is made small selectively by being made high level.
As a result, for example, it is possible to prevent the over-specification of the subscriber line data transmission LSI in a state where the extension distance of the subscriber line is relatively short and selectively reduce the power consumption of each part of the subscriber line data transmission LSI. Therefore, the average power consumption of the subscriber line data transmission LSI can be reduced, and the subscriber line device including the subscriber line data transmission LSI and thus the ISD can be reduced.
It is possible to promote low power consumption of N.

As shown in the above embodiment, the present invention is applied to a data transmission device such as a subscriber line data transmission LSI included in an ISDN subscriber line device to obtain the following effects. Is obtained. (1) In a subscriber line data transmission LSI or the like included in the ISDN subscriber line device, the transmission quality of the subscriber line is monitored based on the error rate of the received data, and when the transmission quality is good, Is a differential type A
The operation of one unit A / D conversion circuit of the / D conversion circuit is stopped, the operation of the booster circuit is stopped, the number of dynamic steps of the digital signal processing unit is reduced, and the clock signal generated by the phase locked loop circuit By lowering the frequency and selectively setting the subscriber line data transmission LSI to the low power consumption mode, for example, the subscriber line data transmission LSI in a state where the extension distance of the subscriber line is relatively short.
It is possible to obtain the effect that it is possible to prevent over-spec such as.

(2) According to the above item (1), it is possible to selectively reduce the power consumption of each part of the subscriber line data transmission LSI. (3) By the above items (1) and (2), the average power consumption of the subscriber line data transmission LSI is reduced, and the low power consumption of the ISDN including the subscriber line data transmission LSI is promoted. The effect of being able to do is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the subscriber line LINE which is a transmission line may be a wireless line, or may be a transmission line other than the subscriber line. In addition, the line status monitoring circuit TE
D may be included in the subscriber line data transmission LSI, or its output signal, that is, the mode control signal LPM.
The logic level of can also be inverted. The mode control signal LPM output from the line state monitoring circuit TED may be composed of 2 bits or more. In this case, three or more operation modes can be prepared in each part of the subscriber line data transmission LSI, and the switching method may be changed for each circuit. In this embodiment, the transmission quality of the subscriber line LINE is identified by the error rate of the received data, but it may be identified by the error rate of the transmitted data returned from the receiving side. The transmission error rate can be determined by a method other than CRC, and the transmission quality of the transmission line can be identified by characteristics other than the transmission error rate.

In FIG. 3, the potential of the reference voltage can be switched in three or more steps. In addition, the transmission circuit TDR
The V D / A conversion circuit D / A can take a form other than the charge redistribution type, and the configuration of the line driving amplifier circuit is also arbitrary. In FIG. 4, the unit A / D conversion circuit ADC2
Is constantly operated, and the unit A / D conversion circuit ADC1
May be selectively activated according to the mode control signal LPM. Further, the A / D conversion circuit A / D and the transmission circuit T
The D / A conversion circuit D / A included in the DRV may be, for example, a so-called flash type A / D conversion circuit or D / A conversion circuit, and the upper bits thereof may be selectively effective for the mode control signal LPM. In this case, by disabling the upper 1 bit, the power consumption of the A / D conversion circuit and the D / A conversion circuit becomes approximately one half, and the same effect can be obtained.

In FIG. 5, the program configuration of the digital signal processing unit DSP and the specific value of the address are not restricted by this embodiment. Further, the number of dynamic steps of the digital signal processing unit DSP can be switched in three or more steps by increasing the number of conditional return instructions. Further, the block configuration of the subscriber line data transmission LSI shown in FIG. 1 and the transmission circuit TDRV and A / D conversion circuit A shown in FIGS.
Various embodiments can be adopted for the specific circuit configuration of / D, the polarity and absolute value of the power supply voltage, and the like.

In the above description, the invention made mainly by the present inventor is the field of application which is the background of the invention.
L for subscriber line data transmission included in DN subscriber line device
Although the case where it is applied to SI has been described, the present invention is not limited to this, and for example, a subscriber line data transmission LSI included in a LAN (Local Area Network) or the like.
And various similar data transmission LSIs.
INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a data transmission device provided for a transmission line having a large allowable variation range of transfer characteristics and a communication system including such a data transmission device.

[0041]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the subscriber line data transmission LSI or the like included in the ISDN subscriber line device, the transmission quality of the subscriber line is monitored based on the error rate of the received data,
If the transmission quality is good, the output amplitude of the transmission circuit is reduced, the operation of one unit A / D conversion circuit of the differential A / D conversion circuit is stopped, the operation of the booster circuit is stopped, and The number of dynamic steps of the signal processing unit is reduced and the frequency of the clock signal formed by the phase-locked loop circuit is lowered to reduce L for subscriber line data transmission.
By selectively setting the SI to the low power consumption mode, it is possible to prevent the over-spec in the state where the extension line of the subscriber line is relatively short and selectively reduce the power consumption of each unit. The average power consumption of the subscriber line data transmission LSI can be reduced, and the low power consumption of ISDN including the subscriber line data transmission LSI can be promoted.

[Brief description of drawings]

FIG. 1 is an L for subscriber line data transmission to which the present invention is applied.
It is a block diagram which shows one Example of SI.

FIG. 2 is a conceptual diagram showing an embodiment for explaining mode switching of the subscriber line data transmission LSI of FIG.

FIG. 3 is a partial circuit diagram showing an embodiment of a transmission circuit included in the subscriber line data transmission LSI of FIG.

4 is a block diagram showing an embodiment of an A / D conversion circuit included in the subscriber line data transmission LSI of FIG.

5 is a program configuration diagram and a process flow diagram showing an embodiment of a digital signal processing unit included in the subscriber line data transmission LSI of FIG.

FIG. 6 is a block diagram showing an example of a subscriber line data transmission LSI developed by the inventors of the present application prior to the present invention.

[Explanation of symbols]

LINE ... subscriber line, HYB ... hybrid circuit, TLSI ... subscriber line data transmission LSI, TE
D: Line status monitoring circuit, TERM: Terminal device,
EX ... Exchange. DSP: Digital signal processing unit, PLL: Phase locked loop circuit, T
DRV ... Transmission circuit, A / D ... A / D conversion circuit,
VCHG ... Booster circuit. OA1 to OA2 ... Operational amplifier circuit, S1 to S3, SA1 to SAn, SB1 to SBn
... Switches, C1-C2, CS1-CSn ... Capacitance. ADC1 to ADC2 ... Unit A / D conversion circuit, S
UB ... Subtraction circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 12/02 29/02 H04M 11/00 303 7470-5K

Claims (3)

[Claims] 1. A data transmission device, characterized in that its power consumption is selectively switched according to the transmission quality of a transmission line. 2. The transmission quality of the transmission line is an error rate of received data, and the error rate of the received data is CRC.
The data transmission device according to claim 1, wherein the data transmission device is determined by a check. 3. The data transmission device is an ISDN subscriber line data transmission LSI, the transmission line is the ISDN subscriber line, and the subscriber line data transmission LSI outputs the data. A transmission circuit whose amplitude is selectively switched according to the transmission quality of the subscriber line, and a difference in which one of the unit A / D conversion circuits is selectively operated according to the transmission quality of the subscriber line. A dynamic A / D conversion circuit,
A booster circuit whose output voltage is selectively switched according to the transmission quality of the subscriber line, and a digital signal processing unit whose dynamic step number is selectively increased or decreased according to the transmission quality of the subscriber line, 3. A data transmission device according to claim 1, further comprising a phase-locked loop circuit whose output frequency is selectively switched according to the transmission quality of the subscriber line.