AU6258600A - Interface for coupling a bus node to the bus line of a bus system - Google Patents
Interface for coupling a bus node to the bus line of a bus system Download PDFInfo
- Publication number
- AU6258600A AU6258600A AU62586/00A AU6258600A AU6258600A AU 6258600 A AU6258600 A AU 6258600A AU 62586/00 A AU62586/00 A AU 62586/00A AU 6258600 A AU6258600 A AU 6258600A AU 6258600 A AU6258600 A AU 6258600A
- Authority
- AU
- Australia
- Prior art keywords
- bus
- voltage
- interface
- supply voltage
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40039—Details regarding the setting of the power status of a node according to activity on the bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/10—Current supply arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Interface Circuits In Exchanges (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Communication Control (AREA)
- Power Sources (AREA)
Abstract
The invention relates to an interface (2) for coupling a bus node (6) to the bus line of a bus system (4). According to the invention, the inventive interface comprises an input (10) for an external supply voltage (Vext) which is provided by a bus-independent voltage source (8), and comprises a monitoring circuit (30). Said monitoring circuit is provided for comparing an internal supply voltage (Vcc) derived from the bus voltage with the external supply voltage (Vext) and for generating an output control signal (R) for the bus node (6) based on the result of the comparison.
Description
GR 99 P 3387 -1 Description Interface for coupling a bus user to the bus line of a bus system 5 The invention relates to an interface for coupling a bus user to the bus line of a bus system, in particular to the bus system EIB of the European Installation Bus Association EIBA. 10 The bus system EIB is a two-wire bus system in which the voltage supply of the bus users which are respectively connected to the bus, system via an interface and the data transmission between the latter 15 are combined on one pair of lines. In this type of bus system, the power drain per bus user is limited to 10 mA, for example. However, such a limited power drain is not sufficient for all the bus users in all applications so that it may be necessary to supply an 20 external voltage to bus users with a higher power requirement. Such an additional external supply voltage which is independent of the bus can also be advantageous for relieving the loading on the voltage supply of the EIB. 25 In such a case, the situation arises in which although the interface, for example a TPUART-IC, is supplied from the EIB cell, the bus user which is connected to the bus system via this interface is fed from an 30 external voltage supply which is independent of the latter. An interface which is used with the EIB generates a control signal (reset signal) for the bus user with 35 which, inter alia, the exchange of data is enabled only if the supply voltage of the bus user has reached a predefined value, and the bus user has also been given sufficient time for a correct run-up. When GR 99 P 3387 - la there is no bus voltage, or insufficient bus voltage, the interface outputs a value GR 99 P 3387 -2 for a binary control signal, for example low (= reset active), which ensures that an exchange of data cannot take place. The control signal is not set to another value, for example high (= reset inactive) and an 5 exchange of data made possible until both the supply voltage of the interface and the bus voltage which is transmitted from the interface to the bus user has reached a predefined value. 10 In the case of a bus user which is supplied via an external power supply unit, an operating situation may then occur in which, on the one hand, the bus voltage is not yet present at a sufficient level, but, on the other hand, the external voltage supply for the bus 15 user is already present so that the bus user is active, but the interface itself has not yet been supplied with a sufficient supply voltage necessary for its operation. In this case, an attempt by the bus user to transmit would lead to a fault message. 20 The invention is then based on the object of disclosing an interface for coupling a bus user to the bus line of a bus system with which the faulty operating state specified above is avoided. 25 The aforesaid object is achieved according to the GR 99 P 3387 - 2 for a binary control signal, for example low (= reset active), which ensures that an exchange of data cannot take place. The control signal is not set to another value, for example high (= reset inactive) and an 5 exchange of data made possible until both- the supply voltage of the interface and the bus voltage which is transmitted from the interface to the bus user has reached a predefined value. 10 In the case of a bus user which is supplied via an external power supply unit, an operating situation may then occur in which, on the one hand, the bus voltage is not yet present at a sufficient level, but, on the other hand, the external voltage supply for the bus 15 user is already present so that the bus user is active, but the interface itself has not yet been supplied with a sufficient supply voltage necessary for its operation. In this case, an attempt by the bus user to transmit would lead to a fault message. 20 The invention is then based on the object of disclosing an interface for coupling a bus user to the bus line of a bus system with which the faulty operating state specified above is avoided. 25 The aforesaid object is achieved according to the invention with an interface having the features of patent claim 1. The interface according to the invention contains an input for an external supply 30 voltage which is made available by a voltage source which is independent of the bus, and a monitoring circuit for comparing an internal supply voltage which is derived from the bus voltage with the external supply voltage, and for generating an output control 35 signal for the bus user as a function of the result of the comparison. This measure ensures that the bus user is enabled only if the interface is also in a satisfactory operating state.
GR 99 P 3387 - 3 In one preferred embodiment of the invention, the output control signal is a binary signal whose value is determined by the sign of the difference between an internal reference voltage and an external reference 5 voltage, respectively derived from the internal supply voltage and the external supply voltage. Such an interface according to the invention is provided in particular for use in a bus system which contains at least one bus user which is supplied with an external 10 supply voltage from a voltage source which is independent of the bus. The interface according to the invention cannot be used for coupling a bus user supplied by the bus voltage. 15 For this purpose, in one advantageous configuration of the invention all that is necessary is to short-circuit the input of the external supply voltage to an output for the internal supply voltage. 20 In order to explain the invention further, reference is made to the exemplary embodiment in the drawing, in which: FIG 1 shows an interface according to the invention 25 with a bus user connected thereto, in a block circuit diagram, FIG 2 shows an advantageous configuration of a monitoring circuit for an interface according 30 to the invention. According to FIG 1, an interface 2, for example a TPUART-IC, is connected to a bus system 4, in the example a two-wire bus system, in particular an EIB. A 35 bus user 6 is connected via the interface 2 to the bus system 4 which contains the specific user electronics for this bus user 6.
3GR 99 P 3387 - 3a The bus user 6 is supplied with an external supply voltage Vext from a voltage source 8 which is independent of the GR 99 P 3387 - 4 bus. The voltage source 8 is independent of the bus in the sense that the supply voltage Vext which is generated by it is independent of the bus voltage and does not load the bus system 4. 5 The voltage source 8 which is independent of the bus is connected to a voltage input 10 of the interface 2. The interface 2 makes available at a voltage output 12 an internal supply voltage Vcc which is generated 10 internally from the bus voltage of the bus system 4 and is provided for supplying voltage to a bus user which is not connected to a voltage source 8 which is independent of the bus. In the exemplary embodiment, this voltage output 12 is not connected to the bus user 15 6 because the latter is supplied via the external voltage source 8. The exchange of data TxD and RxD between the bus system 4 and the bus user 6 takes place via transmitting and receiving lines 14 and 16, respectively. The interface 2 and the bus user 6 are 20 connected to the same reference potential M via a ground line 18. An output control signal R is present at a control output 20 of the interface 2 and is passed on to a 25 voltage input 24 of the bus user 6 via a control line 22. This output control signal R is a binary signal with two possible state values which releases the bus user 6 to receive and transmit data. 30 According to FIG 2, the interface 2 contains a monitoring circuit with a comparator 32 with which the internal supply voltage Vcc which is derived from the bus voltage is compared with the external supply voltage Vext. The external supply voltage Vext is 35 connected to ground M via a protective resistor R and a Zener diode Z which is connected in series therewith. The positive input of the comparator 32 is connected between the Zener diode Z and the protective resistor Rl.
GR 99 P 3387 - 5 As soon as the external supply voltage Vext exceeds the Zener voltage of the Zener diode Z, a constant external reference voltage Vref,ext corresponding to the Zener voltage is applied to the positive input of the 5 comparator 32. This external reference voltage Vref,ext is compared with an internal reference voltage Vref,int which is derived from the internal supply voltage Vcc and made available via a voltage divider circuit R2, R3. The comparator 32 generates, at its output, a 10 binary internal control signal S which is dependent on the sign of the difference between the external reference voltage Vref,ext and the internal supply voltage Vcc. This internal control signal S is transmitted to the gate of a MOSFET 34 whose DRAIN is 15 connected to the control output 20. The MOSFET 34 is in the off state if there is no control voltage (internal control signal S = low) present at the output of the comparator 32. This is the 20 case whenever the comparator 32 supplied by the external voltage supply is not operationally capable because there is no external supply voltage Vext, or an insufficient external supply voltage Vext, or the internal reference voltage Vref,int is less than the 25 external reference voltage Vref,ext. In this way, the output control signal R which assumes the values zero (low) and Vext (high) in the exemplary embodiment is generated from the internal control 30 signal S from the external supply voltage Vext. The voltage value for the high state can be set as desired between zero and Vext by means of suitable voltage line switching. 35 Switched in parallel with the MOSFET 34 is a further MOSFET 36 whose gate is connected to an internal module 38 which generates a control voltage for the gate of the MOSFET 36 from the internal supply voltage Vcc so - 5a that said MOSFET 36 can generate the output control signal R instead of the MOSFET 34. Ame GR 99 P 3387 - 6 In order to maintain the operational capability of the interface 2 even when there is no external voltage supply, in such a mode of operation the voltage output 12 is short-circuited to the voltage input 20, as 5 illustrated in the figure by a bridge 40 shown by dotted and dashed lines.
Claims (4)
1. An interface (2) for coupling a bus user (6) to the bus line of a bus system (4), having an input 5 (10) for an external supply voltage (Vext) which is made available by a voltage source (8) which is independent of the bus, and having a monitoring circuit (30) for comparing an internal supply voltage (Vcc) which is derived from the bus 10 voltage with the external supply voltage (Vext), and for generating an output control signal (R) for the bus user (6) as a function of the result of the comparison. 15
2. The interface (2) as claimed in claim 1, in which the output control signal (R ) is a binary signal whose value is determined by the sign of the difference between an internal reference voltage (Vref,int) and an external reference voltage 20 (Vref,ext), respectively derived from the internal supply voltage (Vcc) and the external supply voltage (Vext).
3. The bus system having an interface (2) as claimed 25 in claim 1 or 2, and having a voltage source (8) which is independent of the bus, for supplying at least one bus user (6).
4. The bus system having an interface (2) as claimed 30 in claim 1 or 2, in which in the case of at a bus subscriber (6) which is supplied by the internal supply voltage (Vcc), the input (10) for the external supply voltage (Vext) is short-circuited to the voltage output (12) of the internal supply 35 voltage (Vcc).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19926095A DE19926095A1 (en) | 1999-06-08 | 1999-06-08 | Interface for coupling a bus device to the bus line of a bus system |
DE19926095 | 1999-06-08 | ||
PCT/DE2000/001712 WO2000075794A1 (en) | 1999-06-08 | 2000-05-26 | Interface for coupling a bus node to the bus line of a bus system |
Publications (1)
Publication Number | Publication Date |
---|---|
AU6258600A true AU6258600A (en) | 2000-12-28 |
Family
ID=7910548
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU62586/00A Abandoned AU6258600A (en) | 1999-06-08 | 2000-05-26 | Interface for coupling a bus node to the bus line of a bus system |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1192551B1 (en) |
CN (1) | CN1355903A (en) |
AT (1) | ATE230862T1 (en) |
AU (1) | AU6258600A (en) |
DE (2) | DE19926095A1 (en) |
HK (1) | HK1047641A1 (en) |
WO (1) | WO2000075794A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002033843A1 (en) * | 2000-10-19 | 2002-04-25 | Siemens Aktiengesellschaft | Driver circuit |
DE20315837U1 (en) * | 2003-10-15 | 2005-03-03 | Weidmüller Interface GmbH & Co. KG | Distributor for connecting electrical equipment with multiple power supply |
DE102010002679B4 (en) * | 2010-03-09 | 2023-01-05 | Robert Bosch Gmbh | Procedure for supplying at least one bus user |
CN103345292B (en) * | 2013-06-28 | 2015-12-23 | 广东威创视讯科技股份有限公司 | Based on the apparatus for protecting power supply that DVI interface is powered |
DE102013013466B4 (en) * | 2013-08-14 | 2018-12-20 | Endress + Hauser Wetzer Gmbh + Co. Kg | Operating electronics for a two-wire process device |
EP3240133B1 (en) | 2016-04-28 | 2018-12-12 | Siemens Aktiengesellschaft | Bus participants |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01193953A (en) * | 1988-01-28 | 1989-08-03 | Pfu Ltd | System for detecting abnormality of bus |
DE19637580A1 (en) * | 1996-09-14 | 1998-03-19 | Insta Elektro Gmbh & Co Kg | Electronic data coupling component group |
DE19639635C1 (en) * | 1996-09-26 | 1998-07-09 | Texas Instruments Deutschland | CMOS-bus driver circuit for data bus system |
US5838073A (en) * | 1997-01-21 | 1998-11-17 | Dell Usa, L.P. | Sideband communication on the standard parallel SCSI bus |
DE29900129U1 (en) * | 1998-11-19 | 1999-08-26 | Lingg & Janke oHG, 78315 Radolfzell | Device for coupling to a bus |
-
1999
- 1999-06-08 DE DE19926095A patent/DE19926095A1/en not_active Withdrawn
-
2000
- 2000-05-26 WO PCT/DE2000/001712 patent/WO2000075794A1/en active IP Right Grant
- 2000-05-26 AT AT00949062T patent/ATE230862T1/en active
- 2000-05-26 AU AU62586/00A patent/AU6258600A/en not_active Abandoned
- 2000-05-26 CN CN00808742A patent/CN1355903A/en active Pending
- 2000-05-26 EP EP00949062A patent/EP1192551B1/en not_active Expired - Lifetime
- 2000-05-26 DE DE50001066T patent/DE50001066D1/en not_active Expired - Lifetime
-
2002
- 2002-12-19 HK HK02109210.3A patent/HK1047641A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
HK1047641A1 (en) | 2003-02-28 |
EP1192551A1 (en) | 2002-04-03 |
ATE230862T1 (en) | 2003-01-15 |
DE50001066D1 (en) | 2003-02-13 |
EP1192551B1 (en) | 2003-01-08 |
DE19926095A1 (en) | 2000-12-14 |
WO2000075794A1 (en) | 2000-12-14 |
CN1355903A (en) | 2002-06-26 |
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