WO2002033843A1

WO2002033843A1 - Driver circuit

Info

Publication number: WO2002033843A1
Application number: PCT/DE2000/003681
Authority: WO
Inventors: Marten Swart
Original assignee: Siemens Aktiengesellschaft
Priority date: 2000-10-19
Filing date: 2000-10-19
Publication date: 2002-04-25

Abstract

The invention relates to a driver circuit for transmitting data via a transmission line (a, b) to a receiver (2, 3). Said driver circuit comprises a controlled first switch element (M1) that links the transmission line (a, b) with a supply voltage (VCC) or with ground (GND) in order to modulate the voltage on the transmission line (a, b) in accordance with the data to be transmitted. A first coupling element (M2) is connected in parallel to the first switch element (M1) and receives the current flowing across the first switch element (M1) as long as the first switch elements (M1) is blocked. The first coupling element is a controlled second switch element (M2) with an adjustable internal resistance, thereby allowing adjusting the desired voltage on the transmission line (a, b) at low power dissipation.

Description

description

driver circuit

The invention relates to a driver circuit for data transmission via a transmission line to a receiver according to the preamble of claim 1.

Two-wire bus systems are known in which a so-called master communicates bidirectionally with two so-called slaves via a bus with two lines, the master also supplying the slaves with power via the bus.

The data transmission from the master to the individual slaves takes place by modulating the voltage prevailing on the two bus lines, so that the bus has alternating high-voltage phases and low-voltage phases in accordance with the data to be transmitted.

The voltage prevailing on the bus lines is modulated by two transistors which connect the two bus lines to a supply voltage or to ground. A resistor is connected in parallel to each of the two transistors, which takes over the current previously flowing through the transistors when the transistors are blocked, the voltage drop across the resistors corresponding to the desired voltage swing on the bus lines. Finally, the master has a current source which is arranged between the two bus lines and drives a cross current between the two bus lines.

In the high-voltage phase, the two transistors are controlled to be conductive, so that one bus line assumes the potential of the supply voltage, while the other bus line assumes ground potential. In contrast, the two transistors are controlled in a non-conductive manner in the low voltage phase. ^'In this state, flows from the supply voltage across the voltage-side resistor, arranged between the two bus lines power source and the ground-side resistor, a shunt current, which determines the voltage level on the two bus lines. The potential of one bus line then corresponds to the voltage drop across the voltage-side resistor, while the potential of the other bus line corresponds to the voltage drop across the ground-side resistor. The cross current flowing in the low voltage phase is made up of the current driven by the current source and the load currents of the slaves connected to the bus. As a result, the current source arranged in the master has to drive more current during the low-voltage phases, the less

Slaves are connected to the bus. Thus, the current source arranged in the master only has to make a small contribution to the required cross current when operating numerous slaves, whereas when only one slave is operated, a considerable current has to be driven by the current source in order to set the desired voltage swing on the bus lines.

A disadvantage of the known driver circuit is the fact that the current source in the master must be able to drive a considerable cross current between the two bus lines in order to set the desired voltage swing on the bus lines even when a single slave is operating. The high cross currents thus required when operating a single slave are, however, associated with a corresponding power loss, which is implemented in the two resistors and in the current source and causes thermal problems.

The invention is therefore based on the object of improving the known driver circuit described above ensure that even when operating a single slave, the power loss in the master is as low as possible.

Starting from a known driver circuit for data transmission according to the preamble of claim 1, the object is achieved by the characterizing features of claim 1.

The invention encompasses the general technical teaching of using a controllable switching element with an adjustable resistor instead of the two resistors for coupling the two bus lines during the low-voltage phase. The volume resistance of this switching element is then set so that the desired voltage is established on the bus during the low voltage phases.

When numerous slaves are operated, a relatively low resistance of this switching element is set, since in this case the slaves draw a relatively large current through the bus, which also leads to a correspondingly large voltage drop across the switching element.

In contrast, when a single slave is operated, a relatively large resistance of the switching element is set, since a single slave draws only relatively little current over the bus, so that only a relatively large resistance leads to the desired voltage drop across the switching element.

A particular advantage of the solution according to the invention is that only a relatively low power loss is required to generate the desired voltage levels during the low-voltage phase, so that no thermal problems occur.

A measuring device is preferably provided for detecting the current flowing via the transmission line, the measuring device on the output side with the modulation input. direction is connected to the internal resistance of the driver circuit in accordance with the above ^'the transmission line current flowing set.

In the preferred embodiment of the invention, the measuring device has a sampling circuit which samples the current flowing over the transmission line with a predetermined sampling period, the sampling period preferably being equal to the data transmission rate on the transmission line. The scanning circuit therefore scans the current flowing over the transmission line preferably shortly before a switch from the high voltage phase to the low voltage phase, so that the current flowing through the transmission line does not jump when switching from the high voltage phase to the low voltage phase. This is advantageous because an abrupt change in the current flowing through the transmission line is associated with undesired interference radiation.

The measuring device therefore preferably has a storage element, for example in the form of a capacitor, in order to temporarily store the measured value of the current flowing through the transmission line during the high voltage phase during the low voltage phase, which ensures that the current flowing through the transmission line is essentially constant during the low voltage phases remains.

In the preferred embodiment of the invention, a regulator is provided in order to regulate the internal resistance of the driver circuit.

This controller is preferably connected to the measuring device on the input side in order to regulate the internal resistance of the driver circuit as a function of the current flowing via the transmission line. In addition, the controller preferably has a reference voltage element which defines the desired voltage swing for the voltage modulation in order to regulate the internal resistance of the driver circuit in such a way that the voltage modulation takes place with the predetermined voltage swing.

The invention is not limited to data transmission between a master and several slaves. Rather, the invention can be used wherever a transmitter sends one or more receivers data over a transmission line, the transmission line being used in addition to the data transmission also for the power supply of the receiver.

Other advantageous developments of the invention are characterized in the subclaims or are shown below together with the description of the preferred embodiment of the invention with reference to the figures. Show it:

1 shows a bus system with a master and several slaves, FIG. 2a shows a pulse diagram of the voltage on the bus lines, FIG. 2b shows a pulse diagram of the current through the bus lines,

3 shows the driver circuit of the master as a block diagram, FIGS. 4 and 5 modifications of the driver circuit from FIG. 3.

The bus system shown in FIG. 1 enables communication between a master 1 and several slaves 2, 3 via a bus consisting of two lines a, b, only two slaves 2, 3 being shown as examples.

For data transmission from master 1 to slaves 2, 3, master 1 has two transmitters 4, 5, each of which modulates the voltage on one of the two bus lines a, b. In this case, the data is transmitted digitally by means of a biphasic code, FIG. 2a exemplarily showing a signal sequence 6 for line a and a signal sequence 7 for line b. It can be seen from the pulse diagram in FIG. 2a that a logic zero is represented by a LOW level on line a and a HIGH level on line b. A logical one, on the other hand, is generated in that line a first assumes a HIGH level and then changes to a LOW level, whereas line b initially assumes a LOW level and then changes to a HIGH level. A HIGH level on line a corresponds to a voltage of 13 V, while a LOW level corresponds to a voltage of 12 V, which leads to a voltage swing of ΔU = 1 V. However, the invention is not limited to the voltage levels mentioned above, but can also be implemented with other voltage levels. Instead of a biphasic code, other codes can also be used for data transmission.

Furthermore, the master 1 has a receiver 8 connected to the two lines a, b in order to receive data from the slaves 2, 3. The data transmission from the slaves 2, 3 to the master 1 takes place here by modulating the current flowing over the lines a, b. For this purpose, the sending slave 2 or 3 changes the electrical current flowing over the lines a and b by adding a signal current to the power supply of the slaves 2, 3 in addition to the normal load current I _LA sτ = 50 mA

mA is drawn over lines a and b. A pulse sequence 9 of the current flowing via lines a, b is shown as an example in FIG. 2b.

Finally, the master 1 also has a control and evaluation logic 10, which controls the two transmitters 4, 5 and the receiver 8 and evaluates the data received by the receiver 8. The driver circuit shown in FIG. 3 firstly modulates the electrical voltage on line a in order to transmit data from the master to the slaves.

On the other hand, the driver circuit shown in FIG. 3 has the task of adjusting the internal resistance of the driver circuit during the low-voltage phases on lines a and b in such a way that the desired voltage level on the lines results from the electrical current flowing off via lines a and b a, b sets. For example, the electrical voltage during the high voltage phases on line a U _HIGH = 13 V and on line b U _HIGH ~ 0V, whereas the voltage during the low voltage phases on line a U _L ow = 12V and on line b U _L ow = lV. The voltage swing on lines a and b is therefore

.DELTA.U = 2V. In the driver circuit according to the invention, the voltage swing on lines a and b is therefore significantly less than in conventional driver circuits with a voltage swing of 5 V, which advantageously contributes to a reduction in the interference radiation. The driver circuit shown in FIG. 3 must therefore have its internal resistance as a function of the total current

Set so that the desired voltage U _LO ⁼ 12 V or U _LO w = l V appears on lines a and b in the low voltage _phases .

It is particularly advantageous in the driver circuit _according to the invention that the normal load current I _LAΞT for _supplying power to the slaves not only flows on lines a and b during the high-voltage _phases , as in conventional driver circuits, but also during the low-voltage _phases . In the case of signal transmission from the master to the slaves, the current swing .DELTA.l is therefore smaller than in conventional driver circuits, which, in addition to the reduced voltage swing described above, leads to a reduction in the interference radiation. In order to modulate the voltage on lines a and b, the driver circuit shown in FIG. 3 has a transistor Ml, the gate connection of which is connected to a signal source S2 which, depending on the information to be transmitted, makes transistor Ml either conductive or non-conductive controls. Signal source S2 thus generates a HIGH level when high voltages are to be transmitted, whereas signal source S2 generates a LOW level when low voltages are to be transmitted ^" . The drain connection of transistor Ml is via a low-resistance resistor

Rl = l Ω connected to a supply voltage VCC = 13 V, while the source connection of transistor Ml is connected to line a. When transistor Ml is turned on, line a thus assumes a HIGH level. The signal source S2 is only shown schematically here and specifies the data to be transmitted from the master to the slaves.

Furthermore, the driver circuit has a transistor M2, the source connection of which is connected to the drain connection of the transistor Ml, while the drain connection of the transistor M2 is connected to the source connection of the transistor Ml and is therefore connected to the line a , The transistor M2 has the task of taking over the current flowing via the line a during the low-voltage phases in which the transistor M1 is blocking.

During the high voltage phases on line a, transistor Ml conducts, while transistor M2 blocks, so that the following voltage is present on line a:

U _H1GH = VCC- {I _LAST + I _SIGNAL + I _REF ,) - R \ = VCC = + 13V

The voltage on line a therefore essentially corresponds to the supply voltage VCC during the high voltage phases. In contrast, during the low-voltage phases on line a, transistor M1 blocks, while transistor M2 is operated as a variable resistor in order to adjust the internal resistance of the driver circuit during line in the low-voltage phases so that on line a independently of that via line a flowing current the desired voltage Uι, o ⁼ +12 V appears. The control of the transistor M2 will be described in detail later.

When switching between the high-voltage phase and the low-voltage phase, the driver circuit ensures that the current flowing via line a does not lead to excessively high voltage changes. For this purpose, the drain connection of transistor Ml is connected to the inverting input of a differential amplifier AI via a high-resistance resistor R2 = 40 kΩ. Between the resistor R2 and the inverting input of the differential amplifier AI branches off a constant current _source I _REF ι, which is connected to ground GND, the constant current _source I _REFI a current of

Dl I Q

I∞n = ISKML ^• = I∞NΛL '^ = 20w4 ^• 0.000025 = 0.5 μA R2 40ÄΩ

generated .

The voltage is therefore at the inverting input of the differential amplifier AI

U_ = VCC - {I _LAST - I _REF ) • Rl - I _REF ^■ R2

Dl 2

= VCC - I _usτ ^■ Rl + I _S1GNAL ^• —— - I _SIGNAL 'Rl

»Vcc- (iu _Sr + ι _SKMU ) .m =

= \ 3V - {50mA + 20mA) - 1Ω = 12.93

on . The voltage U_ present at the inverting input of the differential _amplifier AI thus reflects the current I _ΞIGNAL + I _LAST on line a. The non-inverting input ^'of the differential amplifier AI, however, is connected to the drain terminal of a transistor M3, which is connected to ground GND by its source terminal. In addition, the non-inverting input of the differential amplifier AI is connected to the supply voltage VCC via a resistor R3 = 50 Ω. The voltage is therefore at the non-inverting input of the differential amplifier AI

U ₊ = VCC- I _DM3 - R3

on.

The output of the differential amplifier AI, however, is connected to the gate terminal of the transistor M3, which causes feedback to the non-inverting input of the differential amplifier AI, as will be described below. The differential amplifier AI drives the transistor M3 in such a way that the voltage difference at the inputs of the differential amplifier AI is always zero. So the following must apply:

U ₊ = U_ = VCC - I _Dm - R3 = VCC - (I _SIGNAL + I _LASr ) • Rl

^ 'DM3 ⁼ V LAST ⁺ ' SIGNAL) ^'" 7

= (20mA + 50mA) • - ^ - = 1.4mA '50Ω

The voltage drop across the resistor R3 is therefore equal to the voltage drop across the resistors R1 and R2 in the regulated state, while the drain current I _DM3 through the transistor M3 is equal to the sum of the load current I _LAST and the signal current I _S I _GNA .

The feedback through the differential amplifier AI therefore leads to the drain currents I _DM1 and I _{DM3 of} the transistors ω> NJ M

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Furthermore, the driver circuit has a reference voltage element VREF1, which generates a reference voltage ΔU = 1 V, which is equal to the desired voltage swing. The reference voltage element VREF1 is connected to the supply voltage VCC and to the inverting input of a further differential amplifier A2, so that the desired voltage U _LO w = VCC-ΔU is present on the inverting input of the differential amplifier A2 during the low voltage phases on line a. The output of the differential amplifier A2 is connected to the gate connection of a transistor M5, the source connection of the transistor M5 being connected to the supply voltage VCC, while the drain connection of the transistor M5 is connected to ground GND via a further transistor M4. In addition, the drain connection of the transistor M5 is connected to the non-inverting input of the differential amplifier, so that the source-drain voltage of the transistor M5 is present at the non-inverting input of the differential amplifier. The feedback of the output of the differential amplifier A2 to the non-inverting input of the differential amplifier A2 has the consequence that the source-drain voltage of the transistor M5 in the steady state is equal to the desired voltage swing ΔU for the voltage modulation. In addition, the output of the differential amplifier A2 is also connected to the gate terminal of the transistor M2, the area ratio A _M5 / A _{M2 of} the transistors M2 and M5 being equal to the ratio R3 / Rl = 50 of the resistors Rl and R3. As a result, the differential amplifier A2 drives the transistor M2 in such a way that the same voltage ΔU = 1 V drops across the transistors M2 and M5, which corresponds to the desired voltage swing on line a. During the low voltage phases on line a with transistor Ml open, line a has the following voltage:

^U _LOW - VCC - XU - (I _LAST + I _SIGNAL + I _KEF] ) • Rl = VCC - AU The activation of the transistor M2 by the differential amplifier thus ensures that the desired voltage level U _LO = 12V is established on line a during the low voltage phases.

The following describes how the buffering of the voltage present in the capacitor C1 during the high-voltage phase at the gate terminal of the transistor M3 prevents the current flowing via line a from jumping from the high-voltage phase to the low-voltage phase when switching over ,

For this purpose, the drain connection of transistor M6 is connected to the gate connection of a transistor M4, the source connection of transistor M4 being connected to ground GND, while the drain connection of transistor M4 is connected to the drain connection of the transistor M5 is connected.

The gate voltage of the transistor M3 buffered in the capacitor C1 thus drives the transistor M4. For the drain current I _DM4 through the transistor M4 it follows from the predetermined area ratio A _M4 / A _M3 = 1 of the transistors M4 and M3 and the drain current I _DMI :

( _τ 40 & Ω _c 1Ω

⁼ [ ^{IuΛ + would be} ^"5μΛ ) 50Ω

= (l _Dm + 20mA) - ^

The drain current I _DM4 through transistor M4 is therefore directly related to the drain current I _DM1 through transistor Ml, which is equal to the current flowing via line a. Furthermore, the gate voltage of transistor M2 determines the drain current I _DM5 of transistor M5. The buffering of the gate voltage of the transistor M4 by the capacitor C1 therefore not only prevents sudden changes in the drain current I _DM4Λ but also counteracts sudden changes in the current flowing through line a due to the above-mentioned functional relationship between the drain currents I _DM and I _DM1 .

Be 4 shows an alternative embodiment of the OF INVENTION ^¬ to the invention the driver circuit, which largely corresponds with the embodiment described above, so that used hereinafter the same reference numerals and reference is made to avoid repetition of the foregoing description of FIG. 3

In the following, the additional components of the driver circuit according to FIG. 4 are described first, in order to subsequently explain the functioning of the additional components with reference to the description of the structural structure.

The driver circuit according to FIG. 4 additionally has a transistor M9, the gate connection of which is connected to the drain connection of the transistor Mβ, while the source connection of the transistor M9 is connected to ground.

Furthermore, the driver circuit according to FIG. 4 additionally has a transistor M8, the source connection of which is connected to the reference voltage element VREF1 and to the drain connection of the transistor M9, while the drain connection of the transistor M8 via a resistor R4 = R3 / 2 = 250 Ω is connected to the supply voltage VCC. By contrast, the gate connection of transistor M8 is connected to an additional voltage source Vg, the voltage of which is equal to the maximum value of the voltage supplied by signal source S2. In addition, the resistor R4 connects the supply voltage VCC to the source terminal of the transistor M5. The transistors M4 and M9 and the transistors M5 and M8 preferably have the same transistor area A _M4 = A _M 9 or _M 5 = AM8.

The function of the additional components of the driver circuit shown in FIG. 4 will now be explained with reference to the description above.

Thus, the current flowing through line ^" a causes a voltage drop across transistor Ml and at R1. The voltage shift caused thereby is compensated by resistor R4 and transistors M8 and M9. Thus, flow through transistor M5 and through transistor M8 currents with the same amplitude, which means that the mean values of the voltages on line a shift depending on the current flowing via line a, whereas the modulation stroke advantageously remains almost constant.

FIG. 5 shows an alternative exemplary embodiment of the driver circuit according to the invention, which largely corresponds to the exemplary embodiment described above, so that the same reference numerals are used in the following and reference is made to the above description of FIG. 4 in order to avoid repetition.

The decisive difference between the driver circuit according to FIG. 5 and the exemplary embodiments described above is that the transistor M1 is omitted, so that the connection to the line a takes place exclusively through the transistor M2. This has the advantage that only a single power transistor is required.

In the following, the additional components of the driver circuit according to FIG. 5 are first described, in order to then explain the functioning of the additional components with reference to the description of the structural structure. The gate connection of the transistor M2 is connected to the output of the differential amplifier A2 via a switching element consisting of two transistors Mll, M12, the source connections of the two transistors Mll, M12 being connected together, while the two gate connections of the transistors Mll, M12 can be controlled by the signal source S2.

Furthermore, the driver circuit has two transistors M9 and MIO, the drain connection of transistor M9 being connected to the gate connection of transistor M2, while the two source connections of transistors M9, MIO are connected to one another. The drain connection of the transistor MIO is finally connected to ground via a voltage source Vgl.

Finally, the driver circuit also has an inverter Inl, which connects the signal source S2 to the gate connections of the two transistors M9, MIO.

The functional specialty of the driver circuit shown in FIG. 5 is that the gate voltage of the transistor M2 is switched over. This is done by transistors Mll, M12 and by transistors M9, MIO. In the high voltage phase, transistor M2 is switched through with low resistance, whereas in the low voltage phase transistor M2 is controlled to a defined resistance R _DS between the source connection and the drain connection.

However, the driver circuit according to the invention described above is not limited to the components described above with regard to its circuitry implementation, since, for example, other transistor types can be used.

Finally, it should also be mentioned that the transmitter 5 shown in FIG. 1 for line b is analogous to that above Driver circuit described is constructed so that a detailed description of the driver circuit of the transmitter 5 is unnecessary and in this regard reference is made to the above description.

The embodiment of the invention is also not limited to the preferred exemplary embodiments specified above. Rather, a number of variants are conceivable which make use of the solution shown, even in the case of fundamentally different types.

Claims

claims

1. Driver circuit for the transmission of data via a transmission line (a, b) to a receiver (2, 3), with

a controllable first switching element (M1) which connects the transmission line (a, b) to a supply voltage (VCC) or to ground (GND) in order to modulate the voltage on the transmission line (a, b) in accordance with the data to be transmitted,

a first coupling element (M2) connected in parallel to the first switching element (Ml), which takes over the current flowing through the first switching element (Ml) as long as the first switching element (Ml) is blocking,

characterized,

that the first coupling element is a controllable second switching element (M2) with an adjustable internal resistance in order to be able to set the desired voltage on the transmission line (a, b) with low power loss.

2. Driver circuit according to claim 1, d a d u r c h g e k e n n z e i c h n e t,

that a first transmission line (a) and a second transmission line (b) are provided,

wherein the first transmission line (a) is connected to the supply voltage (VCC) by a parallel connection of the first switching element (M1) and the second switching element (M2),

while the second transmission line (b) is connected in parallel from a third switching element to the voltage dulation and a fourth switching element with an adjustable internal resistance to ground ^' (GND) is connected.

3. Driver circuit according to claim 2, that a controllable current source is arranged between the two transmission lines in order to drive a cross current through the second switching element and the fourth switching element during the low voltage phases on the transmission lines.

4. Driver circuit according to claim at least one of the preceding claims, characterized in that a measuring device (AI, Mβ, M7, Cl, R2, I _REFI ) is provided for detecting the current flowing via the transmission line (a, b), the measuring device being output - tig is connected to the second switching element and / or the fourth switching element in order to adjust their internal resistance in accordance with the current flowing through the transmission line (a, b).

5. Driver circuit according to claim 4, so that the measuring device has a sampling circuit (Sl, M7, M6) in order to sample the current flowing over the transmission line (a, b) with a predetermined sampling period.

6. Driver circuit according to claim 5, that the sampling period is substantially equal to the data transfer rate.

7. Driver circuit according to at least one of claims 4 to 6, characterized in that that the measuring device comprises a storage element (Cl) to the measured value of the latch while the ^'high voltage phases via the transmission lines (a, b) current flowing during the low voltage phase.

8. Driver circuit according to claim 7, d a d u r c h g e k e n n z e i c h n e t that the memory element is a capacitor (Cl).

9. Driver circuit according to at least one of claims 2 to 7, that a controller (M5, A2, VREF1) is provided for regulating the internal resistance of the second switching element and / or the fourth switching element.

10. Driver circuit according to claim 9, so that the controller is connected on the input side to the measuring device in order to regulate the internal resistance as a function of the current flowing via the transmission line (a, b).

11. Driver circuit according to claim 9 or 10, so that the controller has a reference voltage element (VREF1), the output voltage of which is equal to the desired voltage swing on the transmission line (a, b) modulation in order to set the internal resistance in accordance with the desired voltage swing.

12. Driver circuit according to at least one of the preceding claims, that the modulation stroke of the voltage on the transmission line is less than twice the diode voltage.