JPH06302810A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a turn-off gain by a method wherein a plurality of stripe- shaped cathode regions and isolation regions which are formed inside a base region are connected by a cathode electrode and most of a displacement current generated at the lower part of the cathode electrode in a turn-off operation is made to flow to the cathode electrode via the isolation regions. CONSTITUTION:A distance from the tip of a comb-shaped gate electrode 27 in a most distance position from a pad 30 for bonding is designated as L1, and distances from the tip of the comb-shaped gate electrode 27 up to a p-type isolation region 25 are designated sequentially as L2, L3,...Li, Li+1,...Ln as they are brought close to the pad 30 for bonding. Then, they are formed so as to be L1<=Li+1L, where (1) and (n) are natural numbers and (i) represents an arbitrary number which is (n) or lower. Thereby, the sum of a gate pulling-out part current and a displacement current in a turn-off operation is averaged, and it is possible to prevent an element from being destroyed when a current is concentrated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a thyristor and a transistor, and more particularly to a semiconductor device having a structure for preventing element destruction.

[0002]

2. Description of the Related Art Thyristors and transistors are widely used for power control and switching as the most basic semiconductor devices. In addition to demands for improvement of switching characteristics and reduction of loss, particularly for power semiconductor devices that control large power, research for preventing element breakdown has become important. Below, we pick up general thyristors,
The structure and operation will be described with reference to FIGS. 6 and 7.

FIG. 6 is a view of the thyristor viewed from above, showing the structure of the electrodes. Then, AA ′ in FIG.
The cross-sectional structure of the thyristor taken along the line is shown in Fig. 7.
FIG. 7B is a sectional view taken along line BB ′ in FIG.

In FIG. 6, a gate electrode 6 and a cathode electrode 7 are formed on the upper surface of the thyristor so as to be electrically insulated by a silicon oxide film 5 and interdigitated in a comb shape. A gate bonding pad 9 is formed on the end of the gate electrode 6, and a cathode bonding pad 10 is formed on the end of the cathode electrode 7. Note that the passivation for protecting the gate electrode 6 and the cathode electrode 7 is omitted in order to make the drawing easy to see.

A section taken along the line AA 'of FIG. 6, that is, FIG. 7 (a)
In FIG. 3, an n ⁻ type base region 2 is formed on the upper surface of the p ⁺ type anode region 1, and a p type gate region 3 is formed on the surface portion of the n ⁻ type base region 2. An n ⁺ type cathode region 4 is selectively formed on the surface of the p type gate region 3. Further, a gate electrode 6 is formed in contact with the surface of the p-type gate region 3.
A cathode electrode 7 is formed so as to be connected to the surface of the n ⁺ type cathode region 4, and the cathode electrode 7 extends to the upper surface of the silicon oxide film 5 formed on the surface of the p type gate region 3. There is. Further, the anode electrode 8 is uniformly formed on the lower surface of the p ⁺ -type anode region 1.

On the other hand, the BB 'cross section of FIG. 6, that is, FIG.
In FIG. 7B, similar to FIG. 7A, the p ⁺ type anode region 1, the n ⁻ type base region 2, and the p type gate region 3 are formed.
Are formed. Then, in the p-type gate region 3,
Unlike FIG. 7A, no other semiconductor region is formed. Further, a gate electrode 6 is formed in contact with the surface of the p-type gate region 3. A cathode electrode 7 is formed on the upper surface of the silicon oxide film 5 formed on the surface of the p-type gate region 3. Further, the anode electrode 8 is uniformly formed on the lower surface of the p ⁺ -type anode region 1.

Next, the operation of the thyristor having the above structure will be described. The turn-on operation is performed by flowing a gate current from the gate electrode 6. That is, the gate current is n ⁺
When electrons are caused to flow from the type cathode region 4 into the n ⁻ type base region 2 and the electrons flowing into the n ⁻ type base region 2 reach the junction surface with the p ⁺ type anode region 1, p
Holes are injected from the ⁺ type anode region 1 to the n ⁻ type base region 2. This hole is n ⁺ type cathode region 4 to n
^- now to promote electrons flowing into type base region 2, the thyristor latch-up.

The turn-off operation is performed by drawing a gate current from the gate electrode 6 (flowing a current in the opposite direction to that at turn-on). That is, the n ⁻ type base region 2
Excess holes accumulated in the n ^- type base region 2 and p-type gate region 3 are extracted from the gate electrode 6 through the p-type gate region 3.
A depletion layer is formed at the pn junction with the mold gate region 3 to release the latch-up state, shut off the main current between the anode and cathode, and turn off the thyristor.

[0009]

In the above thyristor, as shown in FIGS. 6 and 7, the n ⁺ type cathode region 4 is formed only below the plurality of protrusions of the cathode electrode 7, and On the right side, the p-type gate region 3 is insulated below the cathode electrode 7 by the silicon oxide film 5.
Are formed. Then, a gate capacitance is generated in the p-type gate region 3 formed below the cathode electrode 7.

By the way, the anode voltage increases when the thyristor is turned off. Then, as the anode voltage rises, a displacement current C · dv / dt is generated. (C
Is the gate capacitance, and dv / dt is the time change rate of the anode voltage. Here, the displacement current generated in the vicinity of the p-type gate region 3 formed below the gate electrode 6 is almost evenly distributed in the gate electrode 6. Although flowing, the displacement current generated in the vicinity of the p-type gate region 3 formed below the cathode electrode 7 concentrates and flows into the tip portion of the gate electrode 6 which is the electrode closest to that position.

Therefore, at the time of turn-off, the anode
In addition to the current extraction for turning off between the cathodes, the displacement current must also be extracted together. Therefore, unless a large amount of current corresponding to the displacement current is drawn out from the gate electrode 6, it is not turned off and the turn-off gain deteriorates.

Further, as described above, the displacement current generated in the vicinity of the p-type gate region 3 formed below the cathode electrode 7 concentrates at the tip of the gate electrode 6, but
The tip of the gate electrode 6 is the farthest position from the gate bonding pad 9, and is a position where the extraction current is likely to concentrate at the time of turn-off. This is because the voltage drop due to the gate electrode 6 increases as the distance from the gate bonding pad 9 increases. That is, a sufficient gate current can be extracted near the gate bonding pad 9,
In the portion far from the gate bonding pad 9, sufficient gate current cannot be extracted due to the voltage drop.
Therefore, at the time of turn-off, the thyristor gradually turns off from the vicinity of the gate bonding pad 9,
Finally, only the thyristor near the tip of the comb-shaped gate electrode 6 farthest from the gate bonding pad 9 remains in the ON state, and the current concentrates there.

As described above, since the displacement current is further applied to the portion where the current is concentrated at the time of turn-off, there is a problem that the element is apt to be destroyed by the overcurrent. The present invention solves the above problems, and an object thereof is to realize a semiconductor device that improves turn-off characteristics and prevents element breakdown due to current concentration.

[0014]

A semiconductor device according to claim 1, wherein a second conductivity type base region is formed on an upper surface of the first conductivity type anode region, and the first conductivity type is formed on a surface portion of the base region. A first conductive type isolation region is formed at a position spaced apart from the gate region by a predetermined distance, and a plurality of second conductive type cathode regions are formed in stripes on the surface of the gate region. Assumption.

The semiconductor device has a comb-shaped cathode electrode formed to be connected to each cathode region and the separation region, and a cathode electrode connected to the gate region and electrically insulated from the cathode electrode. It has a comb-shaped gate electrode formed intricately with each other, and a bonding pad on the upper surface of the gate electrode. The distance from the tip of the comb-shaped gate electrode farthest from the bonding pad to the separation region is L _1, and the distance from the tip of the comb-shaped gate electrode to the isolation region is closer to the separation region. The distances to the separation regions are L ₂ , L ₃ , ..., L _i , L in order.
_It is formed so that L _i ≦ L _{i + 1} when _{i + 1} , ..., L _n . (I and n are natural numbers, i is n
The semiconductor device according to claim 2 or 3 is basically the same as the semiconductor device according to claim 1, but the semiconductor device according to claim 1 has a pnpn structure or an npnp structure. Whereas the semiconductor device according to claim 2 is pn
It is a p structure or an npn structure. In addition, the separation area, electrode shape, and the distance from the comb-shaped electrode to the separation area are
This is the same as the semiconductor device according to claim 1.

[0016]

In the semiconductor device according to claim 1, the gate region is formed on the surface of the base region, and the isolation region of the same conductivity type as the gate region is formed at a predetermined distance from the gate region. is doing. Since the separation region and a plurality of stripe-shaped cathode regions formed in the base region are connected by the cathode electrode, most of the displacement current generated under the cathode electrode at turn-off is the separation region. Through the cathode electrode. As a result, the displacement current flowing to the gate electrode via the gate region is reduced, and the turn-off gain is improved.

Further, the smaller the distance L _i from the tip of the comb-shaped gate electrode to the separation region, the easier the displacement current flows into the separation region side, and the smaller the ratio of the displacement current flowing into the gate electrode side. Therefore, in the semiconductor device according to claim 1, since it is formed so that L _i ≦ L _{i + 1} , the inflow of the displacement current into the gate electrode becomes smaller as the distance from the bonding pad becomes larger. Become. Here, as the distance from the bonding pad increases, the gate extraction current tends to concentrate at turn-off, so the sum of the gate extraction current and the displacement current is averaged at each tip of the comb-shaped gate electrode. Current concentration is alleviated. As a result, element breakdown due to current concentration can be prevented.

Also in the semiconductor device according to the second or third aspect, element breakdown due to current concentration can be prevented by the same operation as the semiconductor device according to the first aspect.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view of a thyristor according to an embodiment of the present invention as viewed from above. 2A is a sectional view when the thyristor is cut along the line CC ′ of FIG. 1, and FIG. 2B is a sectional view when the thyristor is cut along the line DD ′. Is.

In FIG. 1, a gate electrode 27 and a cathode electrode 28 are formed on the upper surface of the thyristor by the silicon oxide film 2.
While being electrically insulated by 6, they are formed in a comb shape so as to be intertwined with each other. A gate bonding pad 30 is formed on the lower left end of the gate electrode 27, and a cathode bonding pad 31 is formed on the lower right end of the cathode electrode 28. These bonding pads are connected to predetermined pins of the package by leads (not shown). Note that the passivation for protecting the gate electrode 27 and the cathode electrode 28 is omitted in order to make the drawing easy to see.

A cross section taken along the line CC 'of FIG. 1, that is, FIG.
In, the n ⁻ type base region 22 is formed on the upper surface of the p ⁺ type anode region 21. The n ⁻ type base region 22 is formed by, for example, epitaxial growth. A p-type gate region 23 is formed on the surface of the n ⁻ -type base region 22, and the p-type gate region 23 is formed.
A p-type isolation region 25 is formed at a predetermined distance from. These p-type gate region 23 and p-type isolation region 25
Is formed by selectively removing the silicon oxide film uniformly formed on the surface of the n ⁻ type base region 22 and thermally diffusing the p type impurities using the oxide film as a mask. An n ⁺ type cathode region 24 is selectively formed on the surface of the p type gate region 23. This n ⁺ type cathode region 24
Is formed by thermally diffusing n-type impurities.

Further, a gate electrode 27 is formed in contact with the surface of the p-type gate region 23. Further, a cathode electrode 28 is formed so as to be connected to the surfaces of the n ⁺ type cathode region 24 and the p type isolation region 25, and is electrically insulated from the other semiconductor regions by the silicon oxide film 26. Further, the anode electrode 29 is uniformly formed on the lower surface of the p ⁺ type anode region 21. Each electrode is made of aluminum.

On the other hand, the DD 'cross section of FIG. 1, that is, FIG.
In FIG. 2B, similar to FIG. 2A, the p ⁺ type anode region 21, the n ⁻ type base region 22, and the p type gate region 2 are formed.
3 and the p-type isolation region 25 are formed. However, in the DD ′ cross section, unlike the CC ′ cross section, p
No other semiconductor region is formed in the mold gate region 23.

Further, a gate electrode 27 is formed on the surface of the p-type gate region 23, and a cathode electrode 28 is formed on the surface of the p-type isolation region 25. The gate electrode 27 and the cathode electrode 28 are the silicon oxide film 26.
Are electrically isolated from each other. Further, the anode electrode 29 is uniformly formed on the lower surface of the p ⁺ -type anode region 21.
Are formed.

Returning to FIG. In the figure, a region surrounded by a broken line is a position where the p-type isolation region 25 of FIG. 2 is formed, and the p-type isolation region 25 is electrically connected to the cathode electrode 28. Further, the comb-shaped gate electrode 27 has four protrusions E, F, G, and H, and the length of each protrusion is the distance from the gate bonding pad 30. Depending on. That is, the protruding portion E located farthest from the gate bonding pad 30 is formed to be long, and the protruding portion F,
It is formed to be shorter in the order of G and H. Therefore, the tips of the protrusions of the comb-shaped gate electrode 27 and the p-type isolation region 25 are formed.
When the distances from the protrusions E, F, G and H to the p-type isolation region 25 are L ₁ , L ₂ , L ₃ and L ₄ , respectively, L ₁ ≦ L ₂ ≦ L ₃ ≦ It becomes L ₄ .

In this embodiment, the number of protrusions of the comb-shaped gate electrode 27 is four, but in reality, many protrusions are formed.
If the number is n, the gate bonding pad 30
The distance between the p-type isolation region 25 and the projecting portion furthest from is set to L ₁ , and the gate bonding pad 30
When the distance from each protruding portion to the p-type isolation region 25 is sequentially set to L ₂ , L ₃ , ..., L _n-1 , L _n , as L ₁ ≤L ₂ ≤ ... ≤L It can be represented by a general formula of _n-1 ≤ L _n .

Next, the operation of the thyristor having the above structure will be described. The turn-on operation is similar to that of a conventional thyristor. That is, a gate current is caused to flow from the gate electrode 27 to cause electrons to flow from the n ⁺ type cathode region 24 to the n ⁻ type base region 22, and the electrons flowing into the n ⁻ type base region 22 are p ⁺ type anode region 21. When it reaches the junction surface with, holes are injected from the p ⁺ -type anode region 21 to the n ⁻ -type base region 22. This hole promotes the inflow of electrons from the n ⁺ type cathode region 24 to the n ⁻ type base region 22, and the thyristor latches up.

Similarly to the conventional thyristor, the turn-off operation is also performed by drawing the gate current from the gate electrode 27 (flowing the current in the direction opposite to that at the time of turn-on). That is, excess holes accumulated in the n ⁻ type base region 22 are extracted from the gate electrode 27 via the p type gate region 23, and the n ⁻ type base region 22 and the p type gate region 23 are removed.
A depletion layer is formed at the pn junction between and to release the latch-up state. In this embodiment, in addition to the extraction of the gate current described above, excess holes in the n ⁻ type base region 22 are also discharged to the cathode electrode 28 through the p type isolation region 25. Therefore, the turn-off time is longer than that in the conventional thyristor. Shortened.

By the way, as described in the problem to be solved by the invention, the displacement current C · dv / dt is generated when the thyristor is turned off. Here, the p-type isolation region 25 formed under the cathode electrode 28
Since it also has a capacitance, a displacement current is also generated in the vicinity thereof, but the displacement current easily flows into the card electrode 28 at the closest position from that position. Therefore,
Most of the displacement current flows into the cathode electrode 28 via the p-type isolation region 25, and a small amount of displacement current flows into the gate electrode 27 via the p-type gate region 23. As a result, when pulling out the gate current at turn-off,
Since the displacement current that must be extracted from the gate electrode 27 is greatly reduced, the turn-off gain is improved.

Generally, as the distance from the gate bonding pad 30 increases, the current tends to concentrate at turn-off. This is due to the voltage drop in the gate electrode 27 made of aluminum as described above. Therefore, at the time of turn-off, the current is most likely to be concentrated at the tip of the protrusion E of the gate electrode 27, and the amount of current concentrated in the order of the protrusions F, G, and H is small.

By the way, the relationship between the distance from the tip of the protruding portion of the comb-shaped gate electrode 27 to the p-type isolation region 25 and the magnitude of the displacement current flowing into the tip of the protruding portion of the gate electrode 27 becomes smaller as the distance is smaller. , The displacement current is reduced. This is because the displacement current near the tip of the protruding portion of the gate electrode 27 flows to the cathode electrode 28 via the p-type isolation region 25 as the distance becomes smaller.

In the thyristor of this embodiment, the distance L ₁ between the protrusion E of the gate electrode 27 and the p-type isolation region 25, which is the largest distance from the gate bonding pad 30, is the smallest, and the gate bonding is performed. The distances L ₂ , L ₃ , and L ₄ between the protrusions F, G, and H and the p-type isolation region 25 increase in order as the pad 30 is approached. Therefore, in the vicinity of the protrusion E of the gate electrode 27 where the current concentration is most likely to occur at turn-off, the displacement current flows into the gate electrode 27 at the minimum, and the protrusions F, G, and H are sequentially concentrated at turn-off. Corresponding to the decrease in the discharge current, the ratio of the displacement current flowing into the gate electrode 27 increases. As a result, the sum of the gate extraction current and the displacement current at the protruding portion of each gate electrode 27 is averaged, current concentration is alleviated, and element breakdown due to current concentration can be prevented.

The present invention can be applied to a thyristor in which the conductivity type of each semiconductor region of the thyristor of the above embodiment is inverted, and the same effect can be obtained. Further, the shapes of the gate electrode 27 and the cathode electrode 28,
The positional relationship between the gate bonding pad 30 and the cathode bonding pad 31 on each of the electrodes 27 and 28 is not limited to the example shown in FIG. 1, but may be the structure shown in FIG. 3, for example. That is, each pad 3
0 and 31 are formed near the vertical centers of the electrodes 27 and 28, respectively, and the length of the protrusion of the comb-shaped gate electrode 27 becomes longer as the distance from the center increases in the vertical direction. Good.

Next, another embodiment of the present invention will be described. FIG. 4 is an example in which the present invention is applied to a bipolar transistor. 2 (a) and 2 (b) are shown in FIG. 2 (a) and 2 (a), respectively.
Corresponding to (b), the upper surface structure of this bipolar transistor is similar to that of FIG.

In FIG. 4A, the n ⁺ type semiconductor substrate 4
An n ⁻ type semiconductor region 42 is formed on the upper surface of 1 (collector), and ap type base region 43 and a p type isolation region 45 are formed on the surface portion of the n ⁻ type semiconductor region 42 at a predetermined interval. Has been done. The n ⁺ type emitter region 4 is selectively formed on the surface of the p type base region 43.
4 are formed. Further, the base electrode 47 is formed on the surface of the p-type base region 43, and the n ⁺ -type emitter region 4 is formed.
An emitter electrode 48 is formed on the surfaces of the 4 and p-type isolation regions 45. Here, the base electrode 47 and the emitter electrode 48 are electrically insulated by the silicon oxide film 46. A collector electrode 49 is uniformly formed on the lower surface of the n ⁺ type semiconductor substrate 41.

In FIG. 4B, similar to FIG. 4A, the n ⁻ type semiconductor region 4 is formed on the upper surface of the n ⁺ type semiconductor substrate 41.
2, p-type base region 43, and p-type isolation region 45 are formed. Then, a base electrode 47, an emitter electrode 48, and a collector electrode 49 are formed corresponding to the p-type base region 43, the p-type isolation region 45, and the n ⁺ type semiconductor substrate 41, respectively.

The turn-on operation and turn-off operation of this bipolar transistor are the same as those of a normal transistor controlled by a base current, and the principle of preventing current concentration during turn-off is the same as that of the thyristor described with reference to FIGS. .

FIG. 5 shows an example in which the present invention is applied to a static induction transistor (SIT). 4A and 4B respectively correspond to FIGS. 4A and 4B, and the upper surface structure of this SIT is the same as that of FIG.

In FIGS. 5A and 5B, an n ⁺ type semiconductor substrate 51 (drain) and an n ⁻ type semiconductor region 52 are formed.
Of the n ⁺ type semiconductor substrate 4 shown in FIGS. 4A and 4B, respectively.
1 and n ⁻ type semiconductor region 42. Also,
The p ⁺ type gate region 53 and the p ⁻ type channel region 54 are
The n ⁺ type source region 55 and the p ⁺ type isolation region 56 correspond to the p type base region 43 and the n ⁺ type emitter region 44 and the p type isolation region 45, respectively.

The present invention can also be applied to the transistor shown in FIG. 4 or 5 in which the conductivity type of each semiconductor region is inverted.

[0041]

As described above, according to the present invention,
Since the isolation region of the same conductivity type as the gate region is formed in the region below the cathode electrode where the cathode region is not formed, the amount of displacement current flowing into the gate electrode at turn-off is reduced, and the turn-off gain is improved.

Further, the distance between each protruding portion of the comb-shaped gate electrode and the above-mentioned isolation region is formed such that the one located far from the gate bonding pad is short and the one located near is long. The sum of the gate extraction current and the displacement current of 1 is averaged, so that element breakdown due to current concentration can be prevented.

[Brief description of drawings]

FIG. 1 is a view from above of a thyristor according to an embodiment of the present invention.

2 is a cross-sectional view of the thyristor of FIG. 1, (a) is C
A cross section taken along the line C'is shown in FIG.
A cross section taken along line D'is shown.

FIG. 3 is a top view of a thyristor according to another embodiment of the present invention.

FIG. 4 is a sectional view of a bipolar transistor according to another embodiment of the present invention.

FIG. 5 is a sectional view of a static induction transistor according to another embodiment of the present invention.

FIG. 6 is a top view of a conventional general thyristor.

7 is a cross-sectional view of the thyristor of FIG. 6, (a) is A
-A 'shows a cross section when cut by a line, and (b) shows B-
A cross section taken along line B'is shown.

[Explanation of symbols]

21 p ⁺ type anode region 22 n ⁻ type base region 23 p type gate region 24 n ⁺ type cathode region 25 p type isolation region 26 silicon oxide film 27 gate electrode 28 cathode electrode 29 anode electrode 30 gate bonding pad 31 for cathode bonding pad

Claims (3)

[Claims] 1. A second conductive film is formed on the upper surface of the first conductivity type anode region.
A conductive type base region is formed, a first conductive type gate region is formed on a surface portion of the base region, and a first conductive type isolation region is formed at a position spaced apart from the gate region by a predetermined distance. A semiconductor device in which a plurality of second conductivity type cathode regions are formed in a stripe shape on a surface portion, and a comb-shaped cathode electrode formed by connecting to each of the cathode regions and the separation region, and connected to the gate region. And a comb-shaped gate electrode that is electrically insulated from the cathode electrode and formed in intricate relation with the cathode electrode, and a bonding pad on the upper surface of the gate electrode. the distance from the tip of the gate electrode of the comb to the isolation region and L ₁ located farthest has been approaching to the bonding pad L _2, L ₃ in order to distance to the isolation region from the tip of the gate electrode of the comb _{Te, ···, L i, L i} + 1,
The semiconductor device is formed so that L _i ≦ L _{i + 1} when L _n . (I and n are natural numbers, and i represents any number less than or equal to n) 2. A base region of the second conductivity type and a separation region of the second conductivity type are formed on the surface of the collector region of the first conductivity type and at a position spaced from the base region by a predetermined distance. A semiconductor device in which a plurality of first conductivity type emitter regions are formed in a stripe shape on a surface portion, and a comb-shaped emitter electrode formed by connecting to each of the emitter regions and the isolation region and connected to the base region. And a comb-shaped base electrode that is electrically insulated from the emitter electrode and formed in intricate relation with the emitter electrode, and a bonding pad on the upper surface of the base electrode. Let L ₁ be the distance from the tip of the comb-shaped base electrode at the farthest position to the separation region, and as it approaches the bonding pad, The distance from the tip of the comb-shaped base electrode to the separation region is L ₂ , L ₃ , ..., L _i , L _{i + 1} , in order.
The semiconductor device is formed so that L _i ≦ L _{i + 1} when L _n . (I and n are natural numbers, and i represents any number less than or equal to n) 3. A surface portion of the drain region of the first conductivity type,
A plurality of second conductivity type channel regions are formed in stripes, a second conductivity type gate region surrounding the plurality of channel regions is formed, and a second conductivity type gate region is formed at a position spaced from the gate region by a predetermined distance. In a semiconductor device in which isolation regions are formed and a source region of the first conductivity type is selectively formed on the surface of each channel region, a comb shape formed by connecting to the source regions and the isolation regions is provided. Source electrode, a comb-shaped gate electrode connected to the gate region and electrically insulatively formed from the source electrode and intertwined with the source electrode, and a bonding pad on the upper surface of the gate electrode. has the door, the distance from the tip of the comb gate electrode located farthest from the bonding pad to said isolation region and L _1, said Bondin L ₂ toward the use pads from the tip of the gate electrode of the comb in turn a distance to the isolation _{region, L 3, ···, L i} , L i + 1,
The semiconductor device is formed so that L _i ≦ L _{i + 1} when L _n . (I and n are natural numbers, and i represents any number less than or equal to n)