JPH0630073A - Phase indeterminacy eliminator - Google Patents

Abstract

PURPOSE:To reduce an error in a transmission digital signal by detecting a frame pattern to be transmitted, and correcting the phase of a carrier outputted from a carrier generation circuit so as to detect a normal frame pattern. CONSTITUTION:A carrier phase correction means 2 corrects the phase of the carrier supplied from the carrier generation circuit 4 to a phase rotating circuit 3 so as to set the frame pattern detected by a frame pattern detecting means 1 as the normal frame pattern. In other words, when the phase of the carrier sent out from the carrier generation circuit 4 shows thetat+pi/2, thetat+pi, and thetat+3pi/2, the phase is corrected to thetat+0. When the carrier with phase of thetat+0 is inputted to the phase rotating circuit 3, a normal digital signal can be reproduced, and the normal frame pattern can be detected by the frame pattern detecting means 1. Thereby, the configuration of a demodulator can be simplified, and the error in the transmission digital signal can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase uncertainty removing device for removing an indefinite demodulation carrier phase of a quadrature amplitude modulation (QAM) signal demodulator using asynchronous detection.

[0002]

2. Description of the Related Art When transmitting a digital signal to a remote place, a method of modulating a carrier wave and transmitting it is generally used. Further, since the frequency band used for transmitting digital signals can be effectively used, QAM is widely used as a modulation method.

To demodulate a QAM signal, the received QAM
It is necessary to add a carrier wave synchronized with the carrier wave of the signal, and a carrier wave recovery circuit is used to reproduce this carrier wave. The phase of the carrier wave of the received QAM signal is 0, π / 2,
There are four types of phases, π and 3π / 2, but it is impossible to determine which phase the received QAM signal is,
In the carrier recovery circuit for the QAM signal, one of these four types is used.
Regenerate carrier wave synchronized with one phase.

When the phase difference between the phase of the carrier wave regenerated by the carrier wave regenerating circuit and the phase of the carrier wave of the received QAM signal is 0, the demodulated digital signal matches the original input digital signal, but there is a phase difference. The input and demodulation output digital signals do not match. For this reason, it is possible to transmit a signal having a differential logic with respect to a signal one symbol before the transmitted input signal and obtain an original digital signal having a dedifferentiation logic with a signal one symbol before the demodulated output signal. I have to.

[0005]

As described above, in order to QAM a digital signal for transmission, the input digital signal is subjected to differential logic processing and transmitted. Therefore, a complicated differential logic and a logic circuit for releasing the differential are required. When the differential logic is transmitted and transmitted, when releasing the differential logic, one of the transmitted signals is
Two bit errors occur, which worsens the bit error rate.

An object of the present invention is to provide a phase uncertainty removing device which makes the phase of a carrier wave added at the time of demodulation the same as the phase of a transmitted carrier wave.

[0007]

Means adopted by the present invention for solving the above problems will be described with reference to FIG. FIG. 1 shows the principle of the present invention. First, the principle will be described before explaining the means for solving the problems.

[0008] QAM signal S (t) is where _{S (t) = A I (} t) cos (w s t) + A Q (t) sin (w s t) ... (1), A I (t) and A _In the case of 16QAM, _Q (t) is represented by taking one of ± 1 and ± 3 corresponding to the input digital signal.

In the demodulator, the input signal S (t)
Carrier wave w of force signal S (t)_sClose to w _lOf carrier wave
Asynchronous detection. That is, cos (w in S (t)_lt) Yoo
And sin (w_lt) to pass the low pass filter,
Obtain the signals (t) and Q (t).

[0010] I (t) and Q (t) is, I (t) = S ( t) cos (w l t) = _{[A I (t) cos (θt} ) + A Q (t) sin (θt) ] / 2 ... (2) Q ( t) = S (t) sin (w l t) = _{[- A I (t) sin (} θt) + A Q (t) cos (θt) ] / 2 ... (3) where , Θ = w _s −w _l .

The target demodulated signals are A _I (t) and A _Q
(t) and I (t) and Q (t) shown in equations (2) and (3) include sin (θt) and cos (θt) that rotate at an angular velocity of θ, so phase rotation The circuit performs the following operations. I (t) cos (θt) + Q (t) sin (θt) = A _I (t) (4) −I (t) sin (θt) + Q (t) cos (θt) = A _Q (t) (5) By performing the operation on the left side of equation (4), A _I (t)
However, A _Q (t) can be obtained by performing the operation on the left side of the equation (5). Note that c in equations (4) and (5)
os (θt) and sin (θt) are added from the carrier wave generation circuit.

The carrier waves supplied from the carrier wave generating circuits shown in equations (4) and (5) are sin (θt) and cos (θt).
However, the carrier wave supplied from the carrier wave generation circuit is θt +
In addition to 0, θt + π / 2, θt + π and θt + 3π / 2
In some cases, it has either phase.

When a carrier wave other than θt + 0 is supplied to the phase rotation circuit, the calculation results of equations (4) and (5) do not become A _I (t) and A _Q (t), and the original signal Cannot be demodulated. Therefore, with the help of the frame pattern detection means. When transmitting a digital signal, a frame signal necessary for separating the unit of signal or data to be multiplexed on the receiving side is added. The frame signal is composed of the same pattern at predetermined fixed intervals.

Therefore, the carrier wave phase generated by the carrier wave generating circuit may be corrected so that the frame pattern detecting means receives the regular frame pattern. Next, the means will be described. QAM for correcting a phase shift based on the carrier frequency difference of a detected signal by adding a carrier frequency asynchronous with a carrier frequency of a received signal and demodulating two series of signals
A phase indeterminacy removing device for a demodulator, wherein a frame pattern detecting means 1 for detecting a frame pattern from the demodulated two series of signals and a normal frame pattern are detected by the frame pattern detecting means 1. A carrier wave phase correction means 2 for correcting the output carrier wave phase of the carrier wave generation circuit 4 added to the phase rotation circuit 3 for correcting the phase shift.

[0015]

The carrier phase correction means 2 corrects the phase of the carrier wave supplied from the carrier wave generation circuit 4 to the phase rotation circuit 3 so that the frame pattern detected by the frame pattern detection means 1 becomes a regular frame pattern.

That is, the phases of the carrier waves transmitted from the carrier wave generating circuit 4 are θt + π / 2, θt + π and θt +.
When it is 3π / 2, the phase is corrected to θt + 0. When a carrier wave having a phase of θt + 0 is input to the phase rotation circuit 3, a normal digital signal is reproduced and the frame pattern detecting means 1 detects a normal frame pattern, as shown in equations (4) and (5). .

As described above, the transmitted frame pattern is detected, and the phase of the carrier wave output from the carrier wave generation circuit is corrected so that the normal frame pattern is detected. Is simplified, and errors in the transmitted digital signal can be reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram of the present invention. In FIG. 2, 10
Is a frame pattern detection circuit for detecting a frame pattern, 20 is a carrier wave phase correction circuit for correcting the phase of the carrier wave sent from the carrier wave generation circuit 4, and 3 is a phase rotation circuit.

Signals I (t) and Q (t) shown in equations (2) and (3) are input to the input of the carrier generation circuit 4, and two orthogonal carrier waves supplied from the carrier generation circuit 4 are supplied. The calculation shown on the left side of the equations (4) and (5) is performed and output. A first specific example of the carrier wave generation circuit 4 and the carrier wave correction circuit 20 will be described with reference to FIG.

The carrier generation circuit 4 includes a memory 41 and an adder 4
2 and the phase error detector 43. The carrier phase correction circuit 20 includes a memory 21, a quaternary counter 22,
It is composed of an AND circuit 23 and an adder 24. First,
The carrier wave generation circuit 4 will be described.

The memory 41 stores the values of sin and cos in which the phase angle of the generated carrier wave is associated with the address and the associated address is the phase angle. That is, for example, when the address is changed from 0 to 359, the value of sin (x) and the value of cos (X) are stored in the address x.

The output from the phase rotation circuit 3, that is, the calculation results A _I (t) and A _Q (t) on the left side of the equations (4) and (5) are input to the phase error detector 43, and the following equation Then, the phase error output PD is output. PD = SGM {A _I (t)} ・ ER {A _Q (t)} + SGM {A _Q (t)} ・ ER {A _I (t)} (6) However, SGM {A (t)} is Polarity ER {A (t)} indicating positive or negative of A (t) indicates an error from the normal value of A (t).

The output value PD from the phase error detector 43 is input to the adder 42 and added to the value held by the adder 42. The adder 43 performs addition using the address value of the memory 41 as a modulus. That is, as described above, if the address of the memory 41 is 0 to 359, the adder 42 adds 0 to 360, and 361 to 1 to perform modulo 360 addition.

The added value of the adder 42 is input to the memory 41 as an address, and the sin and cos values corresponding to the address are read and output to the phase rotation circuit 3. The memory 21 of the carrier wave phase correction circuit 20 is composed of memories having four addresses. Address 0 is 0, and address 1 is an address value at which the angle of the memory 41 of the carrier wave generation circuit 4 is 90 degrees. 180 for 2 and 270 for address 3
Stores the address value in degrees.

The AND circuit 23 includes a signal which becomes "1" when the frame pattern detection circuit 10 does not detect a normal frame pattern and a low frequency signal which generates a pulse in a cycle longer than the cycle in which the frame pattern is transmitted. A clock pulse is input. The quaternary counter 22 adds the pulses from the AND circuit 23.

The memory 21 reads data by using the counter value of the quaternary counter 22 as an address, and the adder 24 adds the data to the data value output from the adder 42 to obtain the address of the memory 41. If the signal from the frame pulse detection circuit 10 input to the AND circuit 23 is "1", the low frequency clock pulse passes through the AND circuit 23 and increments the count value of the quaternary counter 22 by one.

When the count value of the quaternary counter 22 is incremented by 1, the data value read from the memory 21 becomes a data value that is 90 degrees larger than the previous data value.
The phase of the carrier wave read from 1 is added by 90 degrees. Even in this state, if the frame pattern detection circuit 10 does not detect a normal frame pattern, "1" is output to the AND circuit 23 and the count value of the quaternary counter 22 is increased by +.
Do 1

When the frame pattern detection circuit 10 detects a normal frame pattern, "0" is output to the AND circuit 23 to prevent passage of the low frequency clock pulse to the quaternary counter 22. Next, a second specific example will be described with reference to FIG. In FIG. 4, the carrier generation circuit 4 is similar to that of FIG.

The carrier wave phase correction circuit 20 is an AND circuit 2.
3, an adder 24 and a π / 2 address generator. The π / 2 address generator 24 generates an address value in which the phase of the carrier wave output from the memory 41 advances by 90 degrees. That is, the address of the memory 41 is 0 as in the above-mentioned example.
In the case of 359, 90 is generated.

As described in the first specific example, the frame pattern detection circuit 10 outputs "1" to the AND circuit 23, the low frequency clock pulse passes through and is input to the π / 2 address generation circuit 24. 90 is output and added by the adder 24 with the signal from the phase error detector 43.

The output from the π / 2 address generator 25 is
When the adder 24 performs addition with the output from the phase error detector 43, 0 is output thereafter. Therefore, every time a low frequency clock pulse is output from the AND circuit 23, the phase of the carrier wave read from the memory 41 jumps to a value different by 90 degrees from the normal case.

Next, a third specific example will be described with reference to FIG. In FIG. 5, the carrier generation circuit 4 is similar to that of FIG. The carrier wave phase correction circuit 20 includes a memory 21, an adder 24 and a four-value converter 26,
The memory 21 and the adder 24 are as described in FIG.

In the third specific example, first, the difference between the phase of the carrier wave expressed by the equations (2) and (3) input to the phase rotation circuit 3 and the phase of the carrier wave supplied from the carrier wave generation circuit 4 is detected. To do. The detection of this phase difference is performed as follows.

As described above, the frame pattern has one
The same pattern is transmitted at regular intervals. So putter
1 bit in the channel is normal (carrier phase difference is 0)
A, _I= 0, A_Q= 0, the carrier level
If the phases differ by 90 degrees, 180 degrees and 270 degrees
Is received as

Phase difference 0 degrees: A _I = 0, A _Q = 0 Phase difference 90 degrees: A _I = 0, A _Q = 1 Phase difference 180 degrees: A _I = 1 and A _Q = 1 Phase difference 270 degrees: a _I = 1, a _Q = 0 ... (7) however, a _I and a _Q is a code representing the positive and negative polarities of a _I and a _Q of formula (1), 0 negative, 1 is a positive Show.

As described above, the phase difference can be detected by using the bits of the frame pattern detected by the frame pattern detection circuit 10. The four-value converter 26 is 0 when the phase difference is 0 degrees, 1 when the phase difference is 90 degrees,
The conversion is performed so that 2 is output in the case of 180 degrees and 3 is output in the case of 270 degrees.

In the example shown in equation (7), the four-value converter 26
Is built saw A _I a 2 ^1, A _Q binary two binary ^0, the output value D ₁ and _{D 0 D 1 = A I D} 0 = A I ◎ A Q ... (8) However, ◎ may be converted to indicate exclusive OR. That is, when the phase difference is 180 degrees, the code is converted to a code when the phase difference is 270 degrees, 270 degrees, and 180 degrees.

The signal converted into four values as described above becomes the same as the output value of the quaternary counter 22 described in the first concrete example of FIG. 3, and the output from the carrier wave generating circuit 4 has the correct phase. Can be corrected. Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various modifications can be made according to the gist of the invention.

[0039]

As described above, according to the present invention, the following effects can be obtained. Since the phase of the carrier wave output from the carrier wave generation circuit is corrected so that a regular frame pattern is detected, the structure of the modulator / demodulator is simplified and errors in the transmitted digital signal can be reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a first specific example of a carrier wave generation circuit and a carrier wave phase correction circuit of the same embodiment.

FIG. 4 is a second specific example of the carrier wave generation circuit and the carrier wave phase correction circuit of the embodiment.

FIG. 5 is a third specific example of the carrier wave generation circuit and the carrier wave phase correction circuit of the same embodiment.

[Explanation of symbols]

 1 frame pattern detection means 2 carrier wave phase correction means 3 phase rotation circuit 4 carrier wave generation circuit 10 frame pattern detection circuit 20 carrier wave phase correction circuit 21, 41 memory 22 quaternary counter 23 AND circuit 24, 42 adder 25 π / 2 address generation Unit 26 4-value converter 43 Phase error detector

Claims (4)

[Claims] 1. A phase uncertain removal of a QAM demodulator that adds a carrier wave asynchronous with a carrier wave frequency of a received signal to correct a phase shift based on the carrier wave frequency difference of a detected signal and demodulates two series of signals. An apparatus, comprising: a frame pattern detecting means (1) for detecting a frame pattern from the demodulated two-sequence signals; and the phase so that a normal frame pattern is detected by the frame pattern detecting means (1). A carrier phase correcting means (2) for correcting an output carrier wave phase of a carrier wave generating circuit (4) added to a phase rotating circuit (3) for correcting a shift, and a phase uncertainty removing device characterized by the following: 2. The carrier wave generation so that an error signal based on a phase error from the phase rotation circuit (3) is accumulated as an address and a data value read from a memory is transmitted as an output carrier wave signal. A circuit (4) is configured to sequentially add an address value at which 0, output carrier wave phases π / 2, π and 3π / 2 are added to the accumulated address value, and the frame pattern detecting means (1) generates a normal address. 2. The phase uncertainty removing device according to claim 1, wherein the added address value in which the frame pattern is detected is fixed. 3. The carrier wave generation so that an error signal based on a phase error from the phase rotation circuit (3) is accumulated and used as an address, and a data value read from a memory is sent out as an output carrier wave signal. The circuit (4) is configured to continue adding the address value at which the output carrier wave phase is added by π / 2 to the error signal to be accumulated until the frame pattern detecting means (1) detects a normal frame pattern. The phase uncertainty removing device according to claim 1, wherein 4. The carrier wave generation so that an error signal based on a phase error from the phase rotation circuit (3) is accumulated and used as an address, and a data value read from a memory is sent out as an output carrier wave signal. A circuit (4) is configured to detect an uncertain phase difference from the frame pattern detected by the frame pattern detecting means (1) and add an address value corresponding to the detected phase difference to the accumulated address value. The phase uncertainty removing device according to claim 1, wherein