JPH06296011A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize logic function and storage function, by generating, on a conductor, a current in a pattern type depending on the coupling between conductor dots, when a specified voltage is applied to the conductor. CONSTITUTION:A semiconductor device has a plurality of semiconductor dots D arranged in a matrix. The dots D are connected with a plurality of conductors as conductive semiconductor channel T. When an input voltage is applied to the conductor T, a current is generated in a pattern type which corresponds with the coupling between the semiconductor dots. Thereby parallel data processing is enabled, and ultra high-speed operation can be realized. The logic function can be changed by changing the state of the semiconductor dots.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a logic function and / or a memory function.

[0002]

BACKGROUND OF THE INVENTION In conventional logic circuits, transistors or other logic gates integrated on a semiconductor chip (eg, CMOS device) logically combine multiple currents of multiple electron currents with each other. . In such a conventional method using current, there is a limit in the speed at which information propagates between adjacent gates, and there is a limit in the degree of integration that can be realized.

On the other hand, in recent years, a method for forming a finer semiconductor channel has been proposed. In this tiny semiconductor channel, electron propagation is wave-like and is characterized by the action of quantum mechanical waves. For details, see the American Physical Society Journal (Am Phys. Soc.), Physical Review Letters Vol. 60, No. 9
Published in BJvan
Wees) et al., “Quantized Conductance.
Of Point Contacts in a Two-dimensional Electron Gas (Quantized Conductance
of Point Contacts in a Two-Dimensional Electron G
as) ”on pages 848 to 850. Further, a method has also been proposed in which dots of a conductive semiconductor material having a sufficiently small diameter are formed on a semiconductor substrate, thereby forming a potential well that can contain a single electron. For more information on this, see Am Phys. So
c. , Physical Review Letters Vol. 62,
No. BJ van Wees et al., "Observation of Zero Dimensional States in a One Dimensional Electron Interferometer (Observation) of Zero-Dimensional States ina On
e Dimensional Electron Interferometer) "2523 to 2526. Normally, 10 semiconductor dots
It has a diameter of 0 nm or less. As a method of forming dots that confine such electrons, direct growth (direct gr
owth) or surface depletion, or by using an electrode that produces a field that confines one electron in the dot region.

[0004]

The present invention realizes a logical function and a memory function by using such semiconductor dots.

[0005]

According to the present invention, an array of a plurality of semiconductor dots for having a predetermined electrical coupling between them and a quantum mechanical electrical coupling with the plurality of dots are provided. A semiconductor device comprising a plurality of formed conductors, wherein when a predetermined voltage is applied to the conductors, a current is generated on the conductors in a pattern depending on the coupling between the dots. Provided.

The preset electrical coupling between the dots can be created in a variety of different ways. For example, in the static method, dots are arranged in a matrix,
A plurality of dots at a specific position in it are deleted.

In the dynamic method, the quantum mechanical state of a plurality of dots is selectively controlled to affect the electron occupancy of the dots, thereby establishing a predetermined electrical coupling between the dots. To generate. The quantum mechanical state of the dot can be controlled by applying an electrical bias potential or by photon injection.

[0008]

The semiconductor device according to the present invention has various effects. That is, parallel data processing becomes possible, and thus ultra-high speed operation is realized. Moreover, it becomes possible to change the logical function by changing the state of the dots.
Furthermore, by arranging the dots in groups to provide redundancy, it is possible to improve the reliability of the device and to facilitate manufacturing and improve the yield.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, referring to FIG.
This will be described with reference to FIG. As shown in FIG. 1, this semiconductor device has a plurality of semiconductor dots D arranged in a matrix, and these dots D are connected to a plurality of conductors as a conductive semiconductor channel T. The dot D and the channel T are defined by appropriately constraining the two-dimensional electron gas generated in the semiconductor heterojunction. Here, a specific example will be described with respect to gallium arsenide (GaAs), but it is also possible to manufacture using a heterolayer junction such as InP or another III-VI group or VI-VI group junction. is there. Well, Ga
Considering the example of the As device in more detail, the method of defining the dot D and the channel T can be understood from the cross-sectional views shown in FIGS. This semiconductor device comprises a GaAs substrate 1 on which a GaAs heterostructure is formed. This heterostructure consists of an undoped (doped) GaAs layer 2, an undoped AlGaAs layer 3 and a doped AlGaAs layer 4, and on top of this undoped AlGaAs layer 5 and doping. The two passivation layers of GaAs layer 6 which are not covered are covered. Hereinafter, the doped layer will be referred to as a doped layer, and the undoped layer will be referred to as an undoped layer.

The layers 2, 3, 4 are composed of undoped GaAs.
A two-dimensional electron gas 7 is generated at the interface between the layer 2 and the undoped AlGaAs layer 3, and the degree of freedom of its conduction is AlGaA.
It is well known that the s-layer 4 is partially controlled by the dopant. In this semiconductor device, the pattern of dopants introduced into layer 4 is chosen so that the electron gas is bound to define the conductive channel T and dot configuration D shown in FIG. This can be accomplished by combining masking and / or focused ion beam (FIB) techniques in a manner recognized by those skilled in the art. For example, Journal of the Vacuum Society of Japan (J. Vac. Sci. T.
echnol) B 6 (3) May 1988, June / J.Y. See Hirayama et al., "GaAs / AlGaAs Material Modifications Induced By Focused Ga Ion Beam Implantation", pages 1018 to 1021. In this way, by partially collapsing the crystal lattice structure using the focused ion beam, desired conductive dots and channel structures D and T can be formed in the conductive region 7.

As will be described in detail later, each dot D constitutes an ultrafine conductive region which functions as a potential well capable of holding an individual electron.

FIG. 4 shows individual dots D and channels T.
Is assigned an appropriate code. The current flowing in the channel Tj is given by the following equation.

I _Tj = f _j (D ₁ , D ₂ , ..., D ₂₅ ; V _T1 , V _T2 , ... V _T20 ) (1) where D _i is the i-th dot and V _Ti is the channel Bias voltage to T _i is shown.

It will be appreciated that changing the state of dot D _i will change the current at terminal T _j . This current change can be detected by a peripheral circuit (not shown). In this way, the dot state configuration can be utilized to define logical and / or memory functions.

The movement of electrons in the semiconductor device will be described in more detail. Now, in FIGS. 5 and 6, it is assumed that the width of the channel T is narrow, for example, 100 nm, and the movement of electrons along the channel is considered to be the behavior of quantum mechanical waves. As shown in FIG. 5, electrons are quantized as standing waves in the width direction of the channel. On the other hand, electrons can propagate in the longitudinal direction of the channel. Electron energy E and longitudinal wavenumber (lo
The relationship with ngitudinal wave number) k is shown in the graph of FIG. When the energy E is less than E _i , the electrons in mode = i decay exponentially and cannot propagate in the channel. E _i is given by the following equation.

E _i = A (i / W) ² (2) where A is a constant determined by the material and W is the width of the channel.

In the case of the GaAs / AlGaAs heterostructure, A = 5600 (meV / nm ² ), and the typical electron energy is 10 meV. Therefore, mode = 1, 2,
The 3 and 4 electrons can propagate in a 100 nm wide channel. However, these electrons cannot propagate in a 10 nm wide channel.

Next, considering the electronic dot D,
The electrons in the dots are fully quantized as standing waves, as shown schematically in FIG.

FIG. 8 shows the interconnection relationship between channels and dots. When the channel T is connected to the dot D as in FIG. 8, the propagation of electrons along the channel is affected by whether or not there are electrons in the dot. The width W _{W of the} channel and the width W _n of the relatively narrow interconnection region are chosen such that W _W > E ₁ > W _n . For example, for a GaAs heterostructure, W _W = 100 nm and W _n = 10 nm. The channels and dots are placed close enough to each other that the electron waves overlap both the channels and the dots, resulting in tunneling of this narrow channel region n.

Therefore, by applying an input voltage to the channel (FIG. 4), a current is generated in the channel. The pattern of this current depends on the configuration and state of the matrix of dots.

As can be seen from FIG. 9, the omission of certain dots from the matrix will show that this is a static way to change the pattern of output current on the channel in response to the input voltage.

On the other hand, the dynamic method is a method of changing the quantum mechanical state of each dot so that each dot is occupied by electrons or not occupied by electrons. Figure 10
(A) is a schematic representation of a 1-dot quantum mechanical potential well. If there are no electrons in the well, the well has a chemical potential energy (energy required to add one electron into the well) E _0.
It is in. If there are electrons in the well, the chemical potential energy rises to E ₁ . FIG. 10B shows how the chemical potential energy changes depending on the spin state of the electron due to Pauli exclusion rule in quantum mechanics. The presence of electrons in the well inhibits channel-to-dot propagation and increases the impedance to current flow. But if there are no electrons in the dot,
The electrons in the channel pass through the area of the dot with a small amount of energy.

The chemical potential energy associated with each dot can also be controlled by other methods. FIG. 11 shows a dynamic method of emitting photons P onto individual dots to excite their electronic states.

As shown in FIG. 12, injection of photons can be performed by projecting a predetermined pattern on a matrix of dots D using a mask M and a reduction lens L. Alternatively, a shutter mechanism or other active optical matrix element can be used to control the injection of photons P into individual dots D, as shown in FIG.

Further, the chemical potential energy of the dots can be electrically and dynamically controlled by applying an electric field to each dot. 14 and 1
As shown in FIG. 5, this semiconductor device has an orthogonal matrix of control electrodes that receive a control potential for biasing individual dots D. The configuration of FIG. 15 is similar to that shown in FIG. 2, and the same reference numerals are used. The configuration of FIG. 15 has a set of parallel-doped conductive channels 8 formed in the undoped region 2 and a set of parallel conductor strips 9 orthogonal thereto. The conductor strip 9 is formed of a metal that covers the passivation layers 5 and 6. In this configuration, by applying an appropriate bias potential to the pair of conductors 8 and 9 and applying an electric field to the specific dot D, its electronic state can be changed. However, the configuration of FIG. 15 may be difficult to realize. The reason is that the spacing between the conductors 8 and 9 changes the electronic state of two or more dots, making it difficult to specify individual dots.

The configurations of FIGS. 16 and 17 can solve this problem. In this structure, two sets of orthogonally arranged metallic address electrodes 10 and 11 are formed on the passivation layers 5 and 6 by coating. This electrode 10
And 11 cooperate with a conductive layer 12 which is grounded. The electrodes 10 and 11 are separated by an insulating thin film (not shown). In use, the designation (addressing) of individual dots D is performed as follows. First, a bias voltage lower than a desired bias voltage is applied to one of the specific address conductors 10. Next, a bias voltage is applied to a specific plurality of address conductors 11. This bias voltage changes the electronic state of the dots located at the intersections of the excited electrodes 10 and 11.

FIGS. 18, 19 and 20 show examples of dot / channel configurations that can be used in the present invention. These use a static method for controlling the transfer function of a semiconductor device. FIG. 18 shows that the channels T do not have to be connected to all the side edges of the dot matrix. FIG. 19 shows that a major part of the dot matrix may be omitted to achieve a particular transfer function.

FIG. 20 shows that the dot configuration D, which was a substantially rectangular array in the above example, may be arranged in a substantially triangular array.

It is also possible to use a combination of a static method and a dynamic method for determining the dot state. That is, in a matrix in which dots are missing at specific matrix positions, a bias potential can be applied to the remaining dots in order to selectively change the electronic state of the specific dots in the dot matrix.

Further, as shown schematically in FIG.
It is also possible to fabricate a three-dimensional array of dots and corresponding channels. To that end, the layers 2, 3 (FIG. 2) are repeated on the substrate 1 to form a repeating dot matrix / channel layer.

Although the present invention has been described above with reference to the GaAs technique, dot formation may be accomplished using other fabrication techniques, such as S.
Other materials such as i or SiGe techniques are also possible. It is also possible to make dots as semiconductor dots in glass.

With reference to FIG. 22, it is not necessary to determine one unit of information for each dot, and one unit of information can be determined for each plurality of dots. As shown in the figure, each channel T is wider than the channel shown in FIG. 1 and spans three dots. That is, the dots D are arranged in 3 × 3 dot subset units, and each subset defines one unit of information. Such redundancy improves semiconductor device function reliability and manufacturing yield.

Next, with reference to FIG. 23, an example of manufacturing the semiconductor device of this embodiment will be described. Using the epitaxial growth technique, layers 2, 3, are sequentially formed on the undoped substrate 1.
Grow 4, 5 and 6. The thickness and composition of each layer are as shown in FIG. The structure thus produced produces a two-dimensional electron gas 7 at the heterojunction between layers 2 and 3. Each layer can be grown by methods well known in the art using molecular beam epitaxy (MBE) or MOCVD.

Following this, the focused ion beam (FIB) method is used to implant Ga + ions into the doped layer 4 in accordance with an appropriate spatial pattern and change the spatial lattice pattern. As a result, the electron gas 7 is bound, which defines the required dot D and channel T. FIB implantation is usually 30-40
Run with KeV until a concentration of 10 ¹² -10 ¹³ cm ² is reached.

Further, the substrate may be pre-patterned to define the dots and channels.

The semiconductor device according to the present invention is particularly suitable for logic /
It has applications as a memory device, but is also useful for applications such as pattern recognition. For pattern recognition, a set of control potentials representing a specific pattern is applied to the first set of channels T in the learning mode. In response to this, the electronic state of the particular dot group changes, resulting in a particular output signal group in the second set of channels T. The device can then be used to recognize the pattern. That is, when the group of input potentials applied to the first set of channels causes the particular set of output signals to be generated in the second set of channels, this means that the pattern has been recognized.

Further, since the dots are arranged very close to each other and function by the interaction between the electrons instead of by the current as in the conventional case, the operation speed of the semiconductor device is improved and the component element of the semiconductor device is improved. The degree of integration is improved. Moreover, since interconnection between devices can be performed by using a conductive path of a semiconductor instead of the conventional method of using a metal layer, it is possible to include a large number of devices in a single chip. Become.

[0038]

According to the present invention, it is possible to perform parallel data processing, thereby realizing ultrahigh speed operation. Moreover, it becomes possible to change the logical function by changing the state of the dots. Furthermore, by arranging the dots in groups to provide redundancy, it is possible to improve the reliability of the device and to facilitate manufacturing and improve the yield.

[Brief description of drawings]

1 is a schematic cross-sectional view of the semiconductor device according to the present invention, taken along the plane III of FIG.

2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the line II '.

FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line II-II ′.

FIG. 4 is a schematic diagram of the channels and dots shown in FIG. 1, with appropriate reference numerals.

FIG. 5 is an illustration of different modes for quantum mechanical wave operation for electron propagation in the channel.

FIG. 6 is a schematic graph showing the relationship between electron energy and mode wave number.

FIG. 7 is an explanatory diagram of an electronic standing wave for one dot.

8 is an explanatory diagram showing an interconnection relationship between a channel T and a dot D. FIG.

FIG. 9 is an explanatory diagram of a dot matrix in which a plurality of dots are missing at a specific position.

FIG. 10 is an explanatory diagram of various electron energies regarding one dot.

FIG. 11 is an explanatory diagram of photon injection into dots.

FIG. 12 is an explanatory diagram of photon injection through a mask pattern.

FIG. 13 is an explanatory diagram of photon injection using a shutter.

FIG. 14 is a schematic configuration diagram of an electrode for applying a bias potential to each dot.

15 is a cross-sectional view taken along the line IV-IV ′ of FIG.

FIG. 16 is a schematic configuration diagram of another electrode for biasing individual dots.

17 is a cross-sectional view taken along the line VV ′ of FIG.

FIG. 18 is an explanatory diagram of another channel configuration.

FIG. 19 is an explanatory diagram of another dot configuration.

FIG. 20 is an explanatory diagram of substantially triangular dots.

FIG. 21 is an explanatory diagram of a three-dimensional array of dots.

FIG. 22 is an explanatory diagram of dots grouped for redundancy.

FIG. 23 is a more detailed explanatory diagram relating to the manufacture of the semiconductor device of the present invention.

[Explanation of symbols]

1 ... GaAs substrate, 2 ... undoped GaAs layer, 3 ... undoped AlGaAs layer, 4 ... doped AlGaAs layer, 5 ...
Undoped AlGaAs layer, 6 ... Undoped GaAs layer, T
... channel, D ... dot.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 20, 1993

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 14

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be amended] Detailed explanation of the invention

[Correction method] Change

[Correction content]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a logic function and / or a memory function.

[0002]

BACKGROUND OF THE INVENTION In conventional logic circuits, transistors or other logic gates integrated on a semiconductor chip (eg, CMOS device) logically combine multiple currents of multiple electron currents with each other. . In such a conventional method using current, there is a limit in the speed at which information propagates between adjacent gates, and there is a limit in the degree of integration that can be realized.

On the other hand, in recent years, a method for forming a finer semiconductor channel has been proposed. In this tiny semiconductor channel, electron propagation is wave-like and is characterized by the action of quantum mechanical waves. For details, see the American Physical Society Journal (Am Phys. Soc.), Physical Review Letters Vol. 60, No. 9
Published in BJvan
Wees) et al., “Quantized Conductance.
Of Point Contacts in a Two-dimensional Electron Gas (Quantized Conductance
of Point Contacts in a Two-Dimensional Electron G
as) ”on pages 848 to 850. Further, a method has also been proposed in which dots of a conductive semiconductor material having a sufficiently small diameter are formed on a semiconductor substrate, thereby forming a potential well that can contain a single electron. For more information on this, see Am Phys. So
c. , Physical Review Letters Vol. 62,
No. BJ van Wees et al., "Observation of Zero Dimensional States in a One Dimensional Electron Interferometer (Observation) of Zero-Dimensional States ina On
e Dimensional Electron Interferometer) "2523 to 2526. Normally, 10 semiconductor dots
It has a diameter of 0 nm or less. As a method of forming dots that confine such electrons, direct growth (direct gr
owth) or surface depletion, or by using an electrode that produces a field that confines one electron in the dot region.

[0004]

The present invention realizes a logical function and a memory function by using such semiconductor dots.

[0005]

According to the present invention, an array of a plurality of semiconductor dots for having a predetermined electrical coupling between them and a quantum mechanical electrical coupling with the plurality of dots are provided. A semiconductor device comprising a plurality of formed conductors, wherein when a predetermined voltage is applied to the conductors, a current is generated on the conductors in a pattern depending on the coupling between the dots. Provided.

The preset electrical coupling between the dots can be created in a variety of different ways. For example, in the static method, dots are arranged in a matrix,
A plurality of dots at a specific position in it are deleted.

In the dynamic method, the quantum mechanical state of a plurality of dots is selectively controlled to affect the electron occupancy of the dots, thereby establishing a predetermined electrical coupling between the dots. To generate. The quantum mechanical state of the dot can be controlled by applying an electrical bias potential or by photon injection.

[0008]

The semiconductor device according to the present invention has various effects. That is, parallel data processing becomes possible, and thus ultra-high speed operation is realized. Moreover, it becomes possible to change the logical function by changing the state of the dots.
Furthermore, by arranging the dots in groups to provide redundancy, it is possible to improve the reliability of the device and to facilitate manufacturing and improve the yield.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, referring to FIG.
This will be described with reference to FIG. As shown in FIG. 1, this semiconductor device has a plurality of semiconductor dots D arranged in a matrix, and these dots D are connected to a plurality of conductors as a conductive semiconductor channel T. The dot D and the channel T are defined by appropriately constraining the two-dimensional electron gas generated in the semiconductor heterojunction. Here, a specific example will be described with respect to gallium arsenide (GaAs), but it is also possible to manufacture using a heterolayer junction such as InP or another III-VI group or VI-VI group junction. is there. Well, Ga
Considering the example of the As device in more detail, the method of defining the dot D and the channel T can be understood from the cross-sectional views shown in FIGS. This semiconductor device comprises a GaAs substrate 1 on which a GaAs heterostructure is formed. This heterostructure consists of an undoped (doped) GaAs layer 2, an undoped AlGaAs layer 3 and a doped AlGaAs layer 4, and on top of this undoped AlGaAs layer 5 and doping. The two passivation layers of GaAs layer 6 which are not covered are covered. Hereinafter, the doped layer will be referred to as a doped layer, and the undoped layer will be referred to as an undoped layer.

The layers 2, 3, 4 are composed of undoped GaAs.
A two-dimensional electron gas 7 is generated at the interface between the layer 2 and the undoped AlGaAs layer 3, and the degree of freedom of conduction is AlGaA
It is well known that the s-layer 4 is partially controlled by the dopant. In this semiconductor device, the pattern of dopants introduced into layer 4 is chosen so that the electron gas is bound to define the conductive channel T and dot configuration D shown in FIG. This can be accomplished by combining masking and / or focused ion beam (FIB) techniques in a manner recognized by those skilled in the art. For example, Journal of the Vacuum Society of Japan (J. Vac. Sci. T.
echnol) B 6 (3) May 1988, June / J.Y. See Hirayama et al., "GaAs / AlGaAs Material Modifications Induced By Focused Ga Ion Beam Implantation", pages 1018 to 1021. In this way, by partially collapsing the crystal lattice structure using the focused ion beam, desired conductive dots and channel structures D and T can be formed in the conductive region 7.

As will be described in detail later, each dot D constitutes an ultrafine conductive region which functions as a potential well capable of holding an individual electron.

FIG. 4 shows individual dots D and channels T.
Is assigned an appropriate code. The current flowing in the channel Tj is given by the following equation.

I _Tj = f _j (D ₁ , D ₂ , ..., D ₂₅ ; V _T1 , V _T2 , ... V _T20 ) (1) where D _i is the i-th dot and V _Ti is the channel Bias voltage to T _i is shown.

It will be appreciated that changing the state of dot D _i will change the current at terminal T _j . This current change can be detected by a peripheral circuit (not shown). In this way, the dot state configuration can be utilized to define logical and / or memory functions.

The movement of electrons in the semiconductor device will be described in more detail. Now, in FIGS. 5 and 6, it is assumed that the width of the channel T is narrow, for example, 100 nm, and the movement of electrons along the channel is considered to be the behavior of quantum mechanical waves. As shown in FIG. 5, electrons are quantized as standing waves in the width direction of the channel. On the other hand, electrons can propagate in the longitudinal direction of the channel. Electron energy E and longitudinal wavenumber (lo
The relationship with ngitudinal wave number) k is shown in the graph of FIG. When the energy E is less than E _i , the electrons in mode = i decay exponentially and cannot propagate in the channel. E _i is given by the following equation.

E _i = A (i / W) ² (2) where A is a constant determined by the material and W is the width of the channel.

In the case of the GaAs / AlGaAs heterostructure, A = 5600 (meV / nm ² ), and the typical electron energy is 10 meV. Therefore, mode = 1, 2,
The 3 and 4 electrons can propagate in a 100 nm wide channel. However, these electrons cannot propagate in a 10 nm wide channel.

Next, considering the electronic dot D,
The electrons in the dots are fully quantized as standing waves, as shown schematically in FIG.

FIG. 8 shows the interconnection relationship between channels and dots. When the channel T is connected to the dot D as in FIG. 8, the propagation of electrons along the channel is affected by whether or not there are electrons in the dot. The width W _{W of the} channel and the width W _n of the relatively narrow interconnection region are chosen such that W _W > E ₁ > W _n . For example, for a GaAs heterostructure, W _W = 100 nm and W _n = 10 nm. The channels and dots are placed close enough to each other that the electron waves overlap both the channels and the dots, resulting in tunneling of this narrow channel region n.

Therefore, by applying an input voltage to the channel (FIG. 4), a current is generated in the channel. The pattern of this current depends on the configuration and state of the matrix of dots.

As can be seen from FIG. 9, the omission of certain dots from the matrix will show that this is a static way to change the pattern of output current on the channel in response to the input voltage.

On the other hand, the dynamic method is a method of changing the quantum mechanical state of each dot so that each dot is occupied by electrons or not occupied by electrons. Figure 10
(A) is a schematic representation of a 1-dot quantum mechanical potential well. If there are no electrons in the well, the well has a chemical potential energy (energy required to add one electron into the well) E _0.
It is in. If there are electrons in the well, the chemical potential energy rises to E ₁ . FIG. 10B shows how the chemical potential energy changes depending on the spin state of the electron due to Pauli exclusion rule in quantum mechanics. The presence of electrons in the well inhibits channel-to-dot propagation and increases the impedance to current flow. But if there are no electrons in the dot,
The electrons in the channel pass through the area of the dot with a small amount of energy.

The chemical potential energy associated with each dot can also be controlled by other methods. FIG. 11 shows a dynamic method of emitting photons P onto individual dots to excite their electronic states.

As shown in FIG. 12, injection of photons can be performed by projecting a predetermined pattern on a matrix of dots D using a mask M and a reduction lens L. Alternatively, a shutter mechanism or other active optical matrix element can be used to control the injection of photons P into individual dots D, as shown in FIG.

Further, the chemical potential energy of the dots can be electrically and dynamically controlled by applying an electric field to each dot. 14 and 1
As shown in FIG. 5, this semiconductor device has an orthogonal matrix of control electrodes that receive a control potential for biasing individual dots D. The configuration of FIG. 15 is similar to that shown in FIG. 2, and the same reference numerals are used. The configuration of FIG. 15 has a set of parallel-doped conductive channels 8 formed in the undoped region 2 and a set of parallel conductor strips 9 orthogonal thereto. The conductor strip 9 is formed of a metal that covers the passivation layers 5 and 6. In this configuration, by applying an appropriate bias potential to the pair of conductors 8 and 9 and applying an electric field to the specific dot D, its electronic state can be changed. However, the configuration of FIG. 15 may be difficult to realize. The reason is that the spacing between the conductors 8 and 9 changes the electronic state of two or more dots, making it difficult to specify individual dots.

The configurations of FIGS. 16 and 17 can solve this problem. In this structure, two sets of orthogonally arranged metallic address electrodes 10 and 11 are formed on the passivation layers 5 and 6 by coating. This electrode 10
And 11 cooperate with a conductive layer 12 which is grounded. The electrodes 10 and 11 are separated by an insulating thin film (not shown). In use, the designation (addressing) of individual dots D is performed as follows. First, a bias voltage lower than a desired bias voltage is applied to one of the specific address conductors 10. Next, a bias voltage is applied to a specific plurality of address conductors 11. This bias voltage changes the electronic state of the dots located at the intersections of the excited electrodes 10 and 11.

FIGS. 18, 19 and 20 show examples of dot / channel configurations that can be used in the present invention. These use a static method for controlling the transfer function of a semiconductor device. FIG. 18 shows that the channels T do not have to be connected to all the side edges of the dot matrix. FIG. 19 shows that a major part of the dot matrix may be omitted to achieve a particular transfer function.

FIG. 20 shows that the dot configuration D, which was a substantially rectangular array in the above example, may be arranged in a substantially triangular array.

It is also possible to use a combination of a static method and a dynamic method for determining the dot state. That is, in a matrix in which dots are missing at specific matrix positions, a bias potential can be applied to the remaining dots in order to selectively change the electronic state of the specific dots in the dot matrix.

Further, as shown schematically in FIG.
It is also possible to fabricate a three-dimensional array of dots and corresponding channels. To that end, the layers 2, 3 (FIG. 2) are repeated on the substrate 1 to form a repeating dot matrix / channel layer.

Although the present invention has been described above with reference to the GaAs technique, dot formation may be accomplished using other fabrication techniques, such as S.
Other materials such as i or SiGe techniques are also possible. It is also possible to make dots as semiconductor dots in glass.

With reference to FIG. 22, it is not necessary to determine one unit of information for each dot, and one unit of information can be determined for each plurality of dots. As shown in the figure, each channel T is wider than the channel shown in FIG. 1 and spans three dots. That is, the dots D are arranged in 3 × 3 dot subset units, and each subset defines one unit of information. Such redundancy improves semiconductor device function reliability and manufacturing yield.

Next, with reference to FIG. 23, an example of manufacturing the semiconductor device of this embodiment will be described. Using the epitaxial growth technique, layers 2, 3, are sequentially formed on the undoped substrate 1.
Grow 4, 5 and 6. The thickness and composition of each layer are as shown in FIG. The structure thus produced produces a two-dimensional electron gas 7 at the heterojunction between layers 2 and 3. Each layer can be grown by methods well known in the art using molecular beam epitaxy (MBE) or MOCVD.

Following this, the focused ion beam (FIB) method is used to implant Ga + ions into the doped layer 4 in accordance with an appropriate spatial pattern and change the spatial lattice pattern. As a result, the electron gas 7 is bound, which defines the required dot D and channel T. FIB implantation is usually 30-40
Run with KeV until a concentration of 10 ¹² -10 ¹³ cm ² is reached.

Further, the substrate may be pre-patterned to define the dots and channels.

The semiconductor device according to the present invention is particularly suitable for logic /
It has applications as a memory device, but is also useful for applications such as pattern recognition. For pattern recognition, a set of control potentials representing a specific pattern is applied to the first set of channels T in the learning mode. In response to this, the electronic state of the particular dot group changes, resulting in a particular output signal group in the second set of channels T. The device can then be used to recognize the pattern. That is, when the group of input potentials applied to the first set of channels causes the particular set of output signals to the second set of channels, this means that the pattern has been recognized.

Further, since the dots are arranged very close to each other and function by the interaction between the electrons instead of by the current as in the conventional case, the operation speed of the semiconductor device is improved and the component element of the semiconductor device is improved. The degree of integration is improved. Moreover, since interconnection between devices can be performed by using a conductive path of a semiconductor instead of the conventional method of using a metal layer, it is possible to include a large number of devices in a single chip. Become.

[0038]

According to the present invention, it is possible to perform parallel data processing, thereby realizing ultrahigh speed operation. Moreover, it becomes possible to change the logical function by changing the state of the dots. Furthermore, by arranging the dots in groups to provide redundancy, it is possible to improve the reliability of the device and to facilitate manufacturing and improve the yield.

 ─────────────────────────────────────────────────── ───Continued from the front page (72) Inventor Gerhard Fasol UK, CB30 H.E., Cambridge, Madingley Road (no address), Hitachi Europe Limited Camping Bench Laboratories, Hitachi Cambridge Laboratories R & D Center (72) Inventor Halone Ahmed UK CB 30 H, Cambridge, Madingley Road (no street number), University of Cambridge Cavendish Laboratory

Claims (14)

[Claims] 1. An array of a plurality of semiconductor dots for having a predetermined electrical coupling between them, and a plurality of conductors forming quantum mechanical electrical coupling with the plurality of dots, the conductor comprising: A semiconductor device, wherein when an input voltage is applied to the conductor, a current is generated in the conductor in a pattern corresponding to the coupling between the dots. 2. The dots are arranged in a matrix, and the dots are missing at a specific position of the matrix, whereby a predetermined electrical connection between the dots is formed. The semiconductor device according to claim 1. 3. A control means for selectively controlling the quantum mechanical state of the dots, thereby affecting the electron occupancy of the dots to form a predetermined electrical connection between the dots. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 4. The semiconductor device according to claim 3, wherein the control means has means for selectively injecting photons into the dot, thereby changing the electronic state of the dot. 5. The semiconductor device according to claim 3, further comprising an electrode means for applying an addressing bias potential to the dot, thereby changing the electronic state of the dot. 6. The semiconductor device according to claim 1, wherein the dots are arranged in a three-dimensional array. 7. The semiconductor device according to claim 1, wherein the dots are grouped so as to provide redundancy. 8. A heterojunction layer having a substrate and a heterojunction layer formed on the substrate, wherein the heterojunction layer is formed so that the dots and channels are formed as conductive regions adjacent to the heterojunction. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 9. The semiconductor device of claim 8, wherein the substrate is GaAs and the heterojunction layer comprises an undoped GaAs layer and heterolayer means on the undoped GaAs layer. 10. The semiconductor device of claim 8, wherein the substrate is a Group IV semiconductor material. 11. The semiconductor device according to claim 8, wherein the substrate is made of an InP material. 12. The heterolayer means is the undoped Ga.
10. The semiconductor device according to claim 9, comprising an undoped AlGaAs layer covering the As layer and a doped AlGaAs layer covering the undoped AlGaAs layer. 13. The method according to claim 9, further comprising a passivation layer means covering the hetero layer means.
2. The semiconductor device according to 2. 14. The semiconductor device according to claim 8, wherein the substrate is pre-patterned to define the dots and channels.