JPH0629570A - Light-emitting element structure - Google Patents

Light-emitting element structure

Info

Publication number
JPH0629570A
JPH0629570A JP18011892A JP18011892A JPH0629570A JP H0629570 A JPH0629570 A JP H0629570A JP 18011892 A JP18011892 A JP 18011892A JP 18011892 A JP18011892 A JP 18011892A JP H0629570 A JPH0629570 A JP H0629570A
Authority
JP
Japan
Prior art keywords
layer
upper electrode
type
light emitting
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18011892A
Other languages
Japanese (ja)
Inventor
Shinichi Watabe
信一 渡部
Kazuyuki Tadatomo
一行 只友
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Priority to JP18011892A priority Critical patent/JPH0629570A/en
Publication of JPH0629570A publication Critical patent/JPH0629570A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide the structure of a light-emitting element such as LED, in which light emitted from a p-n junction can be efficiently taken out to the outside and the generation of light of high luminance is made possible. CONSTITUTION:In a light-emitting element structure in which a p-type/n-type semiconductor layer and n-type/p-type semiconductor layer are p-n joined and upper electrode and lower electrode are formed on a light take-out face and opposite-side rear face respectively, a current block layer 2 is formed between a p-n junction 1 directly below the upper electrode 7 and upper electrode, the current block layer 2 is desirably n-type or p-type semiconductor layer or electrically insulating layer, and the current block layer 2 is more desirably formed into the same shape as or a shape similar to that of the upper electrode and has the cross-sectional area of at least 1/2 of that of the upper electrode and 0.05-10.0mum thickness.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高輝度が得られる発光
ダイオード(LED)等の発光素子構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device structure such as a light emitting diode (LED) capable of obtaining high brightness.

【0002】[0002]

【従来の技術】LED等の発光素子は、計器等の数値表
示や各種表示板に多用されている。一般的に使用される
発光素子構造は、例えば図5で示すように、n型/p型
半導体基板6上に積層したn型/p型半導体層5とp型
/n型半導体層4とを接合させてpn接合部1を形成
し、上記p型/n型半導体層4あるいは必要に応じてさ
らに電流拡散層3を積層して、この表面(以下、光取り
出し面という)上にドット状の電極(以下、上部電極と
いう)7を設け、上記基板6の表面(以下、裏面とい
う)上に平板状の電極(以下、下部電極という)8を形
成している。
2. Description of the Related Art Light emitting elements such as LEDs are widely used for numerical value display of measuring instruments and various display boards. A commonly used light emitting device structure includes, for example, as shown in FIG. 5, an n-type / p-type semiconductor layer 5 and a p-type / n-type semiconductor layer 4 stacked on an n-type / p-type semiconductor substrate 6. The pn junction 1 is formed by bonding, and the p-type / n-type semiconductor layer 4 or the current diffusion layer 3 is further laminated if necessary, and a dot shape is formed on this surface (hereinafter referred to as a light extraction surface). An electrode (hereinafter referred to as an upper electrode) 7 is provided, and a flat plate-shaped electrode (hereinafter referred to as a lower electrode) 8 is formed on the front surface (hereinafter referred to as a back surface) of the substrate 6.

【0003】[0003]

【発明が解決しようとする課題】上記の発光素子構造に
よれば、上部電極7の直下方向のpn接合部が、最も電
流が注入される領域となるので、発光素子はこの部分で
発光量が最も多くなり強発光となる。ところが、この強
発光は、光取り出し面に向かって発せられるが、その直
上部にある上部電極によって吸収され、素子外部に効率
的に取り出すことができず、発光素子の輝度が低下す
る。このように、従来の発光素子構造では輝度が低く、
市場ではさらに高輝度の発光素子の開発が強く望まれて
いる。これに応じて様々な改良が提案されているが、上
記要望を十分満足させる発光素子は未だ開発されていな
いのが現状である。
According to the above light emitting device structure, since the pn junction immediately below the upper electrode 7 is the region into which the most current is injected, the light emitting device emits light at this portion. It becomes the most and becomes a strong light emission. However, although this strong light emission is emitted toward the light extraction surface, it is absorbed by the upper electrode immediately above the light extraction surface and cannot be efficiently extracted to the outside of the element, and the brightness of the light emitting element decreases. In this way, the conventional light emitting device structure has low brightness,
In the market, there is a strong demand for the development of light emitting devices with higher brightness. In response to this, various improvements have been proposed, but in the present circumstances, a light emitting element that sufficiently satisfies the above demand has not yet been developed.

【0004】本発明の目的は、上記の課題を解消し、p
n接合部から放出される光を効率よく外部に取り出すこ
とができ、高輝度の発光が可能なLED等の発光素子構
造を提供することにある。
The object of the present invention is to solve the above problems and
It is an object of the present invention to provide a light emitting element structure such as an LED capable of efficiently extracting the light emitted from the n-junction portion to the outside and capable of emitting light with high brightness.

【0005】[0005]

【課題を解決するための手段】本発明者等は、前記問題
を解消するため種々検討した結果、上部電極直下方向の
pn接合部に電流が集中して注入されない構造とするこ
とで、上記目的が達成できることを見出し本発明を完成
した。即ち、本発明の発光素子構造は、n型半導体層と
p型半導体層とをpn接合し、光取り出し面上に上部電
極を、反対側裏面上に下部電極を形成する発光素子構造
であって、該上部電極直下方向のpn接合部と上部電極
間に電流ブロック層を形成してなり、望ましくは該電流
ブロック層が、n型またはp型半導体層あるいは電気絶
縁性層であって、さらに望ましくは該電流ブロック層
が、上部電極と同一または相似形に形成されてなり、そ
の面積が上部電極の少なくとも1/2を有し、かつ、そ
の厚さが0.05〜10.0μmに形成されるものであ
る。
As a result of various studies to solve the above problems, the inventors of the present invention have made a structure in which current is not concentrated and injected into a pn junction immediately below the upper electrode. The present invention has been completed by finding that the above can be achieved. That is, the light emitting device structure of the present invention is a light emitting device structure in which an n-type semiconductor layer and a p-type semiconductor layer are pn-junctioned, and an upper electrode is formed on the light extraction surface and a lower electrode is formed on the opposite back surface. A current blocking layer is formed between a pn junction portion immediately below the upper electrode and the upper electrode, and the current blocking layer is preferably an n-type or p-type semiconductor layer or an electrically insulating layer, and more preferably The current blocking layer is formed in the same or similar shape as the upper electrode, has an area of at least ½ of the upper electrode, and has a thickness of 0.05 to 10.0 μm. It is something.

【0006】[0006]

【作用】上記構成によれば、上部電極とその直下方向の
pn接合部間に電流ブロック層を形成したので、電流は
このブロック層を迂回して流れるようになり、上記ブロ
ック層直下方向のpn接合部周囲に電流が集中して流れ
る。したがって、上部電極直下のpn接合部分に電流が
集中することが防止される。また、ブロック層直下方向
のpn接合部周囲に電流が集中して流れるので、この部
分が強発光となり、この強発光は上部電極に吸収されに
くくなる。したがって、発光素子の強発光を効率的に外
部に取り出すことが可能となり、発光素子の輝度を向上
させることができる。
According to the above structure, since the current block layer is formed between the upper electrode and the pn junction portion immediately below it, the current flows around the block layer, and the pn in the direction directly below the block layer. The current concentrates around the junction. Therefore, it is possible to prevent current from concentrating on the pn junction portion just below the upper electrode. In addition, since the current is concentrated and flows around the pn junction immediately below the block layer, this portion emits strong light, and this strong light is less likely to be absorbed by the upper electrode. Therefore, the strong light emission of the light emitting element can be efficiently extracted to the outside, and the brightness of the light emitting element can be improved.

【0007】以下、本発明を図面に基づきより詳細に説
明する。図1は、本発明の発光素子の基本構成を示す模
式断面図である。前記従来の発光素子と同一箇所には同
一符号を付し、その詳細な説明は省略する。同図におい
て、前記図5と相違するところは、上部電極7の直下方
向の電流拡散層3とp型/n型半導体層4との境界部9
に電流ブロック層2を形成している点である。
Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing the basic structure of the light emitting device of the present invention. The same parts as those of the conventional light emitting device are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, the difference from FIG. 5 is that the boundary portion 9 between the current diffusion layer 3 and the p-type / n-type semiconductor layer 4 immediately below the upper electrode 7 is different.
The point is that the current blocking layer 2 is formed on.

【0008】本発明の発光素子を構成する半導体材料と
しては特に制限はなく、通常LED等の発光素子材料と
して用いられるものがいずれも使用できる。その具体例
としては、InP系,GaAs系,GaP系,AlGa
As系,GaInP系,GaInAs系等の各種p型ま
たはn型半導体を用いたものが挙げられる。図4は発光
素子の伝導型を示すものであって、本発明の発光素子構
造では図4(a)または(b)のいずれの構成としても
よい。
The semiconductor material constituting the light emitting device of the present invention is not particularly limited, and any of the materials usually used as a light emitting device such as an LED can be used. Specific examples thereof include InP-based, GaAs-based, GaP-based, AlGa
Examples include those using various p-type or n-type semiconductors such as As type, GaInP type, and GaInAs type. FIG. 4 shows the conduction type of the light emitting element, and the light emitting element structure of the present invention may have either of the configurations of FIG. 4 (a) or (b).

【0009】なお、電流拡散層3は必要に応じて設けら
れ、通常キャリア濃度が5×1017cm-3以上の高キャリ
ア濃度層が適用される。上部電極直下に該層3を設ける
ことにより、電流拡散性が改善されて、上部電極とpn
接合部との距離が近接していても、しかも上部電極とし
て面積の小さいドット状電極を用いた場合でも、pn接
合部の全面に電流が流れるようになり、発光素子の輝度
が向上するので好ましい。
The current spreading layer 3 is provided as needed, and a high carrier concentration layer having a carrier concentration of 5 × 10 17 cm -3 or more is usually applied. By providing the layer 3 directly under the upper electrode, the current diffusion property is improved, and the upper electrode and the pn
Even if the distance to the junction is close and a dot-shaped electrode having a small area is used as the upper electrode, a current flows through the entire surface of the pn junction, which improves the brightness of the light emitting element, which is preferable. .

【0010】この電流拡散層は、例えばGaInp系に
ついて述べると、p型GaInp層上に高キャリア濃度
のp+ GaInp層をエピタキシャル成長により形成す
る方法、p型GaInp層としてエピタキシャル成長し
た後、Zn,Mg,Be,Cd等の不純物拡散によって
表面層のキャリア濃度を高くして電流拡散層とする方
法、p型の不純物をイオン化してp型GaInp層表面
に打ち込むイオン注入法によって電流拡散層を形成する
方法などが挙げられる。
This current diffusion layer will be described, for example, in a GaInp system. A method of forming a p + GaInp layer having a high carrier concentration on the p-type GaInp layer by epitaxial growth. After the epitaxial growth of the p-type GaInp layer, Zn, Mg, A method of increasing the carrier concentration of the surface layer to form a current diffusion layer by diffusion of impurities such as Be and Cd, and a method of forming a current diffusion layer by ion implantation in which p-type impurities are ionized and implanted into the surface of the p-type GaInp layer. And so on.

【0011】この電流拡散層の厚さは、この層自身が光
の自己吸収性を有するため、電流拡散効果を発揮する限
りにおいては可及的に薄い方が好ましく、通常は5μm
以下、好ましくは3μm以下とするのがよい。
The thickness of the current diffusion layer is preferably as thin as possible, as long as the current diffusion effect is exhibited, because the layer itself has a self-absorption property of light.
Hereafter, it is preferably 3 μm or less.

【0012】上部電極7は、直下層がp層の場合、Au
Be,AuZn,AuSn、また、直下層がn層の場
合、AuGe等の材料を、半導体素子の光取り出し面の
表面に真空蒸着等の方法により被着した後、パターニン
グ、アニーリング等の通常の処理を施し、半導体の光取
り出し面の中央部や端部等の適当な位置に任意の形状に
成形する。この電極の形状は、特に制限はなく各種形状
が採用可能であるが、形成の容易性などの点からドット
状電極とすることが好ましい。
The upper electrode 7 is made of Au when the layer immediately below is a p-layer.
When Be, AuZn, AuSn, or the immediately underlying layer is an n-layer, a material such as AuGe is deposited on the surface of the light extraction surface of the semiconductor element by a method such as vacuum deposition, and then a normal treatment such as patterning or annealing is performed. Then, it is molded into an arbitrary shape at an appropriate position such as a central portion or an end portion of the light extraction surface of the semiconductor. The shape of this electrode is not particularly limited and various shapes can be adopted, but it is preferable to use a dot-shaped electrode from the viewpoint of ease of formation.

【0013】下部電極8は、直下層がn層の場合、Au
Be,AuZn,AuSn、直下層がp層の場合、Au
Ge等の材料を、上部電極7の場合と同様にして発光素
子下部表面に被着し、ダイシング等の方法により平板状
等の任意の大きさに成形する。
The lower electrode 8 is made of Au when the immediately lower layer is an n layer.
Be, AuZn, AuSn, Au when the layer immediately below is a p-layer
A material such as Ge is deposited on the lower surface of the light emitting element in the same manner as in the case of the upper electrode 7, and is shaped into an arbitrary size such as a flat plate by a method such as dicing.

【0014】電流ブロック層2は、電流を阻止する機能
を有するものであればよく、本発明では、p型またはn
型半導体あるいは電気絶縁性材料により電流ブロック層
を形成して電流阻止機能を持たせるものである。上記p
型またはn型半導体からなる電流ブロック層は、半導体
の整流作用を利用して電流阻止機能を持たせるものであ
る。この整流作用とは、図3で示すように、半導体中に
pn接合部を形成すると、例えば(A)の場合では、電
流は半導体中を流れるが、(B)の場合では、電流は流
れず絶縁体になることをいい、本発明はこの絶縁体にな
る性質を利用するものである。
The current blocking layer 2 may be of any type as long as it has a function of blocking current, and in the present invention, it is of p-type or n-type.
The current blocking layer is made of a semiconductor or an electrically insulating material to have a current blocking function. Above p
The current blocking layer made of a n-type or n-type semiconductor has a current blocking function by utilizing the rectifying action of the semiconductor. This rectifying action means that when a pn junction is formed in a semiconductor as shown in FIG. 3, for example, in the case of (A), a current flows through the semiconductor, but in the case of (B), no current flows. It means to be an insulator, and the present invention utilizes the property of becoming an insulator.

【0015】上記p型またはn型半導体としては基板に
格子整合する材料であればいずれも使用でき、例えばA
lGaInP/GaAs sub.系ではGaAs層が
一般的に使用でき、GaInP/GaAsP sub.
系ではGaInP層、GaAsP層が使用できる。ま
た、電気絶縁性材料としては、電流を阻止する機能を有
するものであればよく、例えばSiO2 ,SiN,Al
2 3 等が使用できるが、本発明では基板との格子整合
が可能でブロック層上への他層の成長を容易とできる上
記p型またはn型半導体の使用が好ましい。
As the p-type or n-type semiconductor, any material can be used as long as it is lattice-matched to the substrate.
lGaInP / GaAs sub. In the system, a GaAs layer is generally used, and GaInP / GaAsP sub.
In the system, a GaInP layer and a GaAsP layer can be used. Further, as the electrically insulating material, any material having a function of blocking an electric current may be used, and for example, SiO 2 , SiN, Al
2 O 3 or the like can be used, but in the present invention, it is preferable to use the above-mentioned p-type or n-type semiconductor which can lattice match with the substrate and facilitate the growth of another layer on the block layer.

【0016】上記電流ブロック層2は、上記材料をMO
CVD法,MBE法,LPE法等を用いた多段階成長に
よって、上部電極7の直下の電流拡散層3とp型/n型
半導体層4との境界部に、あるいはp型/n型半導体層
4中に形成する。
The current blocking layer 2 is formed by using the above-mentioned material in MO.
By the multi-step growth using the CVD method, the MBE method, the LPE method, or the like, at the boundary between the current diffusion layer 3 and the p-type / n-type semiconductor layer 4 immediately below the upper electrode 7, or the p-type / n-type semiconductor layer. Form in 4.

【0017】この電流ブロック層2は、上部電極の形状
に応じて任意の形状に形成できるので、上部電極の形状
と同一または相似形とし、その面積が上部電極の1/2
以上、好ましくは0.8〜2、特に好ましくは1.0〜
1.5になるように形成すればよい。例えば、上部電極
がドット状であれば、その直径の少なくとも1/2以上
の直径を有するドット状の電流ブロック層とすればよ
い。また、例えば、上部電極の最大幅の4/5の幅を有
し、一方向へ帯状に形成したものでもよい。上記電流ブ
ロック層の面積が上部電極の1/2未満であれば、電極
直下に流れ易くなり電流ブロック効果が小さくなり好ま
しくない。一方、2倍を越えるようになると、発光する
pn接合部の面積が小さくなり、発光素子の高輝度化が
達成できないので好ましくない。
Since the current blocking layer 2 can be formed in an arbitrary shape according to the shape of the upper electrode, it has the same shape as or similar to the shape of the upper electrode, and its area is ½ of that of the upper electrode.
Or more, preferably 0.8 to 2, and particularly preferably 1.0 to
It may be formed to have a thickness of 1.5. For example, if the upper electrode has a dot shape, a dot-shaped current blocking layer having a diameter of at least ½ or more of the diameter may be used. Further, for example, it may have a width of 4/5 of the maximum width of the upper electrode, and may be formed in a band shape in one direction. If the area of the current blocking layer is less than ½ of that of the upper electrode, the current blocking layer easily flows directly under the electrode and the current blocking effect is reduced, which is not preferable. On the other hand, if it exceeds 2 times, the area of the pn junction that emits light becomes small, and high brightness of the light emitting element cannot be achieved, which is not preferable.

【0018】この電流ブロック層2の厚さは、0.05
〜10μm、好ましくは0.1〜5μm ,特に好ましく
は0.5〜2μm である。電流ブロック層の厚さが、
0.05μm未満となると、膜厚の制御が困難となり、
また、電流をブロックできなくなり好ましくない。一
方、10μmを越えると、電流拡散層が厚くなり発光素
子の光取り出し効率が低下するとともに、コストが高く
つき好ましくない。
The thickness of this current blocking layer 2 is 0.05.
The thickness is from 10 to 10 μm, preferably from 0.1 to 5 μm, and particularly preferably from 0.5 to 2 μm. The thickness of the current blocking layer is
If it is less than 0.05 μm, it becomes difficult to control the film thickness,
In addition, the current cannot be blocked, which is not preferable. On the other hand, if the thickness exceeds 10 μm, the current diffusion layer becomes thick and the light extraction efficiency of the light emitting element decreases, and the cost becomes high, which is not preferable.

【0019】上記電流ブロック層2および上部電極7
は、電流ブロック層2が上部電極7の直下方向に位置す
るようにそれぞれ形成する。図1では、上部電極7を光
取り出し面の中央部に、電流ブロック層2を上記上部電
極7の直下方向の電流拡散層3とp型/n型半導体層4
の境界面に位置するように形成しているが、図2に示す
ように、上部電極7を光取り出し面の端部に形成し、上
記と同様にそれに対応する位置に電流ブロック層2を形
成することができる。このように、電流ブロック層2が
上部電極7の直下方向に位置するように形成されれば、
どの位置でも差し支えない。
The current blocking layer 2 and the upper electrode 7
Are formed so that the current block layer 2 is located directly below the upper electrode 7. In FIG. 1, the upper electrode 7 is at the center of the light extraction surface, and the current blocking layer 2 is the current diffusion layer 3 and the p-type / n-type semiconductor layer 4 directly below the upper electrode 7.
2, the upper electrode 7 is formed at the end of the light extraction surface, and the current block layer 2 is formed at a position corresponding to the upper electrode 7, as shown in FIG. can do. In this way, if the current block layer 2 is formed so as to be located directly below the upper electrode 7,
Any position is acceptable.

【0020】本発明の発光素子構造、例えば図4(a)
に示す構造では、上部電極7を正極に下部電極8を負極
として通電すると、電流は半導体の整流作用によって、
n型半導体2からp型半導体4へは流れない。このため
電流は上部電極7の直下部分にあたるn型半導体層2を
迂回するように流れる。したがって、電流は上部電極7
の直下部分の周囲を集中して流れるので、発光素子Hは
この部分で強発光となる。また、上部電極7の直下方向
のpn接合部では、ほとんど発光しないので、この発光
が上部電極7に吸収されるとしても発光素子全体の発光
量にはほとんど影響ない。この結果、発光素子の発光効
率が向上する。
The light emitting device structure of the present invention, for example, FIG.
In the structure shown in (1), when the upper electrode 7 is a positive electrode and the lower electrode 8 is a negative electrode, a current flows due to the rectification action of the semiconductor.
There is no flow from the n-type semiconductor 2 to the p-type semiconductor 4. Therefore, the current flows so as to bypass the n-type semiconductor layer 2 which is the portion directly below the upper electrode 7. Therefore, the current is
Since the current flows intensively around the portion immediately below, the light emitting element H emits strong light in this portion. In addition, since the pn junction immediately below the upper electrode 7 emits almost no light, even if this luminescence is absorbed by the upper electrode 7, the amount of light emitted from the entire light emitting element is hardly affected. As a result, the luminous efficiency of the light emitting element is improved.

【0021】なお、上記例では、電流拡散層3および半
導体層4をp型半導体に、電流ブロック層2をn型半導
体として形成したが、本発明では、図4(b)に示すよ
うに、このp型とn型を逆にして、電流を下部電極8b
から上部電極7bへ流す構成としても、上記図4(a)
と同様の作用、効果が得られる。
In the above example, the current diffusion layer 3 and the semiconductor layer 4 are formed as p-type semiconductors, and the current block layer 2 is formed as an n-type semiconductor. However, in the present invention, as shown in FIG. By reversing the p-type and n-type, a current is applied to the lower electrode 8b.
From the above-mentioned FIG.
The same action and effect as can be obtained.

【0022】[0022]

【実施例】以下、実施例を示し本発明を具体的に説明す
る。なお、本発明がこれに限定されるものでないことは
言うまでもない。 実施例1 厚さ350μmのn型GaAsP基板上に、厚さ10μ
mのn型GaInP層および厚さ3μmのp型GaIn
P層を順次エピタキシャル成長した後、このp型GaI
nP層上に、LPE法によって厚さ2μmのn型GaI
nP層を全面に成長させた。その後、フォトリソグラフ
ィーを用いてドット状のGaInP層を残し、それ以外
をエッチングで除去し電流ブロック層を形成した。さら
にこの電流ブロック層およびp型GaInP層上に厚さ
5μmのp型GaInP層をエピタキシャル成長させ
た。ついで、成長後のウエハー表面にAuBeを真空蒸
着した後、パターニング処理を施し、チップ化したとき
の光取り出し面となるチップ表面中央部に直径150μ
mの円形電極を形成した。一方、ウエハー裏面にAuS
nを真空蒸着した後、ダイシングしてチップ化し、図1
に示す構成の発光素子Hを作製した。
EXAMPLES The present invention will be described in detail below with reference to examples. Needless to say, the present invention is not limited to this. Example 1 On an n-type GaAsP substrate having a thickness of 350 μm, a thickness of 10 μm
m n-type GaInP layer and 3 μm thick p-type GaInP layer
After the P layer is sequentially epitaxially grown, the p-type GaI
On the nP layer, n-type GaI having a thickness of 2 μm is formed by the LPE method.
The nP layer was grown on the entire surface. After that, the dot-shaped GaInP layer was left by photolithography, and the rest was removed by etching to form a current block layer. Further, a p-type GaInP layer having a thickness of 5 μm was epitaxially grown on the current blocking layer and the p-type GaInP layer. Next, after vacuum-depositing AuBe on the surface of the wafer after growth, patterning treatment was performed, and a diameter of 150 μm was formed in the central portion of the chip surface which became the light extraction surface when the chip was formed.
m circular electrodes were formed. On the other hand, AuS on the backside of the wafer
n is vacuum-deposited and then diced into chips, as shown in FIG.
A light emitting device H having the structure shown in was produced.

【0023】この発光素子Hの上部電極7と下部電極8
間に20mAの電流を加え、発光素子Hを発光させた。
このときの輝度を輝度測定計(フォトメーターモデル5
50−1 EG&G社製)を用いて測定したところ、表
1に示すような結果が得られた。
The upper electrode 7 and the lower electrode 8 of this light emitting device H
A current of 20 mA was applied between them to cause the light emitting device H to emit light.
The brightness at this time is measured by a brightness meter (photometer model 5
50-1 manufactured by EG & G) and the results shown in Table 1 were obtained.

【0024】実施例2〜3 上記実施例1において、電流ブロック層の直径を変える
以外は全く同様にして発光素子を作製した。電流ブロッ
ク層の直径120μmのものを実施例2、直径180μ
mのものを実施例3とし、これらの発光素子の輝度を上
記実施例1と同様に測定したところ、表1に示す結果が
得られた。
Examples 2 to 3 A light emitting device was manufactured in the same manner as in Example 1 except that the diameter of the current blocking layer was changed. The current blocking layer having a diameter of 120 μm was used in Example 2, 180 μm in diameter.
When m was used as Example 3 and the luminance of these light emitting devices was measured in the same manner as in Example 1, the results shown in Table 1 were obtained.

【0025】比較例1 上記実施例1において、p型GaInP層内に電流ブロ
ック層を形成しない以外は全く同様にして発光素子を作
製した。この発光素子の輝度を上記実施例1と同様に測
定したところ、表1に示す結果が得られた。
Comparative Example 1 A light emitting device was prepared in the same manner as in Example 1 except that the current blocking layer was not formed in the p-type GaInP layer. When the luminance of this light emitting device was measured in the same manner as in Example 1, the results shown in Table 1 were obtained.

【0026】比較例2〜3 上記実施例1において、電流ブロック層の面積を表1に
示すように変更した以外は全く同様にして発光素子を作
製した。電流ブロック層の直径20μmのものを比較例
2、直径300μmのものを比較例3とし、これらの発
光素子の輝度を上記実施例1と同様に測定したところ、
表1に示す結果が得られた。
Comparative Examples 2 to 3 Light emitting devices were prepared in the same manner as in Example 1 except that the area of the current blocking layer was changed as shown in Table 1. When the current blocking layer having a diameter of 20 μm was used as Comparative Example 2 and the current blocking layer having a diameter of 300 μm was used as Comparative Example 3, the brightness of these light emitting devices was measured in the same manner as in Example 1 above.
The results shown in Table 1 were obtained.

【0027】[0027]

【表1】 [Table 1]

【0028】上記表1から明らかなように、本発明の発
光素子構造のものは、輝度が5.2mcd と高い値を示
し、従来電流ブロック層を形成しない発光素子構造のも
のよりも、輝度が57%向上したものであった。
As is clear from Table 1, the light emitting device structure of the present invention has a high brightness of 5.2 mcd, which is higher than that of the conventional light emitting device structure in which the current blocking layer is not formed. It was a 57% improvement.

【0029】[0029]

【発明の効果】以上詳述したように、本発明によれば、
上部電極とその直下方向のpn接合部間に電流ブロック
層を形成したので、上部電極直下のpn接合部分に電流
が集中することが防止される。また、ブロック層直下方
向のpn接合部周囲に電流が集中して流れるので、発光
素子の強発光を効率的に外部に取り出すことが可能とな
り、発光素子の輝度を向上させることができる。したが
って、従来の発光素子構造のものよりもその輝度を大幅
に向上させることができ、高輝度の発光素子となる。
As described in detail above, according to the present invention,
Since the current blocking layer is formed between the upper electrode and the pn junction immediately below the upper electrode, current is prevented from concentrating on the pn junction directly below the upper electrode. In addition, since the current concentrates and flows around the pn junction portion just below the block layer, strong light emission of the light emitting element can be efficiently extracted to the outside, and the brightness of the light emitting element can be improved. Therefore, the brightness of the light emitting device can be significantly improved as compared with that of the conventional light emitting device structure, resulting in a high brightness light emitting device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による発光素子構造を示す模
式断面図である。
FIG. 1 is a schematic cross-sectional view showing a light emitting device structure according to an embodiment of the present invention.

【図2】本発明の他の実施例による発光素子構造を示す
模式断面図である。
FIG. 2 is a schematic cross-sectional view showing a light emitting device structure according to another embodiment of the present invention.

【図3】半導体の整流作用を説明する模式図である。FIG. 3 is a schematic diagram illustrating a rectifying function of a semiconductor.

【図4】本発明の発光素子構造における半導体伝導型構
成を示す模式断面図である。
FIG. 4 is a schematic cross-sectional view showing a semiconductor conduction type structure in the light emitting device structure of the present invention.

【図5】従来の発光素子構造を示す模式断面図である。FIG. 5 is a schematic cross-sectional view showing a conventional light emitting device structure.

【符号の説明】[Explanation of symbols]

1 pn接合部 2 電流ブロック層 3 p型/n型電流拡散層 4 p型/n型半導体層 5 n型/p型半導体層 6 n型/p型半導体基板 7 上部電極 8 下部電極 9 境界部 H 発光素子 1 pn junction 2 current blocking layer 3 p-type / n-type current diffusion layer 4 p-type / n-type semiconductor layer 5 n-type / p-type semiconductor layer 6 n-type / p-type semiconductor substrate 7 upper electrode 8 lower electrode 9 boundary H light emitting element

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 n型半導体層とp型半導体層とをpn接
合し、光取り出し面上に上部電極を、反対側裏面上に下
部電極を形成する発光素子構造であって、該上部電極直
下方向のpn接合部と上部電極間に電流ブロック層を形
成してなる発光素子構造。
1. A light emitting device structure in which an n-type semiconductor layer and a p-type semiconductor layer are pn-junctioned, and an upper electrode is formed on a light extraction surface, and a lower electrode is formed on a back surface on the opposite side, which is directly below the upper electrode. A light emitting device structure in which a current blocking layer is formed between the pn junction and the upper electrode in the direction.
【請求項2】 電流ブロック層が、n型またはp型半導
体層あるいは電気絶縁性層である請求項1記載の発光素
子構造。
2. The light emitting device structure according to claim 1, wherein the current blocking layer is an n-type or p-type semiconductor layer or an electrically insulating layer.
【請求項3】 電流ブロック層が、上部電極と同一また
は相似形に形成されてなり、その面積が上部電極の少な
くとも1/2を有し、かつ、その厚さが0.05〜1
0.0μmである請求項1記載の発光素子構造。
3. The current blocking layer is formed to be the same as or similar to the upper electrode, has an area of at least ½ of the upper electrode, and has a thickness of 0.05 to 1.
The light emitting device structure according to claim 1, which has a thickness of 0.0 μm.
JP18011892A 1992-07-07 1992-07-07 Light-emitting element structure Pending JPH0629570A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18011892A JPH0629570A (en) 1992-07-07 1992-07-07 Light-emitting element structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18011892A JPH0629570A (en) 1992-07-07 1992-07-07 Light-emitting element structure

Publications (1)

Publication Number Publication Date
JPH0629570A true JPH0629570A (en) 1994-02-04

Family

ID=16077738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18011892A Pending JPH0629570A (en) 1992-07-07 1992-07-07 Light-emitting element structure

Country Status (1)

Country Link
JP (1) JPH0629570A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023181A (en) * 2001-07-06 2003-01-24 Showa Denko Kk GaP BASED LIGHT EMITTING DIODE AND ITS FABRICATING METHOD
JP2005123526A (en) * 2003-10-20 2005-05-12 Oki Data Corp Semiconductor device, led head, and image forming device
WO2006080958A1 (en) * 2005-01-24 2006-08-03 Cree, Inc. Led with curent confinement structure and surface roughening

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023181A (en) * 2001-07-06 2003-01-24 Showa Denko Kk GaP BASED LIGHT EMITTING DIODE AND ITS FABRICATING METHOD
JP2005123526A (en) * 2003-10-20 2005-05-12 Oki Data Corp Semiconductor device, led head, and image forming device
WO2006080958A1 (en) * 2005-01-24 2006-08-03 Cree, Inc. Led with curent confinement structure and surface roughening
US7335920B2 (en) 2005-01-24 2008-02-26 Cree, Inc. LED with current confinement structure and surface roughening
US8541788B2 (en) 2005-01-24 2013-09-24 Cree, Inc. LED with current confinement structure and surface roughening
US8772792B2 (en) 2005-01-24 2014-07-08 Cree, Inc. LED with surface roughening

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