JPH0629412A - Flattening method of interlayer insulating film - Google Patents
Flattening method of interlayer insulating filmInfo
- Publication number
- JPH0629412A JPH0629412A JP18328092A JP18328092A JPH0629412A JP H0629412 A JPH0629412 A JP H0629412A JP 18328092 A JP18328092 A JP 18328092A JP 18328092 A JP18328092 A JP 18328092A JP H0629412 A JPH0629412 A JP H0629412A
- Authority
- JP
- Japan
- Prior art keywords
- film
- heat treatment
- interlayer insulating
- insulating film
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は層間絶縁膜の平坦化方法
に関し、特に段差が形成された半導体基板表面上に堆積
した層間絶縁膜を平坦化する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of flattening an interlayer insulating film, and more particularly to a method of flattening an interlayer insulating film deposited on a surface of a semiconductor substrate having steps.
【０００２】[0002]
【従来の技術】従来、半導体基板上の表面段差を少なく
するために、図２（ａ）のように、ポリシリコン等から
なる配線２により段差の形成された基板上に、ホウ素や
リンを含有したシリコン酸化膜（ＢＰＳＧ膜）３または
リンを含有したシリコン酸化膜（ＰＳＧ膜）を層間絶縁
膜として形成し、次で図２（ｂ）のように、窒素雰囲気
で熱処理することによりリフローさせ、ＢＰＳＧ膜３を
平坦化させる方法が一般的に用いられている。2. Description of the Related Art Conventionally, in order to reduce a surface step on a semiconductor substrate, as shown in FIG. 2A, a substrate having a step formed by a wiring 2 made of polysilicon or the like contains boron or phosphorus. The silicon oxide film (BPSG film) 3 or the silicon oxide film (PSG film) containing phosphorus is formed as an interlayer insulating film, and is then reflowed by heat treatment in a nitrogen atmosphere as shown in FIG. 2B. A method of flattening the BPSG film 3 is generally used.
【０００３】また、高温・長時間の熱処理は不純物の拡
散が大きくなるために、数秒から数十秒の短時間熱処理
（ＲＴＡ）が試みられている。さらに、ＢＰＳＧ膜やＰ
ＳＧ膜を水蒸気雰囲気で熱処理すると窒素雰囲気で熱処
理するより高い平坦性が得られることが知られている。Further, since high temperature and long time heat treatment causes large diffusion of impurities, short time heat treatment (RTA) of several seconds to several tens of seconds has been attempted. Furthermore, BPSG film and P
It is known that heat treatment of an SG film in a steam atmosphere provides higher flatness than heat treatment in a nitrogen atmosphere.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の層間絶
縁膜の平坦化方法では、以下のような問題がある。素子
の微細化に伴い、ＭＯＳトランジスタのソース、ドレイ
ンなどの不純物拡散層の深さを制御することが重要とな
ってきた。そのためにはリフローのための熱処理を７５
０℃から８５０℃という低温にしなければならない。し
かし、ＢＰＳＧ膜をそのような温度で窒素雰囲気で熱処
理しても十分な平坦形状が得られない。また、ＰＴＡで
も不純物の拡散を抑えるような時間の熱処理では平坦性
に欠ける。さらに、水蒸気雰囲気での熱処理ではシリコ
ン基板を酸化してしまい、素子の抵抗が高くなるなどの
問題が生じる。The above-described conventional method of planarizing the interlayer insulating film has the following problems. With the miniaturization of elements, it has become important to control the depth of impurity diffusion layers such as the source and drain of a MOS transistor. For that purpose, heat treatment for reflow is 75
It must be as low as 0 ° C to 850 ° C. However, even if the BPSG film is heat-treated at such a temperature in a nitrogen atmosphere, a sufficient flat shape cannot be obtained. Further, even PTA lacks flatness by heat treatment for a time period that suppresses diffusion of impurities. Further, the heat treatment in the water vapor atmosphere oxidizes the silicon substrate, which causes a problem that the resistance of the element increases.
【０００５】本発明の目的は、このような従来の問題を
解決し、層間絶縁膜のリフロー処理の低温化を実現する
方法を提供することにある。An object of the present invention is to provide a method for solving such a conventional problem and realizing a low temperature reflow process of an interlayer insulating film.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するため
に、本発明の層間絶縁膜の平坦化方法は、段差が形成さ
れた半導体基板表面をシリコン酸化膜で覆う工程と、そ
のシリコン絶縁膜を低融点ガラスを形成する不純物の拡
散雰囲気で熱処理する工程とを含むものである。In order to achieve the above object, a method of flattening an interlayer insulating film according to the present invention comprises a step of covering a surface of a semiconductor substrate having a step with a silicon oxide film, and the silicon insulating film. Is heat-treated in an impurity diffusion atmosphere to form a low melting point glass.
【０００７】[0007]
【作用】本発明においては、リフローを不純物拡散雰囲
気で熱処理することにより行うもので、熱処理中にＢＰ
ＳＧ膜表面に低融点ガラス膜が形成され、それが粘性を
もつために低温でも平坦化が可能となる。In the present invention, reflow is performed by heat treatment in an impurity diffusion atmosphere.
A low melting glass film is formed on the surface of the SG film, and since it has viscosity, it becomes possible to flatten even at low temperatures.
【０００８】[0008]
【実施例】次に本発明について図面を参照し説明する。
図１（ａ）〜（ｃ）は、本発明の一実施例を説明するた
めの半導体チップの断面図である。The present invention will be described below with reference to the drawings.
1A to 1C are sectional views of a semiconductor chip for explaining an embodiment of the present invention.
【０００９】まず図１（ａ）に示したように、シリコン
基板１上にポリシリコンからなる配線２を形成したの
ち、配線による段差を覆うようにＢＰＳＧ膜３を形成す
る。First, as shown in FIG. 1A, a wiring 2 made of polysilicon is formed on a silicon substrate 1, and then a BPSG film 3 is formed so as to cover a step due to the wiring.
【００１０】次に図１（ｂ）のように、ＢＰＳＧ膜３の
リフロー処理をホウ素を含有するガスを導入した熱処理
炉中で行う。ホウ素を含有するガスは、例えば、ホウ素
酸化物を熱処理炉に挿入することにより生成する。熱処
理中、雰囲気のホウ素がＢＰＳＧ膜３に拡散し、ＢＰＳ
Ｇ膜３の表面付近でホウ素酸化物に近い組成の低融点ガ
ラス膜４が形成される。Next, as shown in FIG. 1B, the BPSG film 3 is reflowed in a heat treatment furnace into which a gas containing boron is introduced. The gas containing boron is generated, for example, by inserting boron oxide into a heat treatment furnace. During the heat treatment, boron in the atmosphere diffuses into the BPSG film 3,
A low melting point glass film 4 having a composition close to that of boron oxide is formed near the surface of the G film 3.
【００１１】次に図１（ｃ）に示すように、７５０〜８
５０℃で熱処理しガラス膜４をリフローさせる。ホウ素
酸化物の融点は約５００℃と非常に低いので熱処理温度
を７５０℃から８５０℃程度にしても低融点ガラス膜４
は粘性をもっているため、十分な平坦性を得ることがで
きる。Next, as shown in FIG.
Heat treatment is performed at 50 ° C. to reflow the glass film 4. Since the melting point of boron oxide is extremely low at about 500 ° C., the low melting point glass film 4 can be obtained even if the heat treatment temperature is set to about 750 ° C.
Since is viscous, sufficient flatness can be obtained.
【００１２】[0012]
【発明の効果】以上詳述したようにこの発明によれば、
層間絶縁膜のリフロー処理を低温化できるので、微細な
素子形成が可能となり、半導体装置の集積率を向上させ
ることができるなどの効果がある。As described above in detail, according to the present invention,
Since the reflow process of the interlayer insulating film can be performed at a low temperature, fine elements can be formed, and the integration rate of the semiconductor device can be improved.
【図１】本発明の一実施例を説明するための半導体チッ
プの断面図。FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.
【図２】従来例を説明するための半導体チップの断面
図。FIG. 2 is a sectional view of a semiconductor chip for explaining a conventional example.
１ シリコン基板 ２ 配線 ３ ＢＰＳＧ膜 ４ 低融点ガラス膜 1 Silicon substrate 2 Wiring 3 BPSG film 4 Low melting point glass film
Claims (1)
コン酸化膜で覆う工程と、そのシリコン酸化膜を低融点
ガラスを形成する不純物の拡散雰囲気で熱処理する工程
とを含むことを特徴とする層間絶縁膜の平坦化方法。1. An interlayer comprising: a step of covering a surface of a semiconductor substrate on which a step is formed with a silicon oxide film; and a step of heat-treating the silicon oxide film in an impurity diffusion atmosphere for forming a low melting point glass. A method for planarizing an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18328092A JPH0629412A (en) | 1992-07-10 | 1992-07-10 | Flattening method of interlayer insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18328092A JPH0629412A (en) | 1992-07-10 | 1992-07-10 | Flattening method of interlayer insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629412A true JPH0629412A (en) | 1994-02-04 |
Family
ID=16132895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18328092A Withdrawn JPH0629412A (en) | 1992-07-10 | 1992-07-10 | Flattening method of interlayer insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629412A (en) |
-
1992
- 1992-07-10 JP JP18328092A patent/JPH0629412A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |