JPH0629408A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a contact hole self-aligned with a multilayered wiring in a semiconductor device. CONSTITUTION:The first barrier layers 16 and 18 are formed on the first conductive film 14, the barrier layers 16 and 18 and the conductive film 14 are patterned together to form the first wiring pattern 22. Next, an insulating film 28 is formed thereon. Next, the second conductive film 32 and the second barrier layers 34 and 36 are formed on the insulating layer 28 to pattern the barrier layers 34 and 36 and the conductive film 32 together to form the second wiring pattern 40. Next, an insulating film 44 is formed thereon. Next, an opening section 51 that reaches a substrate 10 is formed using at least one from the first barrier layers 16 and 18 and the second barrier layers 34 and 36 as a barrier for etching. Next, side-walls 54A-54C are formed on the side wall of the opening section 51. Finally, the third wiring pattern 56 is formed to contact the substrate 10 via the opening section 51.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a contact hole is formed in a wiring layer pattern in a self-aligned manner.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, it is difficult to obtain a design margin between a contact hole formed between internal wiring layer patterns and a wiring layer pattern adjacent to the hole. Is coming.

Further, in the conventional lithography technique, it is necessary to include an alignment margin between the contact hole and the wiring layer pattern in consideration of a mask shift and a margin of variation in the opening diameter of the hole. Is hindering

As a countermeasure against the above problem, a so-called "self-insulation" is performed in which a side wall (side wall) made of an insulating film is provided on the side surface of the wiring layer pattern to insulate the wiring layer pattern and the contact hole from each other. "Align-contact technology" has been developed. The conventional general "self-align-contact technique" is disclosed in Japanese Patent Laid-Open No. 2-30124. The "self-alignment-contact technique" disclosed in this publication is roughly as follows.

The polysilicon film and the CVD silicon oxide film are collectively patterned to obtain a pattern including an internal wiring layer (hereinafter referred to as a gate) on a silicon substrate. Then, a side wall made of a CVD silicon oxide film is formed on the side surface of the pattern including the gate. Then, a silicon nitride film and a polysilicon film are sequentially formed on the substrate including the pattern including the gate and the sidewall, respectively. This polysilicon film serves as an etching barrier, that is, a stopper layer when an opening (hereinafter referred to as a contact hole) is formed later. Then, a boron-phosphorus-silicon glass (hereinafter referred to as BPSG) film is formed on the polysilicon film. Then, the BPSG film is patterned by RIE using the polysilicon film as an etching barrier.
To obtain contact holes that substantially reach the substrate surface between the patterns including the gate. Then, the polysilicon film is removed from the contact hole by the CDE method using the silicon nitride film as an etching barrier. Next, the BPSG film is reflowed while the polysilicon film is thermally oxidized using the silicon nitride film as an oxidation barrier. Next, the BPSG film is used as an etching barrier through the contact hole, and the silicon nitride film and the oxide film formed on the substrate surface are removed by RIE. Then, an aluminum alloy film is formed on the BPSG film including the inside of the contact hole, and the aluminum alloy film is patterned to form an internal wiring layer connected to the substrate. However, the "self-alignment-contact technology" as described above
Is a method that can be applied only when a wiring layer pattern consisting of one layer is used.

In the future, it is inevitable that semiconductor devices will be further miniaturized and highly integrated. Along with this tendency, the internal wiring layers of semiconductor devices are currently not limited to only two wiring layers made of polysilicon and aluminum alloy, three layers, four layers,
.. is becoming a multilayer wiring.

However, for example, "self-alignment" is effective for a semiconductor device having a multi-layered wiring layer such that the second wiring layer is penetrated from the substrate to the first wiring layer to contact the substrate. The contact technology has not yet been developed.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to self-align with wiring layers, which is effective for a semiconductor device having multiple wiring layers. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming contact holes.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a first barrier layer is formed on a first conductive film formed on a semiconductor substrate, and the first barrier layer and the first barrier layer are formed. The first conductive film is collectively patterned to form a first wiring layer pattern. Then, a second insulating film is formed above the surface of the substrate so as to cover the first wiring layer pattern, and the second conductive film and the second barrier layer are formed on the second insulating film. Form sequentially. Then, the second barrier layer and the second conductive film are collectively patterned to form a second wiring layer pattern. Then, a third insulating film is formed above the surface of the substrate so as to cover the second pattern. Next, the opening reaching the semiconductor substrate is formed into the first,
At least one of the second barrier layers is used as an etching barrier to penetrate the first, second and third insulating films, and a fourth insulating film is formed on the side wall of the opening. Form sidewalls. Then, a third wiring layer pattern that contacts the substrate through the opening is formed.

Further, the first and second barrier layers are respectively stacked with a first substance film made of a first substance and a second substance film made of a second substance different from the first substance. It is characterized in that it is formed by.

A material having an insulating property is selected as the first material, and a material having an insulating property by being activated is selected as the second material, and after forming the opening, The method may further include the step of activating the second substance.

[0012]

In the above manufacturing method, the first wiring layer pattern is formed by collectively patterning the first barrier layer and the first conductive film. Also, the second
The second wiring layer pattern, which is electrically separated from the first wiring layer pattern by the second insulating film, simultaneously patterns the second barrier layer and the second conductive film. It is formed.

According to this method, when the second insulating film or the like is etched to obtain the opening reaching the surface of the semiconductor substrate, the etchant is the first wiring layer pattern or the second wiring layer pattern. The first and second conductive films are protected by the first and second barrier layers, respectively, even if they contact the negative electrode.
Therefore, the problem that the first and second conductive films are etched can be solved. Furthermore, on the side wall of the opening, a fourth
A side wall made of the insulating film is formed.

According to this method, the first and second portions are opened from the opening.
Even if the conductive film is exposed, the exposed surface is covered with the fourth insulating film. Therefore, even if the third wiring layer pattern is further formed in the opening, the exposed surface is not affected by the first and second conductive films. Third
Do not short-circuit with the wiring layer pattern. Further, each of the first and second barrier layers is formed by stacking a film made of a first substance and a film made of a second substance different from the first substance.

According to such a method, one of the films is provided for the first etchant, the other film is provided for the second etchant different from the first etchant, and so on. The etching resistance can be exhibited, and the etching resistance of each of the first barrier layer and the second barrier layer can be strengthened as a whole.

Further, a substance having an insulating property is selected as the first substance, and a substance exhibiting an insulating property by being activated is selected as the second substance. Then, after forming the opening, the second substance is activated.

According to such a method, even if a conductive substance is selected as the second substance, even if the second substance is an insulating substance by being at least activated. It can be made into an insulator by activating. The problem that the third wiring layer patterns are short-circuited via the first barrier layer or the second barrier layer can be solved.

Materials capable of realizing such a method include silicon, hafnium, tantalum, zirconium, tungsten-silicide, molybdenum-silicide, hafnium-silicide, tantalum-silicide and zirconium-silicide. In the case of these substances, the activation is oxidation. When the above substance is oxidized, its resistance value can be increased to that of an insulator.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In this description, common parts are denoted by common reference symbols throughout the drawings, and redundant description will be avoided. 1 to 14 are sectional views shown in the order of steps according to the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

First, the surface of the P-type silicon substrate 10 is thermally oxidized to form a silicon oxide film (SiO ₂ ; hereinafter referred to as a gate oxide film) 12 having a thickness of about 200 Å.
To get Then, a polysilicon film 14 having a thickness of about 3000 angstroms is deposited on the gate oxide film 12 by a low pressure CVD method (hereinafter referred to as LPCVD method). Then, phosphorus is diffused into the polysilicon film 14 by a vapor phase diffusion method using POCl ₃ as a source, so that the polysilicon film 14 is made to be a conductor (made N-type). Then, a silicon oxide film (SiO 2) having a thickness of about 3000 angstrom is formed on the polysilicon film 14 by the LPCVD method.
₂ ) Deposit 16. Then, a polysilicon film 18 having a thickness of about 200 Å is deposited on the silicon oxide film 16 by the LPCVD method (FIG. 1).

Next, a photoresist is applied on the polysilicon film 18. Then, this photoresist is etched by a photolithography method to obtain a gate (workpiece).
A resist pattern 20 corresponding to the contact line) is formed. Then, using the resist pattern 20 as a mask, the polysilicon film 18, the silicon oxide film 16, and the N-type polysilicon film 14 are sequentially etched by the RIE method to form a gate pattern of the N-type polysilicon film 14. And a first wiring layer pattern 22 including a barrier layer composed of the silicon oxide film 16 and the polysilicon film 18. Then, by using the wiring layer pattern 22 as a mask, N-type impurity ions, for example, arsenic (As) ions are ion-implanted into the P-type substrate 10 to become the source / drain of the transistor in the future. A type impurity layer 24 is obtained (FIG. 2).

Next, after removing the resist pattern 20, the upper part of the substrate 10 is covered so as to cover the wiring layer pattern 22.
By the LPCVD method, a silicon oxide film (SiO ₂ ) 26 having a thickness of about 500 Å, about 5000
A boron-phosphorus-silicate glass (BPSG) film 28 having an angstrom thickness is sequentially formed. The silicon oxide film 26 and the BPSG film 28 function as an interlayer insulating film (FIG. 3). Then, the BPSG film 28 is reflowed in a nitrogen atmosphere at a temperature of 850 ° C. to be flattened (FIG. 4).

Then, LPCVD is performed on the BPSG film 28.
By the method, a polysilicon film 30 having a thickness of about 1000 Å is deposited. Then, phosphorus is diffused into the polysilicon film 30 to make the polysilicon film 30 a conductor (N-type). Then, on the N-type polysilicon film 30, a DC magnetron sputtering method of about 20 is performed.
A tungsten silicide film (WSi ₂ ) 32 having a thickness of 00 angstrom is formed. Then, a silicon oxide film (SiO ₂ ) 34 having a thickness of about 3000 angstroms and a polysilicon film 36 having a thickness of about 500 angstroms are formed on the tungsten silicide film 32 by the LPCVD method (FIG. 5). ).

Next, a photoresist is applied on the polysilicon film 36. Next, this photoresist is etched by photolithography to form a resist pattern 38 corresponding to the second wiring layer. Then, using the resist pattern 38 as a mask, the polysilicon film 36, the silicon oxide film 34, the tungsten silicide film 32, and the N-type polysilicon film 30 are sequentially RI.
Etching is performed by the E method. As a result, a second wiring layer pattern 40 including a second wiring layer whose main conductor is the tungsten silicide film 32 and a barrier layer composed of the silicon oxide film 34 and the polysilicon film 36 is obtained. (Fig. 6).

Next, after removing the resist pattern 38, a silicon oxide film (SiO ₂ ) having a thickness of about 500 Å is formed on the BPSG film 28 by LPCVD so as to cover the wiring layer pattern 40. 42, about 70
A BPSG film 44 having a thickness of 00 angstrom is formed. The silicon oxide film 42 and the BPSG film 44 function as an interlayer insulating film (FIG. 7). Then BPSG
The film 44 is reflowed and planarized in a nitrogen atmosphere at a temperature of 850 ° C. (FIG. 8).

Next, a photoresist is applied on the BPSG film 44, and the photoresist is etched by the photolithography method to form a resist pattern 46 having a window 48 between the wiring layer patterns 40. At this time, the window 48 is formed so as to have a width wider than the width between the patterns 40 in a range including a portion to be contacted with the substrate 10. As a result, the side wall 47 of the window 48 comes to be located above the wiring layer pattern 40 (FIG. 9).

Then, using the resist pattern 46 as a mask, the BPSG film 44, the silicon oxide film 42 and the BPS film are formed.
G film 28, silicon oxide film 26 and gate oxide film 12
For example, RI using CHF ₃ ions as an etchant
Etching is performed by the E method. As a result, an opening 50 reaching the substrate 10 (N-type impurity layer 24 in the drawing) between the second wiring pattern 40 and the first wiring pattern 22 is obtained. This etching is performed on the second wiring layer pattern 40 when the polysilicon film 36 is etched by, for example, about 400 angstroms, and on the first wiring layer pattern 22 the polysilicon film 18 is etched. Is finished when, for example, about 200 angstroms are etched. This is because the etching rate of polysilicon is as low as 1/60 or less as compared with the etching rate of BPSG. After that, the resist pattern 46 is removed (FIG. 10).

Next, hydrogen combustion oxidation is performed at a temperature of 850 ° C. to expose the polysilicon films 14 and 1 exposed in the opening 50.
8, 30 and 36 and the surfaces of the tungsten silicide film 32 are oxidized to form oxides 14A, 18A and 30.
Change to A, 36A and 32A. At this time, the opening 50
The surface of the substrate 10 exposed inside is also oxidized, and a silicon oxide film (Si having a thickness of about 150 Å) is formed.
O ₂ ) 52 is formed (FIG. 11).

Next, including the inside of the opening 50, the BPSG
On the film 44, by the LPCVD method, about 2000 angstroms - forming a silicon nitride film (SiN _X) film 54 having a thickness of arm (Figure 12).

Next, the silicon nitride film 54 is etched by the RIE method to form the contact hole 51. At this time, the silicon nitride film 54 is mainly formed by the BPSG films 28 and 44.
On the side wall of the wiring layer and above the side walls of the wiring layers 32 and 14.
Remain as the insulating films 54A to 54C. Further, during this etching, the oxides 18A and 36A may be etched and lost. However, in this case, since the silicon oxide films 16 and 34 serve as etching stoppers, both the wiring layers 14 and 32 are not etched (FIG. 13).

Next, the BPS including the inside of the contact hole 51
A conductive (N-type) polysilicon film 56 containing phosphorus having a thickness of about 3000 angstroms is formed on the G film 44 by the LPCVD method. Then, the polysilicon film 56 is formed by photolithography through the contact hole 51 to the substrate 10 (N-type diffusion layer 2 in the figure).
4) The wiring layer pattern of the third layer which contacts 4) is patterned (FIG. 14).

According to the method of manufacturing a semiconductor device as described above, after forming the opening 50 in the BPSG film 44, on the sidewall of the opening 50, that is, on the BPSG film 44 and the wiring layer pattern 22, Sidewall insulating films 30A to 30C are formed on the sidewalls of 40. Therefore, the side wall insulating films 30A to 30C are not exposed to the ions for etching the BPSG films 28 and 44, and the remaining film of the side wall insulating films 30A to 30C is easily controlled. As a result, good insulation between the wiring layers can be obtained, and the withstand voltage between the wiring layers can be particularly improved.

The conductive polysilicon film 14 is also provided.
The tungsten silicide 32 is used as a barrier layer for the polysilicon films 18, 36 and the silicon oxide films 16, 3, respectively.
6 together with the pattern. For this reason, the pattern of the polysilicon films 18 and 36 becomes the same pattern as the wiring layer pattern, and it is possible to prevent the wiring layers from being shot through the polysilicon film 18.

Further, since the polysilicon films 18 and 36 are removed from the substrate 10 on which the contact holes 51 are to be formed during patterning, a step of removing the polysilicon films 18 and 36 from the substrate 10 later is also performed. unnecessary. Therefore, the process can be simplified and the productivity is improved.

Further, after the patterning, the polysilicon films 18 and 36 are left only above the gate, so that the remaining amount can be reduced. Therefore, its oxidation is easy. If the polysilicon films 18 and 36 can be sufficiently oxidized, there is no problem that the wiring layers 56 formed in the contact holes 51 are short-circuited via the polysilicon films 18 and 36.

Further, according to the above manufacturing method, the second wiring layer pattern 40 can be formed even after the BPSG film 28 covering the first wiring layer pattern 22 is reflowed. It is suitable for a device having a multilayer wiring structure.

Further, if the second wiring layer pattern 40 includes the polysilicon film 36 and the silicon oxide film 34 which serve as barrier layers, as in the first embodiment, the first wiring layer 40 is formed. The contact holes 51 can be formed in a self-aligned manner not only with the pattern 22 but also with the second wiring layer pattern 40. 15 to 25 are sectional views showing the order of steps according to the manufacturing method according to the second embodiment of the present invention. First, according to the manufacturing method described with reference to FIGS.
The structure shown in FIG. 15 is obtained.

Then, LPCVD is performed on the BPSG film 28.
By the method, a polysilicon film 30 having a thickness of about 1000 Å is deposited. Then, phosphorus is diffused into the polysilicon film 30 to make the polysilicon film 30 a conductor (N-type). Then, on the N-type polysilicon film 30, a DC magnetron sputtering method of about 20 is performed.
A tungsten silicide film (WSi ₂ ) 32 having a thickness of 00 angstrom is formed (FIG. 16).

Next, a photoresist is applied to the tungsten silicide film 32. Then, this photoresist is etched by a photolithography method, and a second
Resist pattern 38 corresponding to the second wiring layer pattern
To form. Next, using the resist pattern 38 as a mask, the tungsten silicide film 32 and the N-type polysilicon film 30 are sequentially etched by the RIE method, and the main conductive material is the tungsten silicide film 32.
A layer 41 wiring layer pattern is obtained (FIG. 17).

Then, after removing the resist pattern 38, a silicon oxide film 42, about 7,000 having a thickness of about 500 Å is formed on the BPSG film 28 including the wiring pattern 41 by LPCVD. A BPSG film 44 having an angstrom thickness is formed (FIG. 18). Next, the BPSG film 44 is reflowed in a nitrogen atmosphere at a temperature of 850 ° C. to be flattened (FIG. 19).

Next, a photoresist is applied and this photoresist is etched by the photolithography method to form a resist pattern 46 having a window 48 between the wiring layer patterns 41. At this time, the window 48 is in a range including a portion to be contacted with the substrate 10 and has a pattern.
It is formed to have a width narrower than the width between the two. As a result, the side wall 47 of the resist pattern 46 is disposed above the wiring layer pattern 22 (FIG. 20).

Then, using the resist pattern 46 as a mask, the BPSG film 44, the silicon oxide film 42 and the BPS film are formed.
G film 28, silicon oxide film 26 and gate oxide film 12
Is etched by, for example, the RIE method using CHF ₃ / CO ions as an etchant. As a result, the openings 50 reaching the substrate 10 (N-type impurity layer 24 in the drawing) between the wiring layer patterns 22 are obtained. BP
The etching rate of the polysilicon film 18 is 1/60 or less, which is sufficiently slower than that of the SG films 28 and 44. Therefore, the etching ends when the polysilicon film 18 is etched by, for example, about 200 Å on the first wiring layer pattern 22. After that, the resist pattern 46 is removed (FIG. 21).

Next, hydrogen combustion oxidation is performed at a temperature of 850 ° C. to expose the polysilicon films 14 and 18 exposed in the opening 50.
The surface of each is oxidized to form oxides 14A, 18A, 36
Change to A. At this time, the substrate 10 exposed in the opening 50
Is also oxidized to form a silicon oxide film 52 having a thickness of about 150 Å (FIG. 22).

Next, including the inside of the opening 50, the BPSG
On the film 44, by the LPCVD method, about 2000 angstroms - forming a silicon nitride film (SiN _X) film 54 having a thickness of arm (Figure 23).

Then, the silicon nitride film 54 is etched by the RIE method in the same manner as the method described with reference to FIG. 13 to form the contact hole 51. At this time, the silicon nitride film 54 is mainly formed by the BPSG films 28 and 44.
Side wall insulating films 54A and 54B are left on the side walls of the wiring layer 14 and above the side walls of the wiring layer 14. Further, during this etching, the oxide 18A may be etched and disappears, but in this case, since the silicon oxide film 34 serves as a stopper, the wiring layer 14 is not etched (FIG. 2).
4).

Next, BPS including the inside of the contact hole 51
A polysilicon film 5 containing phosphorus having a thickness of about 3000 angstroms is formed on the G film 44 by the LPCVD method.
6 is formed. Next, a third step is performed in which the polysilicon film 56 is brought into contact with the substrate 10 (N-type diffusion layer 24 in the figure) through the contact hole 51 using photolithography.
Patterning is performed on the second wiring layer pattern (FIG. 25).

According to the method of manufacturing a semiconductor device as described above, the contact hole 51 can be formed in a self-aligned manner with respect to the first-layer wiring pattern 22. Then, after forming an opening 50 communicating with the surface of the substrate 10 in the BPSG films 28 and 44, the side wall insulating film 5 is formed in the opening 50.
Since 4A and 54B are formed, the same effect as that of the first embodiment can be obtained. FIG. 26 is a sectional view showing the final sectional shape of a semiconductor device formed by the manufacturing method according to the third embodiment of the present invention.

As shown in FIG. 26, in a semiconductor device having three or more wiring layers, it is possible to form the contact hole 51 by combining the methods described in the first and second embodiments. is there.

In FIG. 26, reference numeral 22 ₁ indicates a pattern including the _first wiring layer 14 ₁ , and similarly, reference numeral 22 ₂ includes the second wiring layer 14 ₂ . The pattern 22 ₄ is the fourth wiring layer 14 _4.
Each of the patterns including is shown. The first barrier layer is composed of the silicon oxide film 16 ₁ and the polysilicon film 18 ₁ , ..., The fourth barrier layer is the silicon oxide film 16 1.
₄ and a polysilicon film 18 ₄ . Reference code 2
8 ₁ is the first wiring layer 14 ₁ and the second wiring layer 14
₂ shows an interlayer insulating film (BPSG or the like) that insulates them from each other. Similarly, reference numeral 28 ₂ is a second wiring layer 1
4 ₂ and the third wiring layer 14 ₃ are insulated from each other by an interlayer insulating film, ..., Reference numeral 28 ₄ is a third wiring layer 14 _4.
And an inter-layer insulating film for insulating the _fourth wiring layer 14 ₄ from each other. Reference numerals 54A to 54D indicate
_On the side walls of the interlayer insulating films 28 _{1 to} 28 _{4 and} the wiring layer 14
The sidewall insulating film (Si ₃ N ₄ , SiO ₂ or the like) formed above the sidewalls _{1 to} 14 ₄ is shown.

In the semiconductor device shown in FIG. 26, the contact hole 51 becomes deep. Therefore, the thickness of the barrier layer is
It is desirable that the second layer is thicker than the layer, the third layer is thicker than the second layer, the fourth layer is thicker than the third layer, and so on. According to this, for example, even if the fourth barrier layer is exposed to the etchant for a long time, the barrier layer can be left. This can be achieved by setting the film thickness relationships of the polysilicon films 18 ₁ to 18 ₄ as follows, for example.

T18 ₁ <T18 ₂ <T18 ₃ <T18 ₄ (1) In the formula (1), T18 ₁ is the film thickness of the polysilicon film 18 ₁ , T18 ₂ is the film thickness of the polysilicon film 18 ₂ . T
18 ₃ the thickness of the polysilicon film 18 _3, T18 ₄ shows the polysilicon film 18 ₄ of thickness, respectively. Next, a manufacturing method according to the fourth embodiment of the present invention will be described. FIG. 27 is a pattern plan view of a dynamic RAM cell formed by using the manufacturing method according to the fourth embodiment of the present invention.

As shown in FIG. 27, the source area 114 ₁
The drain region 114 ₂ is formed in the element forming region 101 where the surface of the silicon substrate is exposed. A word line (gate electrode) WL is formed on the element forming region 101 between the source region 114 ₁ and the drain region 114 ₂ . The bit line BL is electrically connected to the drain region 114 ₂ . Seo - The source region 114 ₁ stress - Gino - cathode electrode are electrically connected. Note that FIG.
Inside, the storage node electrode and the cell plate electrode are omitted.

28 to 42 are sectional views of the cells of the dynamic RAM, which are shown in the order of steps according to the manufacturing method according to the fourth embodiment of the present invention. Note that this cross section is taken along the line II in FIG.

First, a silicon oxide film (Si) is formed on the surface region of the P-type silicon substrate 100 by, for example, the LOCOS method.
O ₂ ; hereinafter referred to as a field oxide film) 102 is formed,
The element formation region 101 is defined. Then, a silicon oxide film (SiO ₂ ; hereinafter referred to as a gate oxide film) 104 having a thickness of about 150 Å is formed on the element forming region 101 by, for example, a thermal oxidation method. Then, the entire surface above the substrate 100 is subjected to about 2 by, for example, LPCVD.
A polysilicon film 106 having a thickness of 000 angstrom is formed. Then, on the polysilicon film 106,
Phosphorus is diffused by a vapor phase diffusion method using POCl ₃ as a source to make the polysilicon film 106 a conductor (made N-type). Then, a silicon oxide film (SiO ₂ ) 108 having a thickness of about 3000 angstrom is formed on the polysilicon film 106 by the LPCVD method. Then
About 1 is deposited on the silicon oxide film 108 by the LPCVD method.
Polysilicon film 1 having a thickness of 00 angstrom
10 is formed (FIG. 28).

Next, a resist pattern (not shown) corresponding to the word line (gate) pattern is formed on the polysilicon film 110 by photolithography.
Then, using the resist pattern as a mask, the polysilicon film 110, the silicon oxide film 108, and the N-type polysilicon film 106 are sequentially etched by the RIE method. As a result, the word line made of the N-type polysilicon film 106, the silicon oxide film 108 and the polysilicon film 110 are formed.
A wire line pattern 112 including a barrier layer formed of is formed. Then, using the word line pattern 112 and the field oxide film 102 as a mask, N-type impurity ions,
For example, arsenic (As) ions are implanted into the substrate 100.
As a result, the N-type impurity layer 114 _{1 serving} as the source of the transistor and the N-type impurity layer 114 _{2 serving as the} drain are formed.
Is formed. After that, the resist pattern not shown is removed (FIG. 29).

Then, about 100 is formed by LPCVD on the substrate 100 so as to cover the word line pattern 112.
A silicon oxide film (S having a thickness of 0 angstrom)
io ₂ ) 116, a BPSG film 118 having a thickness of about 4000 Å is formed. Silicon oxide film 1
16 and the BPSG film 118 function as an interlayer insulating film. Then, the BPSG film 118 is reflowed and planarized in a nitrogen atmosphere at a temperature of 850 ° C. (FIG. 30).

Next, a resist pattern (not shown) is formed on the BPSG film 118 by photolithography. This resist pattern is in a range including the planned contact portion of the storage node electrode that is to be contacted with the impurity layer 114 ₁ to be the source, and the word line pattern.
The windows have a width wider than the distance between the windows 112. Then, using the resist pattern as a mask, the BPSG film 1
18, silicon oxide film 116, and gate oxide film 104,
For example, R using CHF ₃ / CO ion as an etchant
Etching is performed by the IE method. Thereby, the impurity layer 1
An opening 119 reaching 14 ₁ is obtained. Further, the etching is stopped at the portion of the polysilicon film 110 on the word line pattern 112. This is because the etching rate of polysilicon is as low as 1/60 or less as compared with the etching rate of BPSG. After that, the resist pattern not shown is removed (FIG. 31).

Next, hydrogen combustion oxidation is performed at a temperature of 850 ° C. to oxidize the surfaces of the polysilicon films 106 and 110 exposed in the opening 119, respectively, and the silicon oxide film 1
06A and 110A are obtained. At this time, the surface of the substrate 100 exposed in the opening 119 is also oxidized to form a silicon oxide film 122 having a thickness of about 200 Å (FIG. 32).

Then, a silicon nitride film (SiN _x ) film having a thickness of about 1000 Å is formed on the BPSG film 118 including the inside of the opening 119 by the LPCVD method. Then, the silicon nitride film is etched by the RIE method to form the contact hole 120. At this time, the silicon nitride film remains mainly on the sidewalls of the BPSG film 118 and on the sidewalls of the word line 106. As a result, the sidewall insulation film 124 is obtained (see FIG. 3).
3).

Then, the BP including the inside of the contact hole 120 is included.
A polysilicon film having a thickness of about 1000 Å is formed on the SG film 118 by the LPCVD method. Then, phosphorus is diffused into the polysilicon film by a vapor phase diffusion method using POCl ₃ as a source to convert the polysilicon film into a conductor (made N-type). Then, the polysilicon film is patterned by photolithography to obtain a storage node electrode 126 (FIG. 34). Then, the surface of the storage node electrode 126 is oxidized by, for example, a thermal oxidation method to form a capacitor dielectric film 128 (FIG. 35).

Then, a low resistance polysilicon film having a thickness of about 2000 angstrom is formed on the BPSG film 118 by LPCVD so as to cover the storage node electrode 126. This polysilicon film becomes the plate electrode 130. Then, the plate electrode 130
On top, about 1000 angstroms by LPCVD method.
A silicon oxide film (SiO ₂ ) 132 having a film thickness is formed. Then, the LPC is formed on the silicon oxide film 132.
A polysilicon film 134 having a thickness of about 400 Å is formed by the VD method (FIG. 36).

Next, on the polysilicon film 134, a resist pattern (not shown) corresponding to the opening for allowing the bit line to reach the substrate is formed on the plate electrode by photolithography. Next, the resist pattern
Using the silicon as a mask, the polysilicon film 134, the silicon oxide film 132, the plate electrode (polysilicon film) 130.
Are sequentially etched by the RIE method. This allows
Opening 136 for reaching the bit line to the substrate 100
A plate electrode pattern 138 having The width of the slit 136 is formed to be larger than the distance between the word line patterns 112. The plate electrode pattern 138 includes a plate electrode 130 and a barrier layer composed of a silicon oxide film 132 and a polysilicon film 134. After that, the resist pattern not shown is removed (FIG. 37).

Then, an interlayer insulating film is formed on the BPSG film 118 so as to cover the plate electrode pattern 138.
By the LPCVD method, a silicon oxide film (SiO ₂ ) 140 having a thickness of about 1000 Å, about 40
BPSG film 142 having a thickness of 00 angstrom
To form. Then, the BPSG film 142 is heated to a temperature of 850.
Reflow in a nitrogen atmosphere at ℃ for flattening (Fig. 3
8).

Next, a resist pattern (not shown) is formed on the BPSG film 142 by photolithography. This resist pattern has a window having a width wider than the width of the opening 136 within a range including a portion to be contacted with the bit line contacting the impurity layer 114 _{2 serving} as a drain. Then, using the resist pattern as a mask, the BPSG film 142, the silicon oxide film 140, the BP
SG film 118, silicon oxide film 116, gate oxide film 1
04 is etched by, for example, the RIE method using CHF ₃ / CO ions as an etchant. As a result, the opening 144 reaching the impurity layer 114 ₂ is obtained. Also,
The etching stops at the portion of the polysilicon film 132 on the plate electrode pattern 138 and at the portion of the polysilicon film 110 on the word line pattern 112. This is because the etching rate of polysilicon is as low as 1/60 or less as compared with the etching rate of BPSG. After that, the resist pattern not shown is removed (FIG. 39).

Next, hydrogen combustion oxidation is performed at a temperature of 850 ° C. to expose the polysilicon film 106 exposed in the opening 144.
The surfaces of (wire line), 110, 130 (plate electrode) and 134 are respectively oxidized to form oxides 106A and 11A.
0B, 130A, and 134A are formed, respectively. At this time, the surface of the substrate 100 exposed in the opening 144 is also oxidized to form a silicon oxide film 146 having a thickness of about 150 Å (FIG. 40).

Next, on the BPSG film 142 including the inside of the opening 144, a silicon nitride film (SiN _x ) film having a thickness of about 1000 Å is formed by the LPCVD method. Then, the silicon nitride film is etched by the RIE method to form a contact hole 145. At this time, the silicon nitride film is mainly used as the BPSG film 118, 142.
On the side surface of the wire, the wire wire 106, and the plate electrode 130.
Remains above the sides of. As a result, the sidewall insulating film 148 is obtained (FIG. 41).

Next, including the inside of the contact hole 145, B
About 3000 on the PSG film 142 by the LPCVD method.
A polysilicon film containing phosphorus having a thickness of angstrom is formed. Then, the polysilicon film is patterned by using the photolithography method. By this patterning, the N-type impurity layer 1 is formed through the contact hole 145.
Obtain the bit line 150 electrically connected to 14 ₂ . Through the steps described above, a dynamic RAM cell having a plane pattern shown in FIG. 27 is formed. next,
A manufacturing method according to the fifth embodiment of the present invention will be described. FIG. 43 is a pattern plan view of a dynamic RAM cell formed by using the manufacturing method according to the fifth embodiment of the present invention.

[0068] As shown in FIG. 43, stress - Gino - cathode electrode and the source - a contact portion SNC of the scan area 114 _1, the bit line BL and word - is provided in a region surrounded by the word line WL. Then, the element formation region 101 has a bit line B
It is formed obliquely as seen from a plane so as to connect the source regions 114 ₁ on the diagonal with L in between. Bit line B
L is electrically connected to the drain region 114 ₂ . In FIG. 43, the storage node electrode and the cell plate electrode are omitted.

FIGS. 44 (a) to 44 (c) to FIG. 54 (a)
8C are sectional views of a dynamic RAM cell shown in the order of steps according to the manufacturing method according to the fourth embodiment of the present invention. Note that the cross section shown in (a) is taken along line aa in FIG. 43, the cross section shown in (b) is taken along line bb in FIG. 43, and the cross section shown in (c) is taken in c in FIG. -It shall be along each line c.

First, the field oxide film 102 is formed in the surface region of the P-type silicon substrate 100 by a method similar to that described with reference to FIGS. 27 to 29 to define the element formation region 101. Then, a gate oxide film 104 is formed on the element forming region 101, and then a word line made of an N-type polysilicon film 106 and a barrier made of a silicon oxide film 108 and a polysilicon film 110 are formed above the substrate 100. A word line pattern 112 including layers is formed. Then
An N-type impurity layer 114 ₁ that serves as a source of the transistor and an N-type impurity layer 114 ₂ that serves as a drain are formed {FIGS. 44 (a) to (c)}.

Then, by a method similar to that described with reference to FIG. 30, a silicon oxide film 116, a BPSG film as an interlayer insulating film are formed above the substrate 100 so as to cover the word line pattern 112. 118 is formed. Then B
The PSG film 118 is reflowed and flattened (FIG. 45).
(A)-(c)}.

Next, a resist pattern (not shown) is formed on the BPSG film 118 by photolithography. The resist pattern - down is a range including a contact portion to be of bit lines contact the impurity layer 114 ₂ serving as a drain, Katsuwa - having emission 112 windows of expansion have width than the distance between the cross - word line pattern. Then, using the resist pattern as a mask, the BPSG film 118, the silicon oxide film 116, and the gate oxide film 104 are formed, for example, CHF ₃
Etching is performed by the RIE method using / CO ions as an etchant. As a result, the opening 144 reaching the impurity layer 114 ₂ is obtained. In addition, the above etching is a work
It stops at the portion of the polysilicon film 110 on the contact line pattern 112. This is because the etching rate of polysilicon is as low as 1/60 or less as compared with the etching rate of BPSG. After that, the resist pattern not shown is removed {FIGS. 46 (a) to 46 (c)}.

Then, hydrogen combustion oxidation is performed at a temperature of 850 ° C. to oxidize the surfaces of the polysilicon films 106 and 110 exposed in the openings 144, respectively, to obtain oxides 106A and 110A. At this time, the surface of the substrate 100 exposed in the opening 144 is also oxidized to form a silicon oxide film 146 having a thickness of about 200 Å (FIGS. 47A to 47C).

Then, a silicon nitride film (SiN _x ) having a thickness of about 1000 Å is formed on the BPSG film 118 including the inside of the opening 144 by the LPCVD method. Then, the silicon nitride film is etched by the RIE method to form a contact hole 145. At this time,
The silicon nitride film remains mainly on the side wall of the BPSG film 118 and above the side wall of the word line 106. As a result, the sidewall 148 is obtained {FIG. 48 (a)-
(C)}.

Then, the BP including the inside of the contact hole 145 is included.
A polysilicon film 152 having a thickness of about 3000 angstrom is formed on the SG film 118 by the LPCVD method. This polysilicon film will become a bit line in the future. Then, on the polysilicon film 152, POCl ₃
Is used as a source to diffuse phosphorus to make the polysilicon film 152 a conductor (made N-type). Then
About 1 is formed on the polysilicon film 152 by the LPCVD method.
A silicon oxide film (SiO ₂ ) 154 having a thickness of 000 Å is formed. Then, a polysilicon film 156 having a thickness of about 250 Å is formed on the silicon oxide film 154 by the LPCVD method. Next, a resist pattern (not shown) corresponding to the bit line is formed on the polysilicon film 156 by photolithography. Then, the polysilicon film 156, the silicon oxide film 154, and the N-type polysilicon film 152 are sequentially etched by the RIE method using the resist pattern as a mask. As a result, a bit line pattern 158 including the bit line formed of the N-type polysilicon film 152 and the barrier layer formed of the silicon oxide film 152 and the polysilicon film 154 is formed (FIGS. 49A to 49C). }.

Next, LPC is formed as an interlayer insulating film on the BPSG film 118 so as to cover the bit line pattern 158.
A silicon oxide film 140 having a thickness of about 1000 angstroms and a thickness of about 6000 angstroms are formed by the VD method.
A BPSG film 142 having a thickness of 100 μm is formed. Next, the BPSG film 142 is reflowed in a nitrogen atmosphere at a temperature of 850 ° C. to be flattened {FIG. 50 (a)-
(C)}.

Next, a resist pattern (not shown) is formed on the BPSG film 142 by photolithography. This resist pattern is in a range including the planned contact portion of the storage node electrode that is to be contacted with the impurity layer 114 ₁ to be the source, and the word line pattern.
The windows have a width wider than the distance between the windows 112. Then, using the resist pattern as a mask, the BPSG film 14
2, the silicon oxide film 140, the BPSG film 118, the silicon oxide film 116, and the gate oxide film 104 are, for example, CHF.
Etching is sequentially performed by the RIE method using ₃ / CO ions as an etchant. As a result, the opening 119 reaching the impurity layer 114 ₁ is obtained. In addition, the etching is performed on the polysilicon film 15 on the bit line pattern 158.
6, the polysilicon film 1 is formed on the word line pattern 112.
Stop at each of 10 parts. This is because the etching rate of polysilicon is as low as 1/60 or less as compared with the etching rate of BPSG. After that, the resist pattern not shown is removed {FIGS. 51 (a) to 51 (c)}.
Incidentally, FIG. 55 is a pattern plan view in the steps of FIGS. 49 (a) to 49 (c).

Next, hydrogen combustion oxidation is performed at a temperature of 850 ° C. to expose the polysilicon film 106 exposed in the opening 121.
Oxidize the surfaces of 110, 152 and 156 respectively,
Change to oxides 106A, 110A, 152A and 156A. At this time, the substrate 100 exposed in the opening 119.
Is also oxidized to form a silicon oxide film 122 having a thickness of about 200 Å (FIG. 52).
(A)-(c)}.

Then, a silicon nitride film (SiN _x ) film having a thickness of about 1000 angstrom is formed on the BPSG film 142 including the inside of the opening 119 by the LPCVD method. Then, the silicon nitride film is etched by the RIE method to form the contact hole 120. At this time, the silicon nitride film is mainly used as the BPSG film 142, 118.
Of the bit line 152 and the word line 106. As a result, the side wall 124 is obtained {FIGS. 53 (a) to (c)}.

Then, the BP including the inside of the contact hole 120 is included.
A polysilicon film having a thickness of about 1000 Å is formed on the SG film 142 by the LPCVD method. Then, phosphorus is diffused into the polysilicon film by a vapor phase diffusion method using POCl ₃ as a source to convert the polysilicon film into a conductor (made N-type). Then, the polysilicon film is patterned by photolithography to obtain a storage node electrode 126. Then storage
The surface of the node electrode 126 is oxidized by, for example, a thermal oxidation method to form a capacitor dielectric film 128. Then, a polysilicon film having a thickness of about 3000 angstroms is formed on the BPSG film 142 including the capacitor dielectric film 128 by the LPCVD method, and a plate electrode 139 is obtained from this polysilicon film. Through the above steps, a dynamic RAM cell having a plane pattern shown in FIG. 43 is formed.

The present invention is not limited to the above-mentioned embodiment, and the manufacturing method according to the present invention is applied to other than the bit line contact portion of the memory cell and the storage node contact portion of the memory cell. Needless to say, can be applied.

Although the silicon oxide film and the polysilicon are used as the barrier layer, the polysilicon is replaced by hafnium (Hf), tantalum (Ta), zirconium (Zr),
Tungsten - silicide (WSi _2), molybdenum -
Silicide (MoSi ₂ ), hafnium-silicide (HfSi ₂ ), tantalum-silicide (TaS
i ₂ ), zirconium-silicide (ZrSi ₂ ) or the like. Similar to polysilicon, all of these substances become oxides and become insulators by being subjected to heat treatment at a temperature of 700 ° C. or higher in an oxidizing atmosphere, for example.

Further, the barrier layer is formed by stacking the silicon oxide film and the polysilicon. According to this, CHF is formed.
It is possible to exert etching resistance such that either polysilicon is used for the ₃ / CO etchant, and the silicon oxide film is used for the Cl ₂ etchant. Therefore, the effect that the etching resistance of the barrier layer can be strengthened as a whole is obtained.

Although BPSG is used as the interlayer insulating film, the interlayer insulating film is formed of phosphorus-silicate glass (PS
G) or boron-silicate glass (BSG). Similar to BPSG, all of these substances can be reflowed by heat treatment at a temperature of 700 ° C. or higher in an oxidizing atmosphere, and Si, Hf, T
a, Zr, WSi ₂ , MoSi ₂ , HfSi ₂ , TaS
It is possible to obtain selectivity for etching with i ₂ and ZrSi ₂ . Although the silicon nitride film is used as the side wall insulating film, the side wall insulating film is not limited to the silicon nitride film as long as it is an insulating material.

[0085]

As described above, according to the present invention, there is provided a method of manufacturing a semiconductor device, which is effective for a semiconductor device having multiple wiring layers and which can form contact holes in a self-aligned manner with respect to the wiring layers. it can.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a third step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a sixth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view showing a seventh step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing an eighth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing a ninth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a tenth step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 11 is a sectional view showing an eleventh step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a sectional view showing a twelfth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing a thirteenth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a sectional view showing a fourteenth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a sectional view showing a second step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a sectional view showing a third step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 20 is a sectional view showing a sixth step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a sectional view showing a seventh step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 22 is a sectional view showing an eighth step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 23 is a sectional view showing a ninth step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 24 is a sectional view showing a tenth step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 25 is a sectional view showing an eleventh step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 26 is a sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 27 is a pattern plan view of a cell of a dynamic RAM manufactured by the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 28 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 29 is a sectional view showing a second step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 30 is a sectional view showing a third step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 31 is a sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the fourth example of the present invention.

FIG. 32 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 33 is a sectional view showing a sixth step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 34 is a sectional view showing a seventh step of the method for manufacturing a semiconductor device according to the fourth example of the present invention.

FIG. 35 is a sectional view showing an eighth step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 36 is a sectional view showing a ninth step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 37 is a sectional view showing a tenth step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 38 is a sectional view showing an eleventh step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 39 is a sectional view showing a twelfth step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 40 is a sectional view showing a thirteenth step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 41 is a sectional view showing a fourteenth step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 42 is a sectional view showing a fifteenth step of the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 43 is a pattern plan view of a cell of a dynamic RAM manufactured by the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 44 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 45 is a sectional view showing a second step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 46 is a sectional view showing a third step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 47 is a sectional view showing a fourth step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

48 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention, FIG.
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 49 is a sectional view showing a sixth step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 50 is a sectional view showing a seventh step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 51 is a sectional view showing an eighth step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

52 is a sectional view showing a ninth step of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention, FIG.
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

53 is a sectional view showing a tenth step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention, FIG.
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

FIG. 54 is a sectional view showing an eleventh step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention,
43A is a cross section taken along line aa in FIG. 43, and FIG.
3 is a cross section taken along line bb in FIG. 3, (c) is cc in FIG.
It is a cross section along a line.

55 is a plan view of the semiconductor device in the process shown in FIG. 51. FIG.

[Explanation of symbols]

10 ... P-type silicon substrate, 12 ... Gate oxide film, 14 ...
Conductive polysilicon film, 16 ... Silicon oxide film, 18 ... Polysilicon film, 18A ... Oxide, 22 ... First wiring pattern, 26 ... Silicon oxide film, 28 ...
BPSG film, 30 ... Conductive polysilicon film, 3
2 ... Tungsten silicide film, 34 ... Silicon oxide film, 36 ... Polysilicon film, 40, 41 ... Second wiring pattern, 42 ... Silicon oxide film, 44 ... BPSG
Film, 50 ... Opening portion, 51 ... Contact hole, 54 ... Silicon nitride film, 54A to 54D ... Sidewall insulating film, 5
6 ... Conductive polysilicon film, 100 ... P-type silicon substrate, 101 ... Element forming region, 102 ... Field oxide film, 104 ... Gate oxide film, 106 ... Conductive polysilicon film, 108 … Silicon oxide film, 110…
Polysilicon film, 112 ... Word line pattern, 114 ₁
Source region, 114 ₂ Drain region, 116 Silicon oxide film, 118 BPSG film, 119 Opening, 1
20 ... Contact hole, 124 ... Sidewall insulating film,
126 ... Storage node electrode, 128 ... Capacitor dielectric film, 130 ... Plate electrode, 132 ... Silicon oxide film, 134 ... Polysilicon film, 136 ... Opening part, 13
8 ... Plate electrode pattern, 139 ... Plate electrode, 1
40 ... Silicon oxide film, 142 ... BPSG film, 144 ...
Openings, 145 ... Contact holes, 148 ... Side-hole insulating film, 150 ... Conductive polysilicon film (bit line), 152 ... Polysilicon film. 154 ... Silicon oxide film, 156 ... Polysilicon film, 158 ... Bit line pattern.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 27/108

Claims (12)

[Claims] 1. A step of forming a first insulating film on a surface of a semiconductor substrate, a step of forming a first conductive film on the first insulating film, and a step of forming the first conductive film on the first conductive film. A step of forming a first barrier layer, a step of collectively patterning the first barrier layer and the first conductive film to form a first wiring layer pattern, Forming a second insulating film over the surface of the substrate so as to cover the first wiring layer pattern; forming a second conductive film on the second insulating film; A step of forming a second barrier layer on the second conductive film, and a step of collectively patterning the second barrier layer and the second conductive film to form a second wiring layer pattern. And a step of forming a third insulating film above the surface of the substrate so as to cover the second wiring layer pattern, Forming an opening reaching the body substrate through the first, second and third insulating films by using at least one of the first and second barrier layers as an etching barrier; A step of forming a sidewall made of a fourth insulating film on the sidewall of the opening, and a step of forming a third wiring layer pattern contacting the substrate through the opening. A method for manufacturing a semiconductor device, comprising: 2. The first and second barrier layers are respectively formed of a first material film made of a first material and a second material film different from the first material film.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the second material film made of the above material is stacked and formed. 3. A material having an insulating property is selected as the first material, and a material having an insulating property by being activated at least is selected as the second material, and after the opening is formed. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of activating the second substance. 4. The first substance is selected from compounds in which at least silicon and oxygen are combined, and the second substance is silicon, hafnium, tantalum,
4. The semiconductor device according to claim 3, wherein the activation is selected from any one of zirconium, tungsten-silicide, molybdenum-silicide, hafnium-silicide, tantalum-silicide, and zirconium-silicide. Manufacturing method. 5. A step of defining an element formation region of a first conductivity type on a surface of a semiconductor substrate, a step of forming a first insulation film on the surface of the element formation area, and the first insulation film. Forming a first conductive film thereon; forming a barrier layer on the first conductive film; and patterning the first barrier layer and the first conductive film together. And forming a word line pattern by using the word line pattern as a mask to form a second conductivity type source / drain region in the element forming region. A step of forming a second insulating film on the surface of the substrate so as to cover the word line pattern, and a first opening portion reaching one of the source / drain regions. Using the first barrier layer as an etching barrier and penetrating the first and second insulating films. , On the sidewalls of the first opening, the first consisting of the third insulating film
Forming a sidewall of the source / drain region, forming a storage node electrode reaching one of the source / drain regions through the first opening, and the storage node electrode Forming a fourth insulating film on the surface of the second insulating film, and forming a fourth insulating film on the second insulating film so as to cover the fourth insulating film.
A step of forming a second conductive film; a step of forming a second barrier layer on the second conductive film; and a step of collectively patterning the second barrier layer and the second conductive film. Forming a cell plate electrode pattern having a second opening above the other of the source / drain regions; and the second insulating film so as to cover the cell plate electrode. Forming a fifth insulating film thereon, and using a third opening reaching the other of the source / drain regions as at least one of the first and second barrier layers as an etching barrier. A step of forming the first, second and fifth insulating films by penetrating them, and forming a second insulating film of a sixth insulating film on the side wall of the third opening.
And the step of forming a bit line pattern that is in contact with the other of the source / drain regions through the third opening. Manufacturing method of semiconductor device. 6. A first material film made of a first material and a second material different from the first material in the first and second barrier layers, respectively.
6. The semiconductor device according to claim 5, wherein the second substance film made of the substance is stacked to be formed. 7. A material having an insulating property is selected as the first material, and a material having an insulating property by being activated at least is selected as the second material, and after the opening is formed. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of activating the second substance. 8. The first substance is selected from compounds in which at least silicon and oxygen are combined, and the second substance is silicon, hafnium, tantalum,
8. The semiconductor device according to claim 7, wherein the activation is an oxidation selected from any one of zirconium, tungsten-silicide, molybdenum-silicide, hafnium-silicide, tantalum-silicide, and zirconium-silicide. Manufacturing method. 9. A step of defining an element formation region of a first conductivity type on a surface of a semiconductor substrate, a step of forming a first insulation film on the surface of the element formation area, and the first insulation film. Forming a first conductive film thereon; forming a barrier layer on the first conductive film; and patterning the first barrier layer and the first conductive film together. And forming a word line pattern, and using the word line pattern as a mask to form a second conductivity type source / drain region in the element forming region. A step of forming a second insulating film on the surface of the substrate so as to cover the word line pattern, and a first opening portion reaching one of the source / drain regions. Formed by penetrating the first and second insulating films by using the first barrier layer as a barrier for etching. That the step, on the sidewalls of the first opening, the first made in the third insulating film 1
Forming a side wall of the second conductive film, forming a second conductive film in contact with the other of the source / drain regions through the first opening, and forming a second conductive film on the second conductive film. And forming a second barrier layer, and patterning the second barrier layer and the second conductive film together to form a bit line contacting one of the source / drain regions. Forming a pattern, forming a fourth insulating film so as to cover the bit line pattern, and forming a second opening reaching the other of the source / drain regions, A step of penetrating and forming the first, second, and third insulating films by using at least one of the first and second barrier layers as an etching barrier; and on a sidewall of the second opening. A second insulating film made of a fifth insulating film
Forming a sidewall of the source electrode, and forming a storage node electrode reaching one of the source / drain regions through the second opening, the storage node electrode A step of forming a sixth insulating film on the surface of, and on the fourth insulating film so as to cover the sixth insulating film,
And a step of forming a cell plate electrode pattern. 10. The first and second barrier layers are respectively formed into a first
10. The semiconductor device according to claim 9, wherein a first substance film made of the substance of No. 1 and a second substance film made of a second substance different from the first substance are stacked and formed. . 11. A material having an insulating property is selected as the first material, and a material having an insulating property by being activated at least is selected as the second material, and after the opening is formed. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of activating the second substance. 12. The first substance is selected from compounds in which at least silicon and oxygen are combined, and the second substance is silicon, hafnium, tantalum,
12. The semiconductor device according to claim 11, wherein the activation is oxidation, which is selected from any of zirconium, tungsten-silicide, molybdenum-silicide, hafnium-silicide, tantalum-silicide, and zirconium-silicide. Manufacturing method.