JPH06291113A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH06291113A JPH06291113A JP10030293A JP10030293A JPH06291113A JP H06291113 A JPH06291113 A JP H06291113A JP 10030293 A JP10030293 A JP 10030293A JP 10030293 A JP10030293 A JP 10030293A JP H06291113 A JPH06291113 A JP H06291113A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pattern
- semiconductor device
- si3n4
- oxidation resistant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、選択酸化法によって素
子分離領域を形成する半導体装置の製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an element isolation region is formed by a selective oxidation method.
【０００２】[0002]
【従来の技術】図２は、選択酸化法によって素子分離領
域を形成する半導体装置の製造方法の従来例を示してい
る。この従来例では、図２（ａ）に示すように、Ｓｉ基
板１１を準備し、図２（ｂ）に示すように、このＳｉ基
板１１の表面の全面にパッド用のＳｉＯ2 膜１２を形成
する。2. Description of the Related Art FIG. 2 shows a conventional example of a method of manufacturing a semiconductor device in which an element isolation region is formed by a selective oxidation method. In this conventional example, a Si substrate 11 is prepared as shown in FIG. 2A, and a SiO 2 film 12 for pad is formed on the entire surface of the Si substrate 11 as shown in FIG. 2B. To do.
【０００３】次に、ＳｉＯ2 膜１２上の全面にＳｉ3 Ｎ
4 膜１３を形成し、このＳｉ3 Ｎ4膜１３上にレジスト
（図示せず）を塗布する。そして、リソグラフィ技術を
用いてレジストを素子活性領域のパターンに加工し、こ
のレジストをマスクにしてＳｉ3 Ｎ4 膜１３のみをドラ
イエッチングする。その後、レジストをアッシングで除
去して、図２（ｃ）に示す状態を得る。Next, Si 3 N is formed on the entire surface of the SiO 2 film 12.
A 4 film 13 is formed, and a resist (not shown) is applied on the Si 3 N 4 film 13. Then, the resist is processed into a pattern of the element active region by using a lithographic technique, and only the Si 3 N 4 film 13 is dry-etched using the resist as a mask. Then, the resist is removed by ashing to obtain the state shown in FIG.
【０００４】次に、Ｓｉ基板１１の表面を酸化するが、
Ｓｉ3 Ｎ4 膜１３は酸素を透過させにくいので、Ｓｉ3
Ｎ4 膜１３が耐酸化膜になる。従って、図２（ｄ）に示
すように、Ｓｉ基板１１の表面のうちでＳｉ3 Ｎ4 膜１
３が形成されていない部分が選択的に酸化されて、この
部分にＳｉＯ2 膜１４が形成される。Next, the surface of the Si substrate 11 is oxidized,
Si 3 since N 4 film 13 is easily transmitting oxygen, Si 3
The N 4 film 13 becomes an oxidation resistant film. Therefore, as shown in FIG. 2D, the Si 3 N 4 film 1 is formed on the surface of the Si substrate 11.
The part where 3 is not formed is selectively oxidized, and the SiO 2 film 14 is formed in this part.
【０００５】その後、図２（ｅ）に示すように、Ｓｉ3
Ｎ4 膜１３を除去して、ＳｉＯ2 膜１４で素子分離領域
を形成する。なお、以上のような選択酸化法はＬＯＣＯ
Ｓ法とも呼ばれている。Then, as shown in FIG. 2 (e), Si 3
The N 4 film 13 is removed to form an element isolation region with the SiO 2 film 14. The selective oxidation method as described above is performed by using LOCO.
It is also called the S method.
【０００６】[0006]
【発明が解決しようとする課題】ところが、選択酸化法
による酸化は等方的に進行するので、図２（ｄ）及び
（ｅ）に示したように、Ｓｉ3 Ｎ4 膜１３の端縁からＳ
ｉ3 Ｎ4 膜１３下へＳｉＯ2 膜１４が入り込んで、バー
ズビーク１４ａと呼ばれる部分が形成される。However, since the oxidation by the selective oxidation method proceeds isotropically, as shown in FIGS. 2 (d) and 2 (e), from the edge of the Si 3 N 4 film 13 S
The SiO 2 film 14 enters under the i 3 N 4 film 13 to form a portion called a bird's beak 14a.
【０００７】この結果、半導体装置を微細化するために
素子分離領域のパターンをリソグラフィの限界程度の寸
法に設計しても、設計値通りのパターンの酸化膜を形成
することができなかった。つまり、素子分離領域が設計
値よりも大きくなり、素子活性領域が設計値よりも小さ
くなっていた。As a result, even if the pattern of the element isolation region is designed to have a dimension close to the limit of lithography in order to miniaturize the semiconductor device, the oxide film having the pattern as designed cannot be formed. That is, the element isolation region is larger than the designed value, and the element active region is smaller than the designed value.
【０００８】このため、従来の半導体装置の製造方法で
は、半導体装置の特性が悪化するか、またはこれを回避
するために微細化の程度を下げざるを得ないという問題
があった。Therefore, the conventional method of manufacturing a semiconductor device has a problem that the characteristics of the semiconductor device are deteriorated or that the degree of miniaturization must be reduced in order to avoid this.
【０００９】そこで、本発明の目的は、リソグラフィの
限界程度の寸法の素子分離領域でも設計値通りのパター
ンに酸化膜を形成することができて、微細で且つ特性の
優れた半導体装置を製造することができる方法を提供す
ることである。Therefore, an object of the present invention is to manufacture a fine and excellent semiconductor device in which an oxide film can be formed in a pattern according to a design value even in an element isolation region having a dimension about the limit of lithography. Is to provide a method that can.
【００１０】[0010]
【課題を解決するための手段】上述した課題を解決する
ために、本発明の半導体装置の製造方法は、半導体基板
上に素子活性領域のパターンの第１の耐酸化膜を形成す
る工程と、前記第１の耐酸化膜の側面に第２の耐酸化膜
から成る側壁を形成する工程と、前記第１及び第２の耐
酸化膜をマスクにして前記半導体基板を酸化して、素子
分離領域の表面に酸化膜を形成する工程とを有してい
る。In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first oxidation resistant film having a pattern of element active regions on a semiconductor substrate, A step of forming a side wall made of a second oxidation resistant film on a side surface of the first oxidation resistant film, and oxidizing the semiconductor substrate using the first and second oxidation resistant films as a mask to form an element isolation region. And forming an oxide film on the surface of the.
【００１１】[0011]
【作用】本発明による半導体装置の製造方法では、素子
活性領域のパターンの第１の耐酸化膜の側面に第２の耐
酸化膜から成る側壁を形成しているので、第１及び第２
の耐酸化膜の全体では素子活性領域のパターンよりも大
きい。従って、第１及び第２の耐酸化膜をマスクにして
半導体基板を酸化して酸化膜を形成することによって、
この酸化膜にバーズビークが形成されても、設計値通り
の素子分離領域のパターンに酸化膜を形成することが可
能である。In the method of manufacturing a semiconductor device according to the present invention, since the side wall of the second oxidation resistant film is formed on the side surface of the first oxidation resistant film of the pattern of the element active region, the first and second oxidation resistant films are formed.
The entire oxidation resistant film is larger than the pattern of the element active region. Therefore, by oxidizing the semiconductor substrate using the first and second oxidation resistant films as a mask to form an oxide film,
Even if a bird's beak is formed in this oxide film, it is possible to form the oxide film in the pattern of the element isolation region as designed.
【００１２】しかも、第２の耐酸化膜から成る側壁は、
第１の耐酸化膜を形成した後、例えば、第２の耐酸化膜
を全面に堆積させ、この第２の耐酸化膜の全面を異方性
エッチングすることによって、第１の耐酸化膜に対して
自己整合的に形成することができる。従って、素子分離
領域のパターンがリソグラフィの限界程度の寸法であっ
ても、第２の耐酸化膜から成る側壁を形成することがで
きる。Moreover, the side wall made of the second oxidation resistant film is
After forming the first oxidation-resistant film, for example, a second oxidation-resistant film is deposited on the entire surface, and the entire surface of the second oxidation-resistant film is anisotropically etched to form the first oxidation-resistant film. In contrast, it can be formed in a self-aligned manner. Therefore, even if the pattern of the element isolation region is about the size of the limit of lithography, the side wall made of the second oxidation resistant film can be formed.
【００１３】[0013]
【実施例】以下、本発明の一実施例を、図１を参照しな
がら説明する。なお、図１の実施例において、図２に示
した従来例と対応する構成部分には、同一の符号を付し
た。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In addition, in the embodiment of FIG. 1, the same reference numerals are given to the components corresponding to those of the conventional example shown in FIG.
【００１４】本実施例では、図１（ａ）に示すように、
Ｓｉ基板１１を準備し、このＳｉ基板１１を熱酸化し
て、図１（ｂ）に示すように、Ｓｉ基板１１の表面の全
面に膜厚が５０ｎｍ程度であるパッド用のＳｉＯ2 膜１
２を形成する。In this embodiment, as shown in FIG.
A Si substrate 11 is prepared, the Si substrate 11 is thermally oxidized, and as shown in FIG. 1B, a SiO 2 film 1 for a pad having a thickness of about 50 nm is formed on the entire surface of the Si substrate 11.
Form 2.
【００１５】次に、ＳｉＯ2 膜１２上の全面に膜厚が１
５０ｎｍ程度のＳｉ3 Ｎ4 膜１３を減圧ＣＶＤ法で堆積
させ、このＳｉ3 Ｎ4 膜１３上にレジスト（図示せず）
を塗布する。そして、リソグラフィ技術を用いてレジス
トを素子活性領域のパターンに加工し、このレジストを
マスクにしてＳｉ3 Ｎ4 膜１３のみをドライエッチング
する。その後、レジストをアッシングで除去して、図１
（ｃ）に示す状態を得る。Next, a film thickness of 1 is formed on the entire surface of the SiO 2 film 12.
A Si 3 N 4 film 13 of about 50 nm is deposited by a low pressure CVD method, and a resist (not shown) is formed on the Si 3 N 4 film 13.
Apply. Then, the resist is processed into a pattern of the element active region by using a lithographic technique, and only the Si 3 N 4 film 13 is dry-etched using the resist as a mask. After that, the resist is removed by ashing, and FIG.
The state shown in (c) is obtained.
【００１６】次に、図１（ｄ）に示すように、膜厚が２
００ｎｍ程度のＳｉ3 Ｎ4 膜１５を減圧ＣＶＤ法で再び
全面に堆積させ、このＳｉ3 Ｎ4 膜１５の全面をドライ
エッチングで異方性エッチングして、図１（ｅ）に示す
ように、Ｓｉ3 Ｎ4 膜１５から成る側壁をＳｉ3 Ｎ4 膜
１３の開口部の内側面にこのＳｉ3 Ｎ4 膜１３に対して
自己整合的に形成する。Next, as shown in FIG. 1D, the film thickness is 2
A Si 3 N 4 film 15 having a thickness of about 00 nm is again deposited on the entire surface by the low pressure CVD method, and the entire surface of the Si 3 N 4 film 15 is anisotropically etched by dry etching, as shown in FIG. formed in self-alignment to the Si 3 N 4 this the Si 3 N 4 film 13 on the inner surface of the opening portion of the side wall comprising a membrane 15 the Si 3 N 4 film 13.
【００１７】次に、Ｓｉ3 Ｎ4 膜１３、１５を耐酸化膜
のマスクにしてＳｉ基板１１の表面を酸化して、図１
（ｆ）に示すように、Ｓｉ基板１１の表面のうちでＳｉ
3 Ｎ4膜１３、１５が形成されていない部分に膜厚が６
００ｎｍ程度のＳｉＯ2 膜１４を形成する。その後、図
１（ｇ）に示すように、熱燐酸でＳｉ3 Ｎ4 膜１３、１
５を除去して、ＳｉＯ2 膜１４で素子分離領域を形成す
る。Next, the surface of the Si substrate 11 is oxidized by using the Si 3 N 4 films 13 and 15 as a mask of an oxidation resistant film, and the structure shown in FIG.
As shown in (f), Si of the surface of the Si substrate 11 is
The film thickness is 6 in the portion where the 3 N 4 films 13 and 15 are not formed.
A SiO 2 film 14 of about 00 nm is formed. Then, as shown in FIG. 1 (g), the Si 3 N 4 films 13 and 1 are formed by hot phosphoric acid.
5 is removed, and an element isolation region is formed by the SiO 2 film 14.
【００１８】以上のように本実施例においては、ＳｉＯ
2 膜１４を形成する際の酸化は等方的に進行するので、
図１（ｆ）及び（ｇ）に示したように、ＳｉＯ2 膜１４
にバーズビーク１４ａが形成されるが、Ｓｉ3 Ｎ4 膜１
３、１５の全体のパターンが素子活性領域のパターンよ
りも大きくなっているので、その分だけ素子分離領域の
パターンが小さくなっている。従って、Ｓｉ3 Ｎ4 膜１
５の幅を最適化することによって、設計した素子分離領
域の寸法通りのＳｉＯ2 膜１４を形成することができ
る。As described above, in this embodiment, SiO
Since the oxidation when forming the 2 film 14 proceeds isotropically,
As shown in FIGS. 1F and 1G, the SiO 2 film 14 is formed.
The bird's beak 14a is formed on the Si 3 N 4 film 1
Since the entire patterns of 3 and 15 are larger than the pattern of the element active region, the pattern of the element isolation region is correspondingly smaller. Therefore, the Si 3 N 4 film 1
By optimizing the width of 5, the SiO 2 film 14 can be formed according to the dimension of the designed element isolation region.
【００１９】[0019]
【発明の効果】本発明の半導体装置の製造方法によれ
ば、リソグラフィの限界程度の寸法の素子分離領域でも
設計値通りのパターンに酸化膜を形成することが可能で
あるので、微細で且つ特性の優れた半導体装置を製造す
ることができる。According to the method of manufacturing a semiconductor device of the present invention, it is possible to form an oxide film in a pattern according to a design value even in an element isolation region having a dimension about the limit of lithography, so that it is fine and has a characteristic. It is possible to manufacture an excellent semiconductor device.
【図１】本発明の一実施例による半導体装置の製造方法
を工程順に示す側断面図である。FIG. 1 is a side sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【図２】従来の半導体装置の製造方法を工程順に示す側
断面図である。FIG. 2 is a side sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.
１１ Ｓｉ基板 １３ Ｓｉ3 Ｎ4 膜 １４ ＳｉＯ2 膜 １５ Ｓｉ3 Ｎ4 膜11 Si substrate 13 Si 3 N 4 film 14 SiO 2 film 15 Si 3 N 4 film
Claims (1)
の第１の耐酸化膜を形成する工程と、 前記第１の耐酸化膜の側面に第２の耐酸化膜から成る側
壁を形成する工程と、 前記第１及び第２の耐酸化膜をマスクにして前記半導体
基板を酸化して、素子分離領域の表面に酸化膜を形成す
る工程とを有することを特徴とする半導体装置の製造方
法。1. A step of forming a first oxidation resistant film having a pattern of a device active region on a semiconductor substrate, and a step of forming a side wall made of a second oxidation resistant film on a side surface of the first oxidation resistant film. And a step of oxidizing the semiconductor substrate using the first and second oxidation resistant films as a mask to form an oxide film on the surface of the element isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10030293A JPH06291113A (en) | 1993-04-02 | 1993-04-02 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10030293A JPH06291113A (en) | 1993-04-02 | 1993-04-02 | Fabrication of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06291113A true JPH06291113A (en) | 1994-10-18 |
Family
ID=14270380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10030293A Pending JPH06291113A (en) | 1993-04-02 | 1993-04-02 | Fabrication of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06291113A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018037692A (en) * | 2017-12-07 | 2018-03-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1993
- 1993-04-02 JP JP10030293A patent/JPH06291113A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018037692A (en) * | 2017-12-07 | 2018-03-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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