JPH06290050A - Computer and its program loading method - Google Patents

Abstract

PURPOSE:To load data to a program area in a computer provided with a CPU constituting the program area and a data area of respectively independent buses by writing data at the time of executing a read instruction. CONSTITUTION:The CPU 1 turns a port signal P200 to 'H' at first. Then the CPU 1 outputs data stored in its register to a data area bus (BUSD) 8 and writes the data in a flop flop(FF) by a signal WR574. Then the CPU 1 executes a program for reading out the data of a RAM 3 included in the program area. At this time, an address bus A15-is turned to 'H' and a program selection enable signal PSEN is turned to 'L'. Thereby the output of an OR circuit 6 is turned to 'H' and no data is outputted from the RAM 3. When the output of the OR circuit 6 is 'L', the FF 4 outputs its stored data to the program area bus (BUSPD) 9 and the outputted data are written in the RAM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU in which a program area and a data area are composed of separate buses.
And a program loading method thereof.

[0002]

2. Description of the Related Art In a conventional computer, the program area and the data area are the same, and the program loading and the data writing are the same. However, in recent years, in order to increase the speed, a computer including a CPU (for example, MSM67620 of Oki Electric Industry Co., Ltd.) including a separate bus for a program area and a data area has been manufactured.

[0003]

However, a conventional computer having a CPU having a program area and a data area each formed of a separate bus has a program written in a ROM in advance. Was impossible to load. Therefore, it is possible to manufacture a programmable logic controller (PLC) in which, for example, a part of the program is opened to the user and can be freely rewritten by an external command by using a CPU having a different program area and data area. There wasn't. Therefore, the present invention provides a computer that can write data to a program area that is originally unwritable in a computer including a CPU having a program area and a data area that are independent buses and a method for loading the program. The purpose is to do.

[0004]

A computer of the present invention is a computer including a CPU having a program area and a data area each formed by a separate independent bus, and a RAM provided in the program area and an object to be written. When a signal for selecting the data area as an area and a signal indicating an assigned address are output, a data holding means for holding data on the bus of the data area, and a port signal output by the operation of the CPU And a port signal output means for continuously outputting the port signal until the CPU stops the output, and the CPU when the port signal is being output.
When the CPU executes an instruction to read the contents of the RAM, a write signal output unit that activates the writing of the RAM by using the read signal of the program area output from the CPU as a write signal at that time, and the port signal is output. When the CPU executes an instruction to read the contents of the RAM while the data is being written, the data holding means outputs the data held by the data holding means to the bus in the program area. . Further, the program loading method of the present invention is
A method of loading a program into a computer according to the present invention, wherein the RAM is used when writing the program.
Output the data to be written to the bus of the data area,
While holding the data in the data holding means, then outputting the port signal, and then executing a program for reading the contents of the address of the RAM, and outputs the data held in the data holding means to the bus of the program area ,
A program is loaded into the RAM by outputting a write signal that activates the writing of the RAM from the write signal output means to the RAM.

[0005]

When the program is written, the port signal is output, and the CPU outputs the data to be written in the RAM to the bus in the data area and holds it by the data holding means. After that, a program for reading the contents of the RAM address is executed. As a result, the data holding means outputs the held data to the bus in the program area. at the same time,
The write signal output means activates the write to the RAM. Therefore, the program can be loaded (written) in the RAM.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram showing a computer of an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the embodiment of FIG. A 16-bit data area bus (hereinafter, referred to as BUSD) 8 is provided on the left side of the CPU 1 in the figure, and a 16-bit program area bus (hereinafter, referred to as BUSPD) 9 is provided on the right side. BUS D8 has B
Flip-flop (hereinafter referred to as F / F) 4 that is a 16-bit data holding unit that holds data on the USD 8
The data input terminals are connected to a memory, a connector, and the like in a data area (not shown). BUSPD9 has
Data output terminal of F / F4 and hexadecimal address 0000
16 bit data ROM to which ~ 7FFF is assigned
2 and the RAM 3 of 16-bit data to which hexadecimal addresses 8000 to FFFF are assigned are connected.
Usually, these ROM2 and RAM3 are accessed by setting a program select enable signal PSEN, which will be described later, to L level. Since the ROM 2 may have a table, not only the program but also the data can be read by the program select enable signal PSEN. An address for the first address in the data area is assigned to the F / F4. The address bus exists in both the data area and the program area, but is omitted in the drawing. Signals for the CPU 1 to control these buses include a read signal RD and a write signal WR for the data area,
There is a program select enable signal PSEN for the program area. Both buses (BUST8, B
USPD9) is not synchronized at all, so write signal W
It goes without saying that R is not used. To the output terminal of the program select enable signal PSEN, one of the input terminals of the OR circuits 5 and 6 and the output enable terminal OE of the ROM 2 are connected. ROM
The uppermost address bus A ₁₅ of the CPU 1 is connected to the chip enable terminal 2 of the CPU 1. An output port (not shown) of the CPU 1 that outputs the port signal P200 is connected to the other input terminal of the OR circuit 5. This output port outputs the port signal P200 by the operation of the CPU 1 and continues to output the port signal P200 until the CPU 1 performs the operation of stopping the output. The output terminal of the inverter 7 that inverts the level of the port signal P200 is connected to the other input terminal of the OR circuit 6. The other input terminal of the OR circuit 6 has an inverter 10 for inverting the level of the highest address bus A ₁₅ of the CPU 1.
The output terminal of is connected. The output terminal of the inverter 10 is also connected to the chip enable terminal CE of the RAM 3. The output enable terminal OE of the RAM 3 is connected to the output terminal of the OR circuit 5. The output enable terminal of the F / F 4 and the write terminal WR of the RAM 3 are connected to the output terminal of the OR circuit 6. The OR circuits 5, 6 and the inverters 7, 10 are the CPU 1
The program select enable signal PSEN, which is a read signal of the program area, is used as a write signal for activating the writing of the RAM3, and data writing for outputting the data held by the F / F4 to the BUSPD9. Act as a means. The signal line of the signal WR574 is connected to the clock input terminal of the F / F4. Signal WR574
Is a signal obtained by decoding a signal indicating an address assigned to the F / F 4, and a write signal W that is a signal for selecting a data area as an area to be written by the CPU 1.
It is a signal that is ORed with R. Each bus and port signal P200 is active at H, and other signals and terminals are active at L.

Next, the operation of this embodiment will be described. In addition,
The program for the following operation may be stored in the ROM 2 or a built-in ROM (not shown) of the CPU 1. First, the CPU 1 sets the port signal P200 to H (step 11). Next, the CPU 1 writes the data to be written in the RAM 3 into the register in the CPU 1 (step 12). This data to be written is, for example, input from an external data input device. Next, the CPU 1 writes the contents written in the register to BUS D8.
To the F / F4 by the signal WR574 (step 13). Next, the address of RAM3, for example, 8000
A program for reading the address data is executed (step 14). At this time, since the address bus A ₁₅ indicating the address of the RAM3 becomes H, ROM2 the ROM2 chip enable terminal CE becomes H becomes inactive. On the other hand, the chip enable terminal CE of RAM3 is L
It becomes (active), and one input terminal of the OR circuit 6 also becomes L. At the same time, since the program select enable signal PSEN becomes L, one input terminal of each of the OR circuits 5 and 6 becomes L. However, if the port signal P200 is H
Therefore, the other input terminal of the OR circuit 5 becomes H. Therefore, the output of the OR circuit 5 is H, the output enable terminal OE of the RAM 3 is H (inactive), and nothing is output from the RAM 3. Further, since the output of the inverter 7 becomes L, all the input terminals of the OR circuit 6 become L. Therefore, the output of the OR circuit 6 is L, the output enable terminal of the F / F 4 becomes L (active), the output is opened, and the held data is output to the BUSPD 9. At the same time, the write terminal WR of the RAM3 becomes L (active), and the BU
The data on SPD9 is written. This means that the program for the first address has been loaded. Next, check whether the program has been loaded (step 1
5). If the loading is not completed, steps 11 to 15 are similarly executed at the next address of the RAM 3. After the loading is completed, the port signal P200 is set to L (step 16). This allows RAM3 as well as ROM2.
Can be read and the program loaded in the RAM 3 can be executed. Therefore,
According to the configuration of this embodiment, a part of the program is open to the user, and the programmable logic controller (PL) can be freely rewritten by an external command.
C) etc. can also be produced.

[0008]

As described above, according to the present invention, CP
When U executes an instruction to read the code data from the RAM in the program area, the contents of the data holding means holding the data to be written are written in the RAM, so that the program area and the data area are independent from each other. In a computer including a CPU configured as described above, there is an effect that data can be loaded into a program area that is originally unwritable.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a computer according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 DF / F 5,6 OR circuit 7,10 Inverter 8 BUSD 9 BUSPD 11 to 15 steps

Claims (2)

[Claims] 1. A computer provided with a CPU comprising a program area and a data area each of which is composed of a separate bus, and a RAM provided in the program area and a signal for selecting the data area as an area to be written. When the signal indicating the assigned address is output, the data holding means for holding the data on the bus in the data area, and the port signal output by the operation of the CPU, the CP
Port signal output means for continuously outputting the port signal until U performs the operation of stopping the output, and when the CPU executes an instruction to read the contents of the RAM while the port signal is being output, Write signal output means for making a read signal of a program area output from the CPU a write signal to activate writing in the RAM, and the CPU reads the content of the RAM when the port signal is output. And a data writing unit that outputs the data held by the data holding unit to the bus in the program area when the instruction is executed. 2. A method for loading a program into a computer according to claim 1, wherein when writing the program, data to be written in said RAM is output to a bus in a data area and held by said data holding means. , Then outputs the port signal, then executes a program for reading the contents of the address of the RAM, outputs the data held by the data holding means to the bus in the program area, and outputs the data from the write signal output means. A method for loading a program, wherein a program is loaded into the RAM by outputting a write signal that activates writing in the RAM to the RAM.