JPH0628891A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize a semiconductor memory reducing a cost in a redundancy test and improving reliability. CONSTITUTION:The semiconductor memory having a redundant circuit is provided with a redundant program circuit 4 operating the redundant circuit according to an input address at a regular mode time, a circuit 7 outputting a test mode signal at a test mode time, an address latch and comparator circuit 5 receiving the test mode signal and holding the specified address, and comparing between the input address and the held specified address, and outputting a coincidence signal when the input signal coincides with the specified address and a redundancy test start circuit 6 outputting a redundant circuit start signal RSS operating the redundant circuit by the input of the coincidence signal. Redundancy is peudo-programed and activated, the test for the redundant circuit is executed together with a regular circuit part in a state close to actual operation before through a redundant program process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant circuit for repairing a defect of a memory element.

[0002]

2. Description of the Related Art A semiconductor memory device has been increased in capacity with the progress of miniaturization processing technology in recent years, and high integration of memory chips has been realized. The semiconductor memory device having such a structure has a so-called redundant circuit structure in which spare memory cells for repairing defective memory cells are arranged in advance in the memory array in order to improve the manufacturing yield.

Since a spare memory cell is formed on a wafer by the same manufacturing process as a normal memory cell, a defect may occur in the spare memory cell itself like the normal memory cell. It is necessary to actually operate the redundant circuit as to whether or not the circuit functions without any problem. Therefore, conventionally, a so-called wafer test at the time of manufacture is used to perform a redundant circuit operation confirmation test using a tester.

As a concrete method, first, a tester determines whether or not redundant replacement is possible. If a good result is obtained here, a redundant program step is performed to cut a desired memory cell fuse for selecting a redundant circuit to repair a defective memory cell with a laser or the like. Next, using a tester again, an operation confirmation test including a redundant circuit is performed here.

However, in the above-described redundancy test method, the operation of the redundant circuit cannot be confirmed unless the redundant program step of cutting the fuse is performed, and even after the redundant program step, the spare memory cell is There is a problem in that it may occur when there is a defect in, for example, it does not operate normally, so that it takes a lot of trouble and causes an increase in measurement cost.

In order to solve such a problem, conventionally, in the test mode, a method of directly accessing only the redundant circuit to confirm the operation has been proposed (reference: H. Goto., Et.
al., "A 3.3V 12ns 16Mb CMOS SRAM", ISSCC DIGEST OF
TECHNICAL PAPERS. Pp.216-217, Feb.1992).

[0007]

However, this method is
The normal circuit can be tested only by operating the redundant circuit in a non-operating state, that is, it can perform only so-called static test, and examines the state close to actual operation, that is, the pattern dependence due to interference with surrounding bits. , So-called practical dynamic test cannot be performed. Therefore, only a test result with low reliability can be obtained, which has been an obstacle to improving the reliability of the semiconductor memory device.

The present invention has been made in view of the above circumstances, and an object thereof is to perform a test that is practical and reliable as well as to reduce cost without requiring a complicated labor for a redundant test. An object of the present invention is to provide a semiconductor memory device capable of improving the property.

[0009]

In order to achieve the above object, according to the present invention, in a semiconductor memory device having a normal circuit and a redundant circuit formed to relieve a defect of the normal circuit, a test mode signal When applied,
A test circuit for operating the normal circuit and the redundant circuit corresponding to the applied address is provided.

In the present invention, the test circuit performs a dynamic interference test (disturbance test) of the redundant circuit.

In the present invention, when the test circuit operates the redundant circuit, the test circuit prohibits the operation of the redundant circuit selection drive circuit to perform the above operation.

According to the present invention, in a semiconductor memory device having a redundant circuit formed to relieve a defect of the normal circuit in addition to the normal circuit, a redundant program circuit for operating the redundant circuit according to an input address in the normal mode. When,
A circuit that outputs a test mode signal in the test mode,
An address hold comparison circuit that receives the test mode signal, holds the specified address, compares the input address with the held specified address, and outputs a match signal when the input address matches the specified address. And a redundant test starting circuit for outputting a redundant circuit starting signal for operating the redundant circuit.

In the present invention, a circuit is provided which decodes the input address signal and inputs the decoded address signal to the redundant program circuit and the address holding / comparing circuit.

[0014]

According to the present invention, when the test mode signal is applied, the normal circuit and the redundant circuit corresponding to the address applied by the test circuit are operated to perform the test.

According to the present invention, the test circuit performs the interference test of the redundant circuit accompanying the cooperation with the normal circuit.

According to the present invention, when the redundant circuit is operated, the operation of the redundant circuit selection drive circuit is prohibited by the test circuit.

According to the present invention, in the normal mode, the redundant circuit is activated according to the input address information. on the other hand,
In the test mode, a test mode signal is generated and input to the address holding / comparing circuit. The address holding / comparing circuit holds the designated address in response to the input of the test mode signal. When a predetermined address is input to the address holding / comparing circuit in this state, the address holding / comparing circuit compares the input address with the held designated address, and as a result of the comparison, the input address matches the designated address. Then, the coincidence signal is output to the redundancy test starting circuit. In the redundant test starting circuit, a test starting signal is generated in response to the input of the match signal, and the redundant circuit is started based on this.

According to the present invention, the input address signal is subjected to a predetermined decoding process by the decoding circuit and is input to the redundant program circuit and the address holding / comparing circuit.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first semiconductor memory device according to the present invention.
It is a block diagram which shows the Example of. In FIG. 1, 1 is an address input pad, 2 is an address buffer, 3 is a predecoder, 4 is a redundant program circuit, 5 is an address latch comparison circuit, 6 is a redundancy test start circuit, and 7 is a redundancy test control circuit. There is.

The redundancy program circuit 4 receives the address information A input via the address buffer 2 in the normal mode.
_{Based on 0} (to A _n ), a redundant circuit activation signal RSS for activating a redundant circuit such as a spare decoder (not shown) is generated. At the same time, a disable signal DSB for inactivating the defective bit is generated. On the other hand, in the redundancy test mode, the redundancy test activation circuit 6 receives the test activation signal TAS and outputs the redundancy circuit activation signal RSS for activating the redundancy circuit (not shown).

The address latch comparison circuit 5 receives the test mode signal T output from the redundancy test control circuit 7.
When the designated defective address activated by the input of ST is input and latched through the address input pad 1, and the input address A ₀ matches the latched defective address, the coincidence signal R ₀ (to R _n ) is activated in the redundancy test. Output to the circuit 6.

The redundancy test starting circuit 6 outputs the test starting signal TAS to the redundant program circuit 4 when receiving the output coincidence signal R ₀ (to R _n ) of the address latch comparing circuit 5. At the same time, it outputs a disable signal DSB for inactivating the normal bit.

The redundancy test control circuit 7 receives the control signal CTL from the control system (not shown) via the NC pin or the normal pin and outputs the test mode signal TST.
Is output to the address latch comparison circuit 5.

A normal circuit and a redundant circuit (not shown) of a semiconductor memory device having such a test circuit are mainly composed of a memory cell which is a minimum unit of memory, and have a high level "1" or a low level "0". Unit cells, which are elements that store any one of the two values, are arranged in a row (row) direction and a column (column) direction in a plane to form a so-called matrix array. In the memory array, word lines select memory cells in the row direction, and word lines are selected by a row decoder in response to a row address input signal from the outside. When a set of memory cells arranged in the column direction is selected by the word line, the data stored in these memory cells is transferred to the bit line. Further, replacement of a defective memory cell with a spare memory cell (actually, replacement of a word line including the defective memory cell with a spare word line) is performed by registering a defective address in a spare decoder that selects the spare memory cell. Done. As a specific registration means, a method of cutting the fuse with a laser based on a predetermined redundant program or a method of electrically cutting the fuse is used.

Next, the operation of the above configuration will be described. First, in the normal mode, the address signal input to the address input pad 1 is input to the redundant program circuit 4 as the signal A ₀ via the address buffer 2. In the redundant program circuit 4, when the input address matches the pre-programmed address, the redundant circuit activation signal RSS is generated and output to the redundant circuit (not shown) corresponding to the address to activate the redundant circuit. In addition,
At this time, at the same time as the generation of the redundancy circuit activation signal RSS, the disable bit DSB of the normal bit corresponding to the address is generated, and the defective bit may be inactivated.

On the other hand, in the test mode, the control signal CTL from the control system (not shown) is input to the redundancy test control circuit 7. At this point, nothing has been programmed in the redundant program circuit 4 described above. When the control signal CTL of the redundancy test control circuit 7 is input, the redundancy test mode is activated, and the test mode signal TST is output from the redundancy test control circuit 7 to the address latch comparison circuit 5. In the address latch comparison circuit 5 which receives the test mode signal TST, the latch is activated.

In this state, an address signal of a defective address for which redundancy is desired is input to the address input pad, and this defective address is latched by the address latch comparison circuit 5. By latching the defective address, the redundant address is temporarily programmed.

Here, a predetermined address signal is input to the address input pad 1, and this address signal is input to the address latch comparison circuit 5. The address latch comparison circuit 5 compares the input address with the latched defective address. As a result of the comparison, if the input address matches the latch defective address, the match signal R ₀ corresponding to the address is output to the redundancy test starting circuit 6.

The redundancy test starting circuit 6 performs a predetermined logical operation, for example, a logical product, and outputs the test starting signal TAS.
Is generated and output to the redundant program circuit 4. In the redundant program circuit 4, the redundant circuit activation signal RSS is generated in response to the input of the test activation signal TAS, is output to the redundant circuit (not shown) corresponding to the address, and the redundant circuit is activated. In the redundant test starting circuit 6, the disable signal DSB is generated at the same time when the test starting signal TAS is generated, and the normal bits are inactivated.

As described above, according to this embodiment,
Address latch comparison circuit 5 as a redundancy test latch for pseudo-programming and activating redundancy
Since the above is provided, it is possible to test the redundant circuit together with other normal parts in a state close to the actual operation before the redundant programming process is performed. Therefore, it is possible to prevent the unnecessary execution of the test and prevent the increase of the measurement cost, and also to perform the dynamic interference test in a practical state while operating the redundant circuit and the normal circuit.
Since the influence of bit-to-bit interference and the like can also be tested, the reliability of the test can be improved, and thus the reliability of the semiconductor memory device can be improved.

When the number of redundancy is plural, rows (rows),
Even when the column is used together, a plurality of address latch comparison circuits 5 and redundant test starting circuits 6 are provided and controlled by the redundant test control circuit 7, so that the same test as described above can be performed. The same effect can be obtained. Furthermore, it is also possible to combine a so-called super-voltage method in which a voltage higher than the standard voltage V _CC is used for the input signal to the address input pad 1.

FIG. 2 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention. The second embodiment differs from the first embodiment in the following points. That is, in the first embodiment, the address signal input to the address input pad 1 is input to the address latch comparison circuit 5 and the address signal via the address buffer 2 is input to the redundant program circuit 4. In contrast,
In the second embodiment, the address signal subjected to the predetermined decoding processing in the predecoder 3 is input to the address latch comparison circuit 5 and the redundancy program circuit 4 via the address buffer 2.

Also in the semiconductor memory device of the second embodiment having such a structure, the same effect as that of the first embodiment can be obtained.

The present invention is a DRAM (Dynamic Random).
m Access Memory) and SRAM (Static Random Access Me)
Needless to say, it can be applied to various semiconductor memory devices such as a mory).

[0035]

As described above, according to the semiconductor memory device of the present invention, the redundant circuit is tested together with other normal circuit parts in a state close to the actual operation before the redundant program process is performed. You can Therefore, unnecessary test execution can be prevented and increase in measurement cost can be prevented. In addition, an interference test and the like can be performed in a practical state while operating the redundant circuit and the normal circuit. Since the effect of can be tested, the reliability of the test can be improved, and the reliability of the semiconductor memory device can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of a semiconductor memory device according to the present invention.

[Explanation of symbols]

1 ... Address input pad 2 ... Address buffer 3 ... Predecoder 4 ... Redundant program circuit 5 ... Address latch comparison circuit 6 ... Redundancy test start circuit 7 ... Redundancy test control circuit TST ... Test mode signals R _{0 to} R _n … Match signal TAS … Test activation signal RSS… Redundant circuit activation signal

Claims (5)

[Claims] 1. A semiconductor memory device having, in addition to a normal circuit, a redundant circuit formed to relieve a defect in the normal circuit, when the test mode signal is applied, the normal memory corresponding to the applied address is applied. A semiconductor memory device comprising a circuit and a test circuit for operating the redundant circuit. 2. The semiconductor memory device according to claim 1, wherein the test circuit performs a dynamic interference test of the redundant circuit. 3. The semiconductor memory device according to claim 1, wherein when the test circuit operates the redundant circuit, the test circuit prohibits the operation of the redundant circuit selection drive circuit to perform the operation. 4. A semiconductor memory device having, in addition to a normal circuit, a redundant circuit formed to relieve a defect in the normal circuit, a redundant program circuit for operating the redundant circuit according to an input address in a normal mode, The circuit that outputs the test mode signal in the test mode and the address specified by receiving the test mode signal are held, the input address is compared with the held specified address, and it matches when the input address matches the specified address. A semiconductor memory device comprising: an address holding / comparing circuit that outputs a signal; and a redundant test starting circuit that outputs a redundant circuit starting signal that operates the redundant circuit when a match signal is input. 5. Decoding the input address signal,
5. The semiconductor memory device according to claim 4, further comprising a circuit for inputting the decoded address signal to the redundant program circuit and the address holding / comparing circuit.