JPH0628854A - Semiconductor step-down circuit - Google Patents

Abstract

PURPOSE:To provide a step-down circuit whose loss is low, and whose output voltage is stable on a semiconductor circuit. CONSTITUTION:Two capacitors C1 and C2 whose capacities are equal, and transistors Tr1 and Tr2 are used. At the time of charging the two capacitors C1 and C2 are serially connected, and the charge is operated by an input power source VEXT. And also, at the time of a discharge, each capacitor is connected in parallel, and connected with an output VINT. Thus, a voltage 1/2 times as large as the input voltage VEXT can be generated as the output VINT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor step-down circuit,
In particular, it relates to a step-down circuit for semiconductor memory.

[0002]

2. Description of the Related Art A conventional step-down circuit for a semiconductor memory is of a series regulator type. This step-down circuit is, for example, an IEEE Journal of Soli.
d-State Circuits, Vol. 25,
No. 4, 1990 pp903-911 and the like.

FIG. 6 is a semiconductor step-down circuit diagram showing such a conventional example. As shown in FIG. 6, the conventional series regulator type step-down circuit has a comparator 7 composed of an operational amplifier and a drive transistor Tr1 driven by the output of the comparator 7, and its output V _INT is loaded with a load. Z
It is configured by connecting. The reference power supply V _EXT / 2 is supplied to one input of the operational amplifier 7, and the output voltage V _INT of the step-down circuit is supplied to the other input, and the difference between the reference voltage and the output voltage is detected. The detected difference voltage is input to the gate of the drive transistor Tr1 to control the output voltage V _INT .

Next, regarding the power consumed by this step-down circuit, when the load z connected ahead of the output V _INT consumes the current I _D , the power P _S consumed by the drive transistor Tr1 is the external input. If the voltage is V _EXT , then P _S = (V _EXT −V _INT ) × _ID . Therefore, if the output voltage is V _INT = V _EXT / 2, the power consumption of Tr1 is P _S = (V _EXT / 2) × _ID .

[0005]

SUMMARY OF THE INVENTION In the above conventional series regulator type semiconductor step-down circuit, the voltage between the source and drain of the drive transistor is V _DS ,
If the current flowing through the transistor is I _DS , then V _DS ×
Power of I _DS is wastefully consumed by the memory circuit external to the drive transistor, the output voltage has the disadvantage that not stable.

An object of the present invention is to provide a semiconductor step-down circuit which can eliminate such useless power consumption and stabilize the output voltage.

[0007]

The semiconductor step-down circuit of the present invention uses m × n capacitors (m <n, m, n is an integer) having the same capacitance, and n capacitors are connected in series during charging. Output m / n of input voltage by connecting m sets in parallel and charging by the input power source, and connecting m sets in series at the time of discharging and connecting n sets in parallel to the output To be configured.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. 1A and 1B are a semiconductor step-down circuit diagram and a timing diagram of clock signals of the circuit, respectively, showing an embodiment of the present invention. As shown in FIG. 1A, in this embodiment, a transistor Tr1, a capacitor C1, and a transistor T which are alternately connected between an input V _EXT and a ground.
r2, a capacitor C2, and transistors Tr3 and Tr5 connected between the nodes B and D and the output V _INT.
And a transistor Tr connected between node A and ground
4 and an inverter. Transistor Tr1
The clock φ1 is directly supplied to the gate of the
1 is inverted and supplied. Similarly, the clock φ2 is directly supplied to the gate of the transistor Tr3, and the clock φ2 is inverted and supplied to the gates of the transistors Tr4 and Tr5 via an inverter.

Further, as shown in FIG. 1B, here, the clock φ2 is inverted with respect to the clock φ1, and at the same time, the on / off time is made different. Figure 1 again
It returns to (a) and demonstrates.

In FIG. 1 (a), capacitors C1 and C
The capacities of 2 are set equal. Also, φ1 is H and φ2 is L
During the period, Tr1 and Tr2 are turned on, and Tr3 and Tr2 are turned on.
4, Tr5 is off. At this time, capacitor C
Both 1 and C2 are charged to (1/2) V _EXT , and A
The voltage at point B, point B, and point D is (1/2) V _EXT , V respectively.
_EXT , (1/2) V _EXT . Next, when φ1 becomes H, all the transistors are turned off. Then φ2 is L
Then, Tr1 and Tr2 are turned off and Tr3 and Tr4 are turned off.
Tr5 turns on. Then, the point A becomes the ground potential, and the points B and D become (1/2) V _EXT , respectively. Therefore, from the output V _INT , half ( _1/1 /) of the input V _EXT
2) A voltage of V _EXT is obtained.

Next, the power consumed by the circuit shown in FIG. 1A will be described with reference to FIGS. 2A and 2B.

2 (a) and 2 (b) are respectively shown in FIG. 1 (a).
FIG. 3 is an equivalent circuit diagram when discharging and charging the step-down circuit in FIG. FIG. 2A shows the circuit of FIG. 1, where φ1 = H and φ2 =
In the case of L (discharge period), in FIG. 2B, φ1 = L, φ2 =
The case of H (charging period) is shown. In addition, FIG.
Then, the initial potential of V _INT is set to (1/2) V _EXT, and the capacitances of capacitors C1 and C2 are both set to C. In FIG. 2B, the on resistance of the transistor of FIG. 1 is extremely low and can be ignored. .

First, as shown in FIG. 2A, when a current of I _D flows through the load Z for a time of Δt, the capacitor C
The charge ΔQ lost from 1, C2 is ΔQ = I _D Δt. Therefore, the decrease amount ΔV of the voltage of V _INT is ΔV = ΔQ / 2C = _ID Δt / 2C, and therefore the voltage V _C1 across the capacitors C1 and C2,
V _C2 is V _C1 = V _C2 = (1/2) V _EXT −ΔV.

Next, as shown in FIG. 2B, when the charging state is switched, the capacitors C1 and C2 are charged.
At this time, the electric power required to charge the capacitors C1 and C2 is the sum of the electric power consumed by the step-down circuit and the electric power consumed by the load Z. The potential V _B at the first B point is _{V B = V C1 + V C2} = V EXT -2ΔV, energy E _A point B is consumed by the entire circuit until VEXT is, E _A = CV _EXT [Delta] V = V _{EXT ID} Δt / 2. The energy EZ consumed load Z during the Δt, since a _{E Z = CV EXT ΔV- (1/4} ) CΔV 2, the power consumption P _C of the step-down circuit, P _C = (E _A -E _Z ) / Δt = CΔV ² / 4Δt = ΔVI _D / 8. Therefore, when ΔV → 0, the power consumption of the circuit of FIG. 1 is ideally 0, and it can be seen that the loss is extremely low as compared with the conventional circuit.

In short, in the present embodiment, since the input voltage is divided by the capacitance without using the resistor, ideally no power loss occurs. In addition, since the step-down unit that is not used works as a stabilizing capacitor, the output voltage can be stabilized.

FIGS. 3A and 3B are equivalent circuit diagrams of the step-down circuit at the time of charging and discharging, respectively, for explaining the second embodiment of the present invention. As shown in FIG.
, C1n, capacitors C21, C22, ..., C2n, ..., Capacitors Cm1, Cm2, ..., Cmn are connected in parallel between the input V _EXT and ground. Further, as shown in FIG. 3B, at the time of discharging, the capacitor on the array is connected between the output V _INT and the ground. With this configuration, the present embodiment does not set the input / output relationship to V _INT = (1/2) V _EXT , but V _INT = (m / n) V _EXT (m <n, m, n
Can generate any output V _INT that satisfies the relationship

FIG. 4 is a block diagram of a semiconductor step-down circuit showing a third embodiment of the present invention. As shown in FIG. 4, in this embodiment, a small capacity step-down unit 1a and a large capacity step-down unit 1b, a clock generation circuit 2 for supplying a clock to these step-down units 1a and 1b, an output VINT and a reference voltage Vref.
And a latch circuit 3 that controls the supply of the clock from the clock generation circuit 2 to the large capacity step-down unit 1b based on the output of the comparator 4. In particular, when the capacitance of each of the capacitors forming the small-capacity step-down unit 1a is C1 and the capacitance of each of the capacitors of the large-capacity step-down unit 1b is C2, there is a relationship of C1 <C2 between them. is there. Further, the reference voltage V _REF is V _REF = (m / n) V
Set as _EXT- ΔV.

First, when the load is light, the output V _INT is almost (m / n) V _EXT , so the output of the comparator 4 is L.
Therefore, the clock supplied to the large capacity step-down unit 1b is stopped. Here, the step-down unit 1b in the clock stopped state is set to the discharging state. In this discharge state,
Since the capacitor of the large capacity step-down unit 1b works as a stabilizing capacity, the output V _INT becomes stable.

Next, when the load becomes heavy and the voltage of the output V _INT drops by ΔV or more, the output of the comparator 4 becomes H, and a clock is supplied to the large capacity step-down unit 1b, so that a large amount of power can be obtained.

FIGS. 5A and 5B are a block diagram of a semiconductor step-down circuit and a timing diagram of clock signals of the circuit, respectively, showing a fourth embodiment of the present invention. Figure 5
As shown in (a), in this embodiment, the large-capacity step-down unit 1b in FIG.
This is an example configured with a and 5b. Further, as shown in FIG. 5B, clocks φ1A,
By shifting φ2A by 1/2 phase, the step-down units 5a, 5
b is alternately discharged, and the output can be stabilized. The large-capacity step-down unit 1b can further improve the stability by preparing k step-down units 5a, ..., 5k having the same capacity and shifting the phases of each by 1 / k.

[0021]

As described above, the semiconductor voltage step-down circuit of the present invention has the effect of ideally reducing the loss to zero by dividing the input voltage by the capacitor. Further, according to the present invention, the output voltage can be stabilized by operating several step-down units in parallel, and when one of the step-down units is not used, the step-down unit can function as a stabilizing capacitor, so that the output is further improved. The effect is that it can be stabilized.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor step-down circuit according to a first embodiment of the present invention and a timing of a clock signal of the circuit.

2 is an equivalent circuit diagram of the step-down circuit in FIG. 1 during discharging and charging.

FIG. 3 is an equivalent circuit diagram at the time of charging and discharging of a step-down circuit for explaining the second embodiment of the present invention.

FIG. 4 is a block diagram of a semiconductor step-down circuit showing a third embodiment of the present invention.

FIG. 5 is a diagram showing a semiconductor voltage step-down circuit according to a fourth embodiment of the present invention and a timing of a clock signal of the circuit.

FIG. 6 is a semiconductor step-down circuit diagram showing a conventional example.

[Explanation of symbols]

Tr1 to Tr5 MOS transistors C1, C2, Cmn capacitor V _EXT external input voltage V _INT output voltage V _ref reference voltage 1a small capacity step-down unit 1b large capacity step-down unit 2 clock generation circuit 3 latch circuit 4 comparator 5a, 5b step-down unit

Claims (2)

[Claims] 1. m × n pieces (m <n, m, n having the same capacity
Is an integer), when charging, n sets are connected in series and m sets are connected in parallel to be charged by the input power supply, and when discharging, m sets are connected in series and n sets are output in parallel. By connecting and discharging, the input voltage m /
A semiconductor step-down circuit that outputs a voltage of n. 2. A first step-down unit composed of a capacitor having a large capacity and a second step-down unit composed of a capacitor having a small capacity are connected in parallel, and when the output load is light, the first step-down unit is connected.
By fixing the step-down part of the circuit to a discharging state to provide a stabilizing capacitance, the output is driven only by the second step-down part, and when the output load is heavy, the circuits of both the first and second step-down parts are driven. 2. The semiconductor step-down circuit according to claim 1, wherein the output is driven by.