JPH0628486A - Image processor - Google Patents

Abstract

PURPOSE:To curtail the number of program steps of the image processor such as a graphic processor, etc., and to enhance its processing capacity. CONSTITUTION:A graphic processor, etc., are provided with a thick line plotting mechanism containing a pattern memory PM for holding dot patterns of (i) rows x (j) columns prepared in accordance with various thick lines, a thick line coordinate generating part BLCG for deriving a center path between two points designated in accordance with a prescribed algorithm, and a pattern selector PS for referring to each dot of the dot pattern successively along the center path in accordance with row selecting signals A0-A4 outputted from an i-scale counter CTRA and column selecting signals B0-B4 outputted from a j-scale counter CTRB. In such a manner, by only designating a start point and an end point, and the kind of lines various thick in which the pattern in its line width direction is not constant can be plotted by a single command.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device,
For example, the present invention relates to a graphic processor and a technique that is particularly effective when used for thick line drawing.

[0002]

2. Description of the Related Art There is an image processing apparatus such as a graphic processor for efficiently creating and displaying figures and images. Further, as one means for efficiently performing thick line drawing by such a graphic processor or the like, there is known a thick line drawing method in which an aggregate of pixels called a pel is moved between two designated points.

A thick line drawing method using a pel is described in, for example, Japanese Patent Laid-Open No. 63-91787.

[0004]

In a conventional graphic processor or the like, various lines including a straight line are basically drawn with a line width of 1 dot as a unit. For this reason,
As illustrated in FIG. 14, the drawing of a thick line used in a map or the like and the pattern of which in the line width direction is not constant is represented by, for example, the start point (X
s, Ys) and the end point (Xe, Ye), a command for drawing a straight line as a central path, that is, DRWL1 SWL2 (Xs, Ys) * (Xe, Ye) and four parallel lines to this central path. A command for drawing a dotted line, that is, DRWL2 SWL3 (Xs, Ys-2) * (Xe, Y
e-2) DRWL2 SWL3 (Xs, Ys-1) * (Xe, Y
e-1) DRWL2 SWL3 (Xs, Ys + 1) * (Xe, Y
e + 1) DRWL2 SWL3 (Xs, Ys + 2) * (Xe, Y
e + 2) and That is, this method requires a number of commands corresponding to the number of dots in the line width direction to draw one thick line, which increases the number of steps of the graphic processor and reduces its processing capability.

In order to deal with this, it is conceivable to unify the commands by adopting the thick line drawing method by the pel as described above. However, this method
Since the pel's locus has a constant width, it is effective as a drawing method for a thick line in which the pattern in the line width direction is fixed. However, in the line width direction as illustrated in FIG. It is not suitable for drawing thick lines with irregular patterns.

An object of the present invention is to provide an image processing device such as a graphic processor having a new function. Another object of the present invention is to reduce the number of program steps of the image processing apparatus and improve its processing capability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, i lines prepared for an image processing device such as a graphic processor corresponding to various thick lines x
Each of the dot patterns is stored in accordance with a pattern memory that holds the j-th row dot pattern, a thick-line coordinate generation unit that obtains a central path between two points designated according to a predetermined algorithm, and an output signal of an i-ary and j-ary counter. A thick line drawing mechanism including a pattern selector that sequentially refers to the dots along the central path in the drawing direction and the line width direction is provided.

[0009]

According to the above means, it is possible to realize an image processing apparatus such as a graphic processor capable of drawing various thick lines whose patterns in the line width direction are not constant by a single command only by designating a start point, an end point and a line type. . As a result, the number of program steps of the image processing apparatus can be reduced and its processing capability can be increased.

[0010]

1 is a block diagram of an embodiment of a thick line drawing mechanism of a graphic processor to which the present invention is applied. First, the outline of the configuration and operation of the thick line drawing mechanism of the graphic processor of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are mounted on a common printed board together with other circuit elements forming the graphic processor.

In FIG. 1, the thick line drawing mechanism of this embodiment is not particularly limited, but has a thick line coordinate generator BLCG, a pattern memory PM and a pattern selector PS as its basic configuration. Of these, to the bold line coordinate generation unit BLCG, the start point (Xs, Ys) and the end point (Xe, Ye) of the bold line to be drawn are given from the software of the graphic processor, that is, the central processing unit (not shown),
The pattern memory PM has a thick line type SWL to be drawn.
Is given.

The bold line drawing mechanism is further provided with an i-ary or quinary counter CTRA (first counter) and a j-ary or 5 counter.
Progressive counter CTRB (second counter), image memory address generator GMAG and drawing color selector GMD
Equipped with S. Of these, the counters CTRA and CTRB
Is supplied with the internal control signals UA and UB for stepping from the thick line coordinate generation unit BLCG, and the count values thereof are decoded in the respective counters, and then the selection signals A0 to A4 for row selection and the columns. The selection signals B0 to B4 for selection are supplied to the pattern selector PS.

The thick line coordinate generator BLCG is not particularly limited, but is composed of a micro-program type sub-processor and has a start point (X) given according to a predetermined algorithm.
s, Ys) and the end point (Xe, Ye), and the internal control signals UA and UB are selectively formed in a predetermined combination to generate counters CTRA and CTRB.
Selectively step forward. As a result, the output signals of the counters CTRA and CTRB, that is, the row selection signals A0 to A4 and the column selection signals B0 to B4 are formed in a predetermined order,
As a result, the reference order of the dot patterns of the pattern selector PS is set. The center line of the thick line obtained by the thick line coordinate generation unit BLCG is sequentially output in dot units as the X coordinate CX and the Y coordinate CY, and transmitted to the image memory GM via the image memory address generation unit GMAG.
The algorithm for obtaining the central path of various thick lines can be arbitrarily changed by, for example, rewriting the microprogram stored in the memory in the thick line coordinate generation unit.

On the other hand, the pattern memory PM holds dot patterns of i rows × j columns, ie, 5 rows × 5 columns prepared corresponding to various thick lines, and these dot patterns are provided by the central processing unit. In accordance with the seed SWL, it is read in a pattern unit, that is, in a unit of 25 dots, and output to the pattern selector PS. The various thick line dot patterns held in the pattern memory PM can be arbitrarily added or modified by, for example, inputting a predetermined command from the keyboard of the graphic processor, and the size of the rows and columns can be changed. it can.

The pattern selector PS refers to the pattern latch PL of 5 rows × 5 columns that temporarily holds the dot pattern output from the pattern memory PM, and the dot pattern held by this pattern latch PL in dot units. And a large number of switches for extracting. These switches are row selection signals A0 to A4 and column selection signals B0 to B4 output from the counters CTRA and CTRB.
Then, the corresponding dot of the dot pattern is selectively extracted and transmitted as dot data DD to the drawing color selection unit GMDS. The specific configuration and operation of the pattern selector PS will be described in detail later.

The drawing color selection unit GMDS performs predetermined coloring processing on the dot data DD output from the pattern selector PS, forms pixel data, and outputs the pixel data to the image memory GM. These pixel data are stored in an address designated by the image memory address generation unit GMAG of the image memory GM, and then CR (not shown) in a predetermined order.
It is read out and displayed on the T (cathode ray tube) display.

FIG. 2 shows a circuit diagram of an embodiment of the pattern selector PS included in the thick line drawing mechanism of FIG. The specific configuration and operation of the pattern selector PS included in the thick line drawing mechanism of this embodiment will be described with reference to FIG.

In FIG. 2, the pattern selector PS of this embodiment is not particularly limited, but unit latch circuits UL00 to UL04 to UL40 to UL44 of 5 rows × 5 columns.
Pattern latch PL consisting of The input node of each unit latch circuit forming the pattern latch PL is coupled to the corresponding output terminal of the pattern memory PM via a signal path (not shown). In addition, five unit latch circuits UL00 to UL40 to U arranged in each column.
The output nodes of L04 to UL44 are the corresponding switches S
Commonly coupled to internal nodes D0 to D4 via A00 to SA40 to SA04 to SA44, respectively. The control gates of these switches are five in each row, that is, the switches SA00 to SA04 to SA40 to SA4.
4 are commonly coupled to each other and output signals from the counter CTRA, that is, row selection signals A0 to A.
4 are supplied respectively.

The pattern selector PS further includes five switches SB0 to SB4 provided between the internal nodes D0 to D4 and its output terminal DD. The output signals of the counter CTRB, that is, the column selection signals B0 to B4 are supplied to the control gates of these switches, respectively.

From these facts, the pattern latch P of the pattern selector PS read from the pattern memory PM is read.
The dot patterns held by L are first selected five by five according to the row selection signals A0 to A4 and output to the corresponding internal nodes D0 to D4. Then, the column selection signal B
Further, one by one is selected according to 0 to B4, and becomes the output signal of the pattern selector PS, that is, the dot data DD. As described above, these dot data DD are converted into predetermined pixel data by the drawing color selection unit GMDS, and then sequentially written in the image memory GM. When the number of dots in the row and column directions of the dot pattern can be arbitrarily set, it is necessary to increase the number of elements in the row and column directions of the pattern latch PL and the switch of the pattern selector PS in accordance with the maximum number. It goes without saying that there is.

FIG. 4 shows a pattern configuration diagram of an embodiment of a bold line dot pattern for private railway display used in the graphic processor of FIG. 1, and FIG. 5 shows thick line drawing coordinates and its coordinates in the graphic processor of FIG. The conceptual diagram of one Example for demonstrating a processing direction is shown. Further, FIGS. 6 and 7 show pattern configuration diagrams of one example of the private railway display thick line drawn in the coordinate Za direction and the coordinate Zb direction using the dot pattern of FIG. 4, and FIG. 1, a conceptual diagram of an embodiment for explaining a private line display thick line drawing command of the graphic processor of FIG. 1 is shown. Based on these figures, a concrete method of drawing thick lines by the graphic processor of this embodiment and its characteristics will be described. In the following pattern configuration diagram, each dot of the dot pattern is represented by a quadrangle. In addition, the dots of the logical "1" that should be displayed brightly on the CRT display are shaded,
The logical "0" dots that should be displayed dark are left blank.

In the graphic processor of this embodiment, the dot patterns prepared corresponding to the various thick lines are represented by the bold lines for private railway display in FIG.
It is composed of 25 dots that are combined in a grid pattern of 5 rows × 5 columns. These dot patterns are stored in the pattern memory PM of the thick line drawing mechanism and read out to the pattern latch PL in the pattern selector PS as needed. At this time, as shown in FIG. 5, the correspondence between the row or drawing direction and the column or line width direction of each dot pattern and the X-axis and Y-axis that is assumed for image processing is such that the moving direction of the thick line is the coordinate. It is selectively set depending on which of Za to Zh.

That is, the traveling direction of the thick line is the coordinate Z in FIG.
If it is a, the line of the dot pattern, that is, the drawing direction is +
It is set in the X direction, and its column, that is, the line width direction is set in the + Y direction. When the traveling direction of the thick line is at the coordinate Zb, the drawing direction of the dot pattern is the + Y direction, and the line width direction thereof is set to the + X direction. Furthermore, when the traveling direction of the thick line is at the coordinates Zc and Zd, the drawing directions of the dot patterns are set to the + Y direction and the −X direction, respectively.
The line width directions are set to the −X direction and the + Y direction, respectively. The traveling direction of the thick line is coordinates Ze, Zf, Zg.
, And Zh, the drawing directions of the dot patterns are set to −X direction, −Y direction, −Y direction, and + X direction, respectively, and the line width directions thereof are −Y direction, −X direction, + X direction, and −Y direction, respectively. Set to the direction. As will be described later, the address calculation of the image memory GM based on the central path obtained by the thick line coordinate generator BLCG and the count values of the counters CTRA and CTRB is selectively performed according to the above correspondence.

Here, the bold line for private railway display is the starting point (Xs, Y
s), that is, (0, 2) to the end point (Xe, Ye), that is, (19, 8) is drawn as an example, the thick line drawing method by the graphic processor of this embodiment will be specifically described. To do.

In the thick line coordinate generation unit BLCG of the thick line drawing mechanism, prior to the start of the drawing process, the starting point (0, 2) and the ending point (19, 8) of the bold line for private railway display from the central processing unit.
Is given to the pattern memory PM, and the line type SWL1 indicating the private railway display thick line is given. In response to this, the dot pattern of FIG. 4 corresponding to the private railway display thick line is read from the pattern memory PM and sent to the pattern latch PL of the pattern selector PS. In addition, the bold line coordinate generation unit B
In LCG, the start point (0,
2) and the central path connecting the end points (19, 8) are obtained, the initial values of the counters CTRA and CTRB are both set to 0, and the corresponding address of the image memory GM is designated and the X coordinate CX of 0 and The Y coordinate CY is output to the image memory address generation unit GMAG. Further, the initial values of the counters CTRA and CTRB are both 0.
Is set to, the row selection signals A0 to A4 and the column selection signals B0 to B4 supplied to the pattern selector PS.
Among them, only the corresponding row selection signal A0 and column selection signal B0 are alternatively set to the high level. In addition, the thick line coordinate generation unit BLCG calculates the center route of the bold line for private railway display,
It is identified that the traveling direction of the bold line for private railway display corresponds to the coordinate Za in FIG.

In the pattern selector PS, the row selection signal A
By selectively setting 0 to the high level, the corresponding five switches SA00 to SA04 are simultaneously turned on, and the holding patterns of the unit latch circuits UL00 to UL04 are output to the corresponding internal nodes D0 to D4. It Also,
Since the column selection signal B0 is alternatively set to the high level,
First, the unit latch circuit UL0 output to the internal node D0
The holding pattern of 0, that is, the logic "0" is alternatively selected and sent to the drawing color selection unit GMDS as the dot data DD. Further, the internal control signal UB is formed four times at a predetermined interval, and the count value of the counter CTRB is 1 to 4
Step by step. Accordingly, the internal node D1
To unit latch circuits UL01 to UL04 output to D4
Holding patterns, that is, the logics "0", "1", "0" and "0" are sequentially and selectively selected and sent as dot data DD to the drawing color selection unit GMDS. At this time, the X coordinate CX for designating the address of the image memory GM is 0.
The Y coordinate CY is kept as it is and is sequentially updated to add the count value of the counter CTRB.

Thereafter, the count value of the counter CTRB is returned to the initial value 0, the internal control signal UA is formed only once, and the count value of the counter CTRA is updated to 1. Therefore, the holding patterns of the unit latch circuits UL10 to UL14, that is, the logic "00100" are sequentially and selectively selected, and the drawing color selection unit GM is selected as the dot data DD.
Sent to DS. At this time, the X coordinate CX for designating the address of the image memory GM is updated to 1 and the Y coordinate CX is updated.
Y is also sequentially updated to add the count value of the counter CTRB. Next, when the count value of the counter CTRB is returned to the initial value 0 again and the count value of the counter CTRA is updated to 2, the holding pattern of the unit latch circuits UL20 to UL24, that is, the logic "11111" is sequentially and alternately selected. It is selected and sent as dot data DD to the drawing color selection unit GMDS. At this time, the X coordinate CX for designating the address of the image memory GM is updated to 2, but the Y coordinate CY.
Is updated by adding (1) to the count value of the counter CTRB because the coordinates of the central route of the bold line for private railway display are updated to (2, 3).

Thereafter, the same processing is repeated in units of dot patterns, and the dot patterns held by the unit latch circuits UL00 to UL04 to UL40 to UL44 of the pattern latch PL are sequentially and alternately selected for each dot, and the dot pattern is selected. Drawing color selection unit GM as data DD
Sequentially sent to DS. Along with this, the X coordinate CX and the Y coordinate CY for designating the address of the image memory GM are the coordinates of the central route and the counters CTRA and CT.
It is sequentially updated according to the count value of RB. Then, as a result of the above processing being repeated for five dot patterns, the private railway display thick line connecting the start point (0, 2) and the end point (19, 8) is autonomous without the intervention of the central processing unit. Is drawn to. In other words, the thick line drawing process, when viewed from the central processing unit, is the starting point (Xs, Y) of the private line display thick line as illustrated in FIG.
s) A single command for giving (0, 2) and end point (Xe, Ye), that is (19, 8), and a line type SWL, that is, SWL1 indicating a private railway thick line, that is, DRWL SWL1 It starts and ends only by issuing (Xs, Ys) * (Xe, Ye). As a result, the number of program steps of the graphic processor is reduced and its processing capacity is correspondingly increased. The effect of the present invention becomes more remarkable as the line width of the thick line becomes larger. Further, in the conventional thick line drawing method, a large number of commands must be issued when enlarging / reducing a figure, but in the case of the present invention, only the coordinates of the start point and the end point need to be changed, which is extremely efficient. Will be things.

Next, in the case of FIG. 7 in which a private railway display thick line is drawn from the starting point (2,0) to the ending point (8,19),
The traveling direction of the bold line for private railway display corresponds to the coordinate Zb in FIG. 5, the drawing direction is + Y direction, and the line width direction is + X direction. When the drawing process is started, the thick line drawing mechanism first reads the dot pattern of FIG. 4 corresponding to the bold line for private railway display from the pattern memory PM and sends it to the pattern latch PL of the pattern selector PS. Also,
In the bold line coordinate generator BLCG, a central route connecting the start point (2,0) and the end point (8,19) is obtained, and
The initial values of the counters CTRA and CTRB are both set to 0. As a result, the image memory address generator GM
X coordinate CX and Y coordinate CY of 0 are both given to AG, and row selection signal A0 and column selection signal B0 are given.
Are alternately set to the high level, and the dot pattern reference / extraction processing is started.

Thereafter, the same processing as in the case of FIG. 6 is repeated for each dot pattern, the dot patterns held by the pattern latch PL are sequentially and selectively selected for each dot, and the drawing color is selected as the dot data DD. Part G
Sent to MDS. In accordance therewith, the X coordinate CX for designating the address of the image memory GM, the Y coordinate CY according to the coordinate of the central route and the count value of the counter CTRB, and the coordinate of the central route and the counter CTRA.
Are sequentially updated according to the count value of. And
As a result of the above processing being repeated for five dot patterns, a private railway display thick line connecting the start point (2,0) and the end point (8,19) is drawn autonomously without the intervention of the central processing unit. Will be done.

FIG. 10 shows a pattern configuration diagram of another embodiment of the private railway display thick line dot pattern used in the graphic processor of FIG. Further, FIG. 11 shows a pattern configuration diagram of an embodiment of a private railway display thick line drawn in parallel with the X axis by the dot pattern of FIG. 10, and FIGS. 12 and 13 show the X axis and 0 degrees. A pattern configuration diagram of an example of a private railway display thick line drawn at an angle of near and 45 degrees is shown, respectively. With reference to these figures, another embodiment of the dot pattern used in the graphic processor of FIG. 1 and its application will be described. It should be noted that this embodiment basically follows the embodiment of FIGS. 4 to 8, and therefore only the portions different from this will be described.

In FIG. 10, the dot patterns corresponding to the bold lines for private railway display are not particularly limited, but three types are prepared corresponding to the drawing direction. That is, in the dot pattern shown in (a) of FIG. 10, as illustrated in FIG. 11, the drawing direction of the bold line for private railway display is parallel to the X axis or the Y axis, or intermediate to the X axis or the Y axis. It is commonly used when making an angle. However, the dot pattern shown in (b) of FIG. 10 is effective when the drawing direction of the bold line for private railway display makes an angle near 0 degrees with the X axis, as illustrated in FIG. In the dot pattern shown in 10 (c), as shown in FIG. 13, the drawing direction of the private railway display thick line is the X axis, that is, Y.
It is effective when forming an angle of about 45 degrees with the axis.

As described above, by preparing a plurality of various thick line dot patterns corresponding to the drawing direction, distortion of the thick line due to the drawing direction can be suppressed, and clear and clear thick line drawing can be realized. Becomes The selection of the dot pattern corresponding to the drawing direction may be performed autonomously by the bold line drawing mechanism, or may be performed subordinately by an instruction from the outside.

By applying the present invention to an image processing device such as a graphic processor and its thick line drawing as shown in the above-described embodiments, the following operational effects can be obtained. That is, (1) a pattern memory for holding an i-row × j-column dot pattern prepared corresponding to various thick lines in an image processing device such as a graphic processor, and a center between two points designated according to a predetermined algorithm. A thick line drawing mechanism including a thick line coordinate generation unit for obtaining a path and a pattern selector for sequentially referring to each dot of the dot pattern in the drawing direction and the line width direction along the central path according to the output signals of the i-adic and j-adic counters. By providing the above, it is possible to obtain the effect that various thick lines whose patterns in the line width direction are not constant can be drawn by a single command only by specifying the start point, the end point, and the line type. (2) According to the above item (1), it is possible to effectively enlarge or reduce a graphic including a thick line by simply changing the coordinates of the start point and the end point. (3) In the above items (1) and (2), by preparing a plurality of types of dot patterns corresponding to the drawing directions of various thick lines, distortion of the thick lines due to the drawing direction is suppressed, and clear and clear thick lines are displayed. The effect of being able to draw is obtained. (4) According to the above items (1) to (3), it is possible to reduce the number of program steps of an image processing apparatus such as a graphic processor and improve the processing capability while improving the image quality of a drawn thick line. Is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the bold line coordinate generation unit BLCG may use a processor of a stored program method, or may perform all drawing processing by hardware. The pattern selector PS, as shown in FIG.
J shift registers SR10 to SR that receive i bits, that is, 5 bits in the drawing direction of the dot pattern, that is, 5 shift registers
14 (first shift register) and one j-bit, that is, 5-bit shift register SR2 (second shift register) that receives the output signals R0 to R4 of these shift registers in parallel and shifts in the line width direction. And can be basically configured.

Here, the shift registers SR10 to SR1
4 is a corresponding output signal MC00 of the pattern memory PM
~ MC40 to MC04 to MC44 are controlled by internal control signal D
The data is fetched in parallel according to L1, and the held data is shifted bit by bit in the drawing direction according to the internal control signal DS1. The shift register SR2 takes in the output signals R0 to R4 of the shift registers SR10 to SR14 in parallel according to the internal control signal DL2, shifts the held data in the line width direction bit by bit according to the internal control signal DS2, and outputs the dot data. Output as DD. When this method is adopted, the shift registers SR10 to SR14
In addition, although the line width repetition period is restricted by the number of bits of SR2, there is an advantage that the amount of hardware can be reduced as compared with the case of FIG. 2 using a counter and a large number of switches.

In the dot patterns shown in FIGS. 4 and 10, the number of dots in the row and column directions can be set arbitrarily, and the pattern is also arbitrary. Further, in FIG. 10, the prepared dot patterns are limited to three types,
A larger number of dot patterns can be prepared corresponding to various thick line drawing directions. In this embodiment, each dot of the dot pattern is associated with 1 bit, and the coloring process is performed by the drawing color selection unit GMDS based on the selected dot data DD. However, each dot has an n-bit configuration and is selected. It is possible to selectively perform 2 n-th power type coloring processing by the generated n-bit dot data. If each dot of the dot pattern has the same number of bits as the dot data input to the image memory GM, the drawing color selection unit GMDS can be omitted. The reference of the dot pattern in the pattern selector PS can be made not only in units of 1 dot but also in units of 5 dots in the line width direction, for example. The direction of the thick line drawing process can be advanced from the end point to the start point, or can be zigzag in a single dot pattern by reciprocating in the line width direction.

The thick line subjected to the drawing processing by the thick line drawing mechanism of this embodiment may have a constant pattern in the line width direction, or may be an arbitrary curve. In this case, similar drawing processing may be performed assuming a tangent line at each point of interest on the curve. The drawing processing by the thick line drawing mechanism may be partially implemented by software by the central processing unit. Further, various embodiments such as the block configuration of the thick line drawing mechanism shown in FIG. 1, the specific configuration of the pattern selector PS shown in FIGS. 2 and 3 and the procedure and command format of the drawing process by the thick line drawing mechanism can be adopted. .

In the above description, the case where the invention made by the present inventor is mainly applied to the graphic processor which is the background field of application has been described. However, the present invention is not limited to this and, for example, an image processing function. It can also be applied to a word processor or workstation having a. The present invention can be widely applied to an image processing apparatus that has at least an image processing function and draws a thick line.

[0040]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an image processing device such as a graphic processor, a pattern memory for holding dot patterns of i rows × j columns prepared corresponding to various thick lines,
A thick line coordinate generation unit that finds a central path between two points specified according to a predetermined algorithm, and a drawing direction and a line width direction of each dot of the dot pattern along the central path according to the output signals of the i-adic and j-adic counters. By providing a thick line drawing mechanism including a pattern selector that sequentially refers to
It is possible to realize an image processing device such as a graphic processor that can draw various thick lines whose patterns in the line width direction are not constant by a single command only by designating a start point, an end point, and a line type. As a result, the number of program steps of the image processing apparatus can be reduced and its processing capability can be increased.

[Brief description of drawings]

FIG. 1 is a partial block diagram showing an embodiment of a thick line drawing mechanism of a graphic processor to which the present invention is applied.

FIG. 2 is a circuit diagram showing a first embodiment of a pattern selector included in the thick line drawing mechanism of FIG.

3 is a circuit diagram showing a second embodiment of the pattern selector included in the thick line drawing mechanism of FIG.

FIG. 4 is a pattern configuration diagram showing a first embodiment of a private railway display thick line dot pattern used in the graphic processor of FIG. 1;

5 is a conceptual diagram showing an example of bold line drawing coordinates and a processing direction thereof in the graphic processor of FIG.

6 is a pattern configuration diagram showing an example of a private railway display thick line drawn in the coordinate Za direction using the dot pattern of FIG. 4. FIG.

7 is a pattern configuration diagram showing an example of a private railway display thick line drawn in the coordinate Zb direction using the dot pattern of FIG.

8 is a conceptual diagram showing an example of a private line display thick line drawing command in the graphic processor of FIG. 1;

FIG. 9 is a conceptual diagram showing an example of a private line display thick line drawing command in a graphic processor developed by the inventors of the present application prior to the present invention.

10 is a pattern configuration diagram showing a second embodiment of a private railway display thick line dot pattern used in the graphic processor of FIG. 1;

11 is a pattern configuration diagram showing one example of a private railway display thick line drawn in a direction parallel to the X axis using the dot pattern of FIG.

12 is a pattern configuration diagram showing an example of a private railway display thick line drawn in the direction near 0 degrees with respect to the X axis using the dot pattern of FIG.

FIG. 13 is a pattern configuration diagram showing an embodiment of a private railway display thick line drawn in the direction near 45 degrees with respect to the X axis using the dot pattern of FIG.

14 is a symbol diagram showing an example of thick lines on a map to which the thick line drawing method of the graphic processor of FIG. 1 can be applied.

[Explanation of symbols]

BLCG ... Thick line coordinate generator, CTRA, CTRB
..Counter, GMAG ... Image memory address generation unit, PM ... Pattern memory, PS ... Pattern selector, GMDS ... Drawing color selection unit, GM ... Image memory PL: Pattern latch, UL00 to UL0
4 to UL40 to UL44 ... Unit latch circuit, S
A00 to SA04 to SA40 to SA44, SB0
SB4 ... Switch. SR10 to SR14, SR2
..Shift registers

Claims (9)

[Claims] 1. An image processing apparatus, characterized in that at least a predetermined thick line whose pattern in the line width direction is not constant can be drawn by a single command. 2. The image processing apparatus obtains a pattern memory for holding dot patterns of i rows × j columns prepared corresponding to various thick lines, and a central path between two points designated according to a predetermined algorithm. The image processing apparatus according to claim 1, further comprising a thick line drawing mechanism including a thick line coordinate generation unit and a pattern selector that refers to the dot pattern along the central path. 3. The image processing apparatus according to claim 2, wherein the content of the dot pattern can be rewritten from the outside. 4. The pattern selector refers to the dot pattern in dot units along the center path, and draws such dot pattern reference j times in a thick line width direction. The image processing apparatus according to claim 2 or 3, wherein the image processing apparatus repeats i times each in a direction. 5. The pattern selector includes j first shift registers of i bits for receiving i dots in the drawing direction of the dot pattern and shifting them in a loop, and j
5. A single j-bit second shift register that receives the output signals of the first shift registers in parallel and shifts in the line width direction is included.
Image processing device. 6. The thick line drawing mechanism comprises an i-ary first counter for sequentially specifying each dot of the dot pattern in the drawing direction, and a j-ary for sequentially specifying each dot of the dot pattern in the line width direction. The image processing apparatus according to claim 5, further comprising a second counter. 7. The image processing apparatus according to claim 6, wherein the initial values and the stepping cycles of the first and second counters can be set from the outside. 8. The image processing apparatus according to claim 6, wherein the reference order of each dot of the dot pattern is selectively switched according to a drawing direction of a thick line. 9. The dot pattern according to claim 2, wherein a plurality of types are prepared in correspondence with the drawing directions of various thick lines.
The image processing apparatus according to claim 6, claim 7, or claim 8.