JPH06284009A - Analog-to-digital converting circuit - Google Patents

Abstract

PURPOSE:To obtain an A/D converting circuit which can greatly be improved in resolution. CONSTITUTION:Low-order comparators 101-108 corresponding to respective columns of a switching block are composed of comparators CN1 whose gains are N and comparators Cn1 and Cn2 whose gains are n1 (or n2), and the outputs of the comparators Cn1 and Cn2 are connected to comparators Cn1 and Cn2 corresponding to adjacent columns or columns skipping one column to constitute a ring comparator. Then differential outputs of the switching block are compared by a comparing circuit in interpolative structure of two connected low- order comparators CN1 and comparators Cn1 themselves or Cn1 and Cn2 to obtain an interpolative output, and the left side or right side of the ring comparator is disconnected according to the outputs of high-order comparators 21 and 23. Further, this circuit is provided with inhibiting circuits 121 and 122 which inhibit the output of an unnecessary interpolating circuit from being inputted to a low order encoder 140.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital (hereinafter referred to as A / D) for converting an analog signal into a digital signal.
More specifically, the present invention relates to a serial-parallel A / D conversion circuit that converts an analog signal into a digital signal in two steps, an upper level and a lower level.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a configuration example of a conventional A / D conversion circuit, showing a circuit configuration for converting an analog signal V _IN into a 4-bit digital code. In FIG. 6, 10 is a matrix circuit, 21 to 23 are upper comparators, 30 is an upper encoder, 41 to 48 are lower comparators, 51 and 52 are output gates, 60 is a lower encoder, 70 is a selection gate, and 80 is an inverter. Shows.

The matrix circuit 10 has 20 switches.
Block S₁₂, S₁₄, S₁₆, S ₁₈, S_{twenty one}, S_{twenty three}, S
_{twenty five}, S₂₇, S₃₂, S₃₄, S₃₆, S₃₈, S₄₁, S₄₃，
S₄₅, S ₄₇And S₅₂, S₅₄, S₅₆, S₅₈Is the left column in the figure
To 2 on odd and 3 on even
A so-called staggered 5x8 matrix with locks arranged
It is arranged in a box shape. The specific array is
Switching block S₁₂, S₁₄, S₁₆, S₁₈Is the top
The switching block S_{twenty one}, S_{twenty three}, S_{twenty five}, S₂₇Is next
Switching block S ₃₂, S₃₄, S₃₆, S₃₈But
The switching block S is at the lower stage.₄₁, S₄₃, S₄₅，
S₄₇Is placed further below the switching block.
Ku S₅₂, S₅₄, S₅₆, S ₅₈Is placed at the bottom, from below
The switching blocks arranged on the second and fourth lines
Click S₄₁, S₄₃, S₄₅, S₄₇And S_{twenty one}, S_{twenty three}, S_{twenty five}，
S₂₇To form the first, third, fifth and seventh columns.
Are placed on the 1st, 3rd and 5th lines.
Itching block S₅₂, S₅₄, S₅₆, S₅₈, S₃₂, S
₃₄, S₃₆, S₃₈And S₁₂, S₁₄, S₁₆, S₁₈In pairs
Thus, the second, fourth, sixth and eighth columns are formed.

Switching block S₁₂, S₁₄And
Itching block S₅₄, S₅₆, S ₅₈Each switch except
Block S₁₆, S₁₈, S_{twenty one}, S_{twenty three}, S_{twenty five}, S₂₇, S
₃₂, S₃₄, S₃₆, S₃₈, S₄₁, S₄₃, S₄₅, S₄₇and
S₅₂Is an npn transistor Q₁, Q₂And Q₃Or
It is composed of a differential type amplifier. In addition,
Itching block S₁₂, S₁₄, S₅₄, S₅₆And S₅₈
Is a transistor Q forming a so-called differential pair₁And Q₂
Is omitted, and the lower level comparator is directly controlled by the control signal.
Provide even-numbered columns of "H" and "L" level signals to the
Is configured to feed. This allows the matrix
The wiring of the circuit 10 is simplified.

Each switching block S ₁₆ , S ₁₈ , S ₂₁ , S ₂₃ , S ₂₅ having differential pair transistors Q ₁ , Q ₂
S ₂₇ , S ₃₂ , S ₃₄ , S ₃₆ , S ₃₈ , S ₄₁ , S ₄₃ , S ₄₅ , S
₄₇ and one reference voltage e ₁ to e ₁₅ to the base of the transistor Q ₁ is obtained by dividing the reference voltage V _RT -V _RB in reference resistance element R ₁ to R ₁₆ of the S ₅₂ is supplied, the other transistor Q _An analog signal V _IN to be converted into a digital code is supplied to each of the bases of ₂ . Moreover, emitters of the transistors Q ₁ and Q ₂ are connected, to the connection midpoint gate OR _U1 ~OR _U5 output control signal x ₁ ~x each current source through the transistor Q ₃ to be switched by ₅ I of It is connected. The power supply voltage V _DD is supplied to the collectors of the transistors Q ₁ and Q ₂ via a resistance element r, and the outputs thereof are input to the comparators C _{D1 to} C _D8 of the eight lower comparators 41 to 48, respectively. It also serves as the first stage amplifier of 41 to 48.

The reference resistance elements R _{1 to} R ₁₆ are connected in series between the two reference potentials V _RT and V _RB, and extend over 5 rows so as to correspond to the matrix arrangement of the switching blocks in the matrix circuit 10. It is folded back and arranged. Specifically, in the first row and the fifth row from the bottom in the figure, two resistance elements R ₁₆ , R ₁₅ and R ₂ ,
R ₁ is connected in series, and resistive elements R _{14 to} R ₁₁ , R _{10 to} R ₇ and R _{6 to} R ₃ are connected in series in the second to fourth rows, respectively. That is, the minimum position of the reference voltage (the connection point between the reference potential V _RB terminal and the resistance element R ₁₆ ) and the maximum position (the connection point between the reference potential V _RT terminal and the resistance element R ₁ ) are in the matrix. So that it is located at the midpoint in the row direction of the switching blocks arranged in a
The resistance columns of the first and fifth rows are arranged with a shift of a half cycle from the resistance columns of the second to fourth rows.

Three high-order comparators 21, 22, 23
_Are comparators C _{U1 to} C _U3 and an AND gate A _{U1 respectively.}
~ A _U4 is equipped. An analog signal V _IN is supplied to one input of each of the comparators C _{U1 to} C _U3 of the upper comparators 21 to 23, and a reference voltage obtained by dividing the reference potentials V _{RT to} V _RB by coarse quantization is supplied to the other input. V ₁ (= e ₄ ), V ₂ (=
e ₈ ) and V ₃ (= e ₁₂ ) are supplied. The output of each of the comparators C _{U1 to} C _U3 of the upper comparators 21 to 23 becomes “H” or “L” level corresponding to the level of the sampled analog signal, and any one of the AND gates A _{U1 to} A _U4 . Only one is configured to output a "1" level.

The outputs of the AND gates A _{U1 to} A _U3 of the upper comparators 21 to 23 are wired-connected to the three encode lines LN _{31 to} LM ₃₃ of the upper encoder 30. At this time, the upper encoder 30 generates the upper 1-bit conversion code data corresponding to the output levels of the AND gates A _{U1 to} A _{U3 on} the three encode lines LN _{31 to} LM ₃₃ . FIG. 7 shows conversion code pattern examples of the upper comparator output and the upper encoder, respectively.

The outputs of the AND gates A _U1 and A _U3 of the upper comparators 21 and 23 are the output gates 5 on the lower side.
2 2-input OR gate OR _{2 and} 2-input OR gate O
It is connected to one input of R _{D1 as well} as to one input of the OR gate OR ₁ of the output gate 51 and one input of the two-input OR gate OR _D1 via the inverter 80.

Further, AND gate A_U1Output is 2 inputs
OR gate OR_U1Both inputs and 2 inputs OR gate OR
_U2Connected to one input. OR gate OR_U1of
Output is control signal x₁As a switching block
Ku S₁₂, S₁₄, S₁₆, S₁₈Transistor Q₃Base of
Or gate OR_U2Is the control signal
Issue x₂As a switching block S_{twenty one}, S_{twenty three}, S _{twenty five}，
S₂₇Transistor Q₃Supplied to the base of. But
The AND gate A of the upper comparator 21_U1Output
Becomes "1" level (V₁<V_IN<
V_RT), The switching block S in the fifth row from the bottom₁₂，
S₁₄, S₁₆, S₁₈And the switching block S in the 4th row
_{twenty one}, S_{twenty three}, S_{twenty five}, S₂₇And are activated.

AND gate A _{U2 of the} upper comparator 22
Is the other input of the 2-input OR gate OR _U2 and 2
It is connected to one input of the input OR gate OR _U3 .
The output of the OR gate OR _U2 is used as the control signal x ₂ as described above for the switching blocks S ₂₁ , S ₂₃ ,
Is supplied to the base of the transistor Q ₃ of S _25, S _27, the output of the OR gate OR _U3 switching block S ₃₂ as the control signal _{x 3, S 34, S 36} , is supplied to the base of the transistor Q ₃ of S _38. Therefore, when the output of the AND gate A _U2 of the high-order comparator 22 becomes the “1” level (V ₂ <V _IN <V ₁ ), the switching blocks S ₂₁ , S ₂₃ , S of the fourth row from the bottom are shown. ₂₅ , S ₂₇ and the switching blocks S ₃₂ , S ₃₄ , S ₃₆ , S _{38 of} the third row.
Is activated.

AND gate A of upper comparator 23_U3
Output is a 2-input OR gate OR_U3The other input of and 2
Input OR gate OR_U4Connected to one input.
OR gate OR_U3Output is controlled as described above
Signal x₃As a switching block S₃₂, S₃₄，
S₃₆, S₃₈Transistor Q₃Is supplied to the base of
Agate OR_U4Is the control signal x_FourAs
Itching block S₄₁, S₄₂, S₄₃, S₄₄The transition
Star Q₃Supplied to the base of. Therefore, Andge
Card A_U3If the output of becomes "1" level (V₃
<V_IN<V₂), The switching block on the third row from the bottom
Ku S₃₂, S₃₄, S₃₆, S ₂₈And the switching line on the second line
Lock S₄₁, S₄₃, S₄₅, S₄₇Is activated.

AND gate A_U4Output is a 2-input oag
OR_U4Other input and two-input OR gate OR_U5of
Connected to both inputs. OR gate OR_U4Output is above
As mentioned above, the control signal x_FourSwitching as
Block S₄₁, S₄₃, S₄₅, S₅₇Transistor Q₃of
OR gate OR supplied to the base_U5Output is
Signal x_FiveAs a switching block S₅₂, S₅₄，
S₅₆, S₅₈Transistor Q₃Supplied to the base of.
Therefore, AND gate A_U4Output is "1" level
If it becomes (V_RB<V_IN<V₃), Second row from the bottom
Switching block S₄₁, S₄₃, S₄₅, S ₄₇And the first
Switching block S on the line₅₂, S₅₄, S₅₆, S₅₈But
Activated.

[0014] lower comparator 41 to 48 are respectively provided with comparators C _D1 -C _D8 and the AND gate A _D1 to A _D8, each column of the matrix circuit 10 to the second input of each comparator C _D1 -C _D8 The collector output of the transistor Q ₁ and the collector output (differential output) of the transistor Q ₂ of the selected switching block are supplied.

The positive side output of the comparator C _D1 of the lower comparator 41 is connected to one input of a 2-input AND gate A _{D1 and} the other input of the OR gate OR ₁ of the output gate 51, and the negative side output thereof is a 2-input OR gate OR. Connected to the other input of _D1 . The output of the OR gate OR _D1 is connected to one input of the AND gate A _D2 of the lower comparator 42.

Comparator C of the lower comparator 42_D2The positive side of
Output is 2 input AND gate A_D2Connected to the other input of
The negative output is the 2-input AND gate of the lower comparator 44.
Card A _D4Connected to one input. Lower Compale
Comparator C of data 43_D3The positive side output is a 2-input AND gate
A_D3Connected to one input and the negative output is the lower comparator.
2-input AND gate A of the data 41 _D1Connect to the other input of
Has been done. Comparator C of the lower comparator 44_D4The positive side of
Output is 2 input AND gate A_D4Connected to the other input of
The negative output is the 2-input AND gate of the lower comparator 46.
Card A _D6Connected to one input. Lower Compale
Comparator C of the data 45_D5The positive side output is a 2-input AND gate
A_D5Connected to one input and the negative output is the lower comparator.
2-input AND gate A of data 43 _D3Connect to the other input of
Has been done. Comparator C of the lower comparator 46_D6The positive side of
Output is 2 input AND gate A_D6Connected to one input
The negative output is the 2-input AND gate of the lower comparator 48.
Card A _D8Connected to one input. Lower Compale
Comparator C of data 47_D7The positive side output is a 2-input AND gate
A_D7Connected to one input and the negative output is the lower comparator.
2-input AND gate A of the data 45 _D5Connect to the other input of
Has been done.

The positive side output of the comparator C _D8 of the lower comparator 48 is connected to the other input of the two-input AND gate A _{D8 and} the other input of the two-input OR gate OR ₂ of the output gate 52, and the negative side output is two inputs. It is connected to one input of the OR gate OR _D2 . The output of the OR gate OR _D2 is connected to the other input of the AND gate A _D7 of the lower comparator 47.

The lower comparator 4 having the above structure
1 to 48 form a so-called ring comparator, and the outputs of the comparators C _{D1 to} C _D8 become “H” or “L” levels corresponding to the levels of two inputs, and the AND gates A _{D1 to} A D. Only one of _D8 outputs active "1" level. Lower comparator 41-48
The output of AND gates A _{D1 to} A _D8 of the lower encoder 60
Wired to. Also, the output gates 51 and 52
The outputs of the OR gates OR ₁ and OR ₂ are inverted by inverters I ₁ and I ₂ , respectively, and their outputs are similarly wired-connected to the lower encoder 60.

The lower encoder 60 is a data line LN which generates lower conversion code data D ₂ , D ₃ and D _4.
61 , lower comparators 46 and 48, and output gate 5
Any one of the outputs of the selection line LN ₆₂ for generating the selection signal SEL ₁ indicating that any one of the outputs of 2 has become “1”, the lower comparators 41, 43, 45, 47 and the output gate 51. Selection signal S indicating that
It is composed of a selection line LN ₆₃ for generating EL ₂ and a selection line LN ₆₄ for generating a selection signal SEL ₃ indicating that one of the outputs of the lower comparators 42 and 44 has become “1”.

The selection gate 70 is composed of AND gates A ₁ -A.
₃ and uses the selection signals SEL ₁ , SEL ₂ and SEL ₃ output from the lower encoder 60,
One upper data is selected from the three types of uppermost data output from the upper encoder 30, and the OR gate OR is selected.
Output as conversion code D ₁ via ₁ .

In such a configuration, for example, when the sampling voltage V _s of the sampled analog signal is V _RB <V _S <V ₃ (= e ₁₂ ), the comparators C _U1 to The output of C _U3 becomes “L”, and binary signals of “0” are output from the AND gates A _{U1 to} A _U3 and “1” is output from A _U4 . as a result,

The binary signal [000] is input to the upper encoder 30 via the buffers B _{U1 to} B _U3 . Upper encoder 30
Then, three rows of encoder lines [LN ₃₁ ] to [LN ₃₁ ] to [LN] that generate predetermined data by a so-called wired OR circuit
N ₃₃ ]

The upper data of [000] is generated and output to the selection gate 70.

Further, the sampling voltage V _s is V ₃ <V _S
If <V ₂ (= e ₈ ), the upper comparators 21 and 2
The outputs of the two comparators C _U1 and C _U2 are “L”, the outputs of the comparator C _U3 of the upper comparator 23 are “H”, and the AND gates A _U1 , A _U2 and A _{U4 of the} upper comparators 21 and 22.
"0" from the AND gate A of the upper comparator 23
_A binary signal of "1" is output from _U3 . As a result, the binary signal [001] is input to the upper encoder 30 via the buffers B _{U1 to} B _U3 . In the upper encoder 30, encoder lines [LN ₃₁ ] to [LN ₃₃ ]
The upper data of [001] is generated in the
Is output to.

Further, the sampling voltage V _s is V ₂ <V _S
If <V ₁ (= e ₄ ), the output of the comparator C _U1 of the upper comparator 21 is “L”, and the upper comparators 22 and 23 are
The outputs of the comparators C _U2 and C _U3 of the above become “H”, and the AND gates A _U1 , A _U3 and A _{U4 of the} upper comparators 21 and 23.
From "0", AND gate A of upper comparator 22
_U2 outputs binary signals of "1". As a result, the binary signal [010] is input to the upper encoder 30 via the buffers B _{U1 to} B _U3 . In the upper encoder 30, encoder lines [LN ₃₁ ] to [LN ₃₃ ]
The upper data of [011] is generated in the
Is output to.

Further, the sampling voltage V _s is V ₁ <V _S
If V _RT , the outputs of the comparators C _{U1 to} C _U3 of the upper comparators 21 to 23 become “H”, and the upper comparator 2
Binary signals of "0" are output from the AND gates A _U2 , A _U3 and A _{U4 of 2} , 23, and "1" from the AND gate A _U1 of the upper comparator 21. as a result,
The binary signal [100] is input to the upper encoder 30 via the buffers B _{U1 to} B _U3 . Upper encoder 30
Then, in encoder lines [LN ₃₁ ] to [LN ₃₃ ], [1
10] is generated and output to the selection gate 70.

In parallel with this, each AND gate A
_{U (1, 2, 3, 4)} control line binary output signal in is "1" _{(x 1, x 2, x} 3, x 4, x 5) to the connected matrix circuit The transistor Q ₃ of each of the 10 switching blocks is turned on in units of two rows, and the quantization level is finely digitized.

For example, AND gate A_U3Output of
At the "1" level, the switch on the second line from the bottom in the figure
Block S₄₁, S₄₃, S₄₅, S₄₇, And next to this
Switching block S on the third row that touches₃₂, S₃₄, S
₃₆, S₃₈Each transistor Q ₃Turns on and the reference resistance
R₇~ R₁₆Reference voltage e divided by₇~ E₁₅And sample
Voltage V_SBut each switching block S₄₁, S₄₃，
S₄₅, S₄₇And S₃₂, S₃₄, S₃₆, S₃₈Differentially increased by
Width and compared by lower comparators 41-48
It Similarly, AND gate A_U2Output of "1" level
Sometimes, the switching block S in the third row₃₂，
S₃₄, S₃₆, S₃₈, And the 4th row adjacent to this
Itching block S_{twenty one}, S_{twenty three}, S_{twenty five}, S₂₇Is activated
Re_,Differential amplification is performed, and the lower comparator 4
The comparison according to 1 to 48 is performed. For example, Andge
To A_U2When the output of is at "1" level, switching
Block S_{twenty one}, S_{twenty three}, S₃₂, S₃₄By lower conversion code
Is detected, the switching block S_{twenty five}, S₂₇, S₃₆，
S₃₈Detects the redundant bit of the lower conversion code.

In this way, the lower conversion code is the activated switching block, the sampled voltage V _S is compared with the reference voltage divided by the reference resistance element, and the AND gates of the lower comparators 41 to 48 are compared. A _D1 ~
A binary signal corresponding to the comparison result is output from A _{D8 and the} output gates 51 and 52 to the lower encoder 60.

In the lower encoder 60, as shown in FIG. 8, AND gates A _D1 to
The output conversion codes D _{2 to} D ₄ are output to the line LN according to the output levels of A _D8 and the output gates 51 and 52 (A _D0 and A _D9 ).
_It is set to ₆₁ and output, and the selection line LN ₆₂
One line of Ln ₆₄ is set to "1", are input to the AND gates A ₁ to A ₃ of the selection gate 70 as the selection signal SEL ₁ to SEL _3. At this time, for example, when the output of the AND gate A _D6 of the lower comparator 46 is at “1” level, the conversion codes D _{2 to} D ₄ are [11].
1] is set and output, and the selection signal SEL ₁ is “1”.
When the selection signals SEL ₂ and SEL ₃ are “0” level, the selection gate 70 is connected to the AND gate A ₁ of the selection gate 70.
Is input to AND gates A ₂ and A ₃ .

In the select gate 70, only the AND gate A ₁ is activated in response to the input of only the select signal SEL ₁ at "1" level. The high-order data generated on the line LN ₃₁ of the high-order encoder 30 is supplied to the AND gate A ₁ . Therefore, in the select gate 70,
The upper data generated on the line LN ₃₁ is selected and, as a result, is output as the upper conversion code D ₁ via the OR gate OR ₁ .

This A / D conversion circuit can obtain an accurate conversion code detected at a lower time point even when the settling characteristic of the sampling circuit is bad due to high-speed sampling, and a redundant dedicated circuit is unnecessary. This has the advantage that the matrix circuit 10 and the selection circuit 70 can be simplified.

[0031]

However, in the above-mentioned A / D conversion circuit, if an attempt is made to improve the resolution, a large number of taps from the voltage dividing resistance element group are required, and a finer semiconductor element is processed. However, the so-called offset voltage of the comparator becomes equivalent to the error because the reference voltage value of the adjacent comparator becomes minute when the miniaturization progresses. As a result, there is an adverse effect such as loss of the characteristics as.

Therefore, as a means for solving this problem and improving the resolution, a comparison circuit employing a so-called interpolation structure has been proposed. FIG. 9 is a block diagram showing a conventional comparison circuit adopting this interpolation structure. In FIG. 9, cmp ₁ and cmp ₂ are complementary output type comparators, v _in is an input analog signal, and v _r1 and v _r2 (v _r1 <v _r2 ) are reference voltages, respectively.

In this comparison circuit, an intermediate virtual voltage between the two reference voltages v _r1 and v _r2 is obtained from the positive output of the comparator cmp _{1 and} the negative output of the comparator cmp ₂ , and this virtual voltage and the input An extra comparison result of the analog signal v _in is obtained. This configuration has the advantage of facilitating absorption of errors such as machining accuracy as compared with the case where a large number of independent taps are taken as described above, but the two reference voltages v _r1 , v
_R2 can be equally weighted and only an extra result of comparison with an intermediate voltage between the two reference voltages is obtained, and an arbitrary number or multiple virtual voltages cannot be obtained. Therefore, the resolution of the above-described conventional A / D conversion circuit can be doubled, further improvement is difficult, and there is a problem that the applicable range is limited.

The present invention has been made in view of such circumstances, and an object thereof is to significantly improve the resolution.
It is to provide a / D conversion circuit.

[0035]

In order to achieve the above object, according to the present invention, a plurality of reference resistance elements connected in series between two reference potentials and arranged in a matrix and having a higher conversion output. A plurality of differential outputs that are activated by a signal on a row-by-row basis and compare each reference voltage divided by the reference resistance element with the converted input signal to detect the presence or absence of lower bit data and redundant bit data to obtain a differential output. An upper encoder that compares a switching block and a reference voltage supplied to the switching block located at a specific position of the switching block matrix with an input signal to be converted, and obtains a plurality of conversion codes of upper bits according to the comparison result. If, the obtained first and second comparator weight of the output to obtain a set complementary output n, complementary output weight of the output is set to n ₁ n a comparator, weight of the output is
₂ (however, n ₁ + n ₂ = N) is set to obtain a complementary output, and one output of the third comparator and one output of the fourth comparator are added. A first adder and a second adder for adding the other output of the third comparator and the other output of the fourth comparator, and The differential output of one column of the switching block matrix is connected to the input of the third comparator,
Inputs of the second and fourth comparators are connected to lower comparators to which differential outputs of other columns of the switching block matrix are connected, and complementary outputs of the respective comparators of the lower comparators to lower bit data and redundant bit data. From the upper encoder and a lower encoder that generates a selection signal for selecting any one of the upper bit conversion codes of the upper encoder while obtaining a predetermined lower conversion code according to the presence or absence of There is provided a selection gate for selectively outputting any one of the plurality of converted codes of the upper bits output based on the selection signal output from the lower encoder.

In the present invention, the lower comparator comprises a first comparator or a second comparator and third and fourth comparators corresponding to each column of the switching block,
The input of each comparator has a plurality of comparators connected to the differential output of the switching block of the corresponding column, and the outputs of the third and fourth comparators of each comparator are the third comparators of the other comparators. Alternatively, the ring comparator is configured by a ring comparator connected to the output of the fourth comparator, and a predetermined part of the ring comparator is cut according to the upper conversion output signal, and an unnecessary comparator output is input to the lower comparator. Equipped with a deterrent circuit to deter.

In the present invention, the weights of the outputs of the third and fourth comparators are set to n ₁ = n ₂ = N / 2.

[0038]

According to the present invention, when an analog signal is input to the upper encoder, the input signal is compared with the reference voltage supplied to the switching block located at a specific position of the switching block matrix, and the comparison result is obtained. A plurality of conversion codes of upper bits corresponding to the above are output to the selection gate. In parallel with the conversion operation of the high-order bits, the input analog signal is output from each of the switching blocks arranged in a matrix in each of the switching blocks in the row activated by the high-order conversion output signal.
The reference potential is divided by the reference resistance element and compared with each reference voltage. The differential output that is the comparison result of these switching blocks is output to the lower encoder as lower bit data or redundant bit data. In the lower encoder, the differential output of one column is input to the inputs of the first and third comparators, and the differential output of the other column is input to the inputs of the second and fourth comparators. These first to fourth comparators constitute a comparison circuit having an interpolation structure, and a predetermined complementary output is obtained in this comparison circuit and output to the lower encoder. The lower encoder obtains and outputs a predetermined lower conversion code according to the presence or absence of lower bit data and redundant bit data in the output data of the lower comparator. At the same time, a selection signal for selecting any one of the conversion codes of the upper bits generated by the upper encoder is generated, and the selection signal is output to the selection gate. In the select gate,
One conversion code is selected from a plurality of conversion codes of upper bits output from the upper encoder based on the selection signal output from the lower encoder, and is output as an upper conversion code.

According to the invention, the differential output of the activated switching block is the two first comparators of the connected comparators or the second comparators of the connected comparators or the first and second comparators. Are compared with each other by a third or fourth comparator or by a comparison circuit having an interpolation structure composed of third and fourth comparators, and an interpolation output is obtained and output to a lower encoder. At this time, in the suppression circuit, a predetermined part of the ring comparator is cut based on the higher conversion output signal, and unnecessary input of interpolation output to the lower encoder is suppressed.

According to the present invention, the input signal and the virtual voltage {V
_{R1 + (V R2 -V R1)} · (1/4)}, {V R1 + (V R2 -
V _R1 ) · (1/2)}, {V _R1 + (V _R2 −V _R1 ) · (3
/ 4)}. Note that V _R1 and V _R2 indicate predetermined reference voltages.

[0041]

1 is a circuit diagram showing an embodiment of an A / D conversion circuit according to the present invention, and the same components as those in FIG. 6 showing a conventional example are represented by the same reference numerals. That is, 10 is a matrix circuit, 21 to 23 are upper comparators, 30 is an upper encoder, 70 is a selection gate, 80 is an inverter,
101 to 108 are interpolation type lower comparators, 111 to 1
18 is a latch circuit, 121 and 122 are inhibiting circuits, 130
Is a lower AND gate circuit, 140 is a lower encoder,
R _{1 to} R ₁₆ are reference resistance elements, r is a load resistance element, B _U1
~ B _U3 , B _D0 ~ B _D33 are multi-output pin buffers, AD _U1 ~
AD _U5 is a high-order 2-input AND gate, and OR ₁ is a conversion code output 2-input OR gate. This circuit shows a circuit configuration for converting the input analog signal V _IN into a 6-bit digital code.

The positive side output of the comparator C _U1 of the upper comparator 21 is connected to both inputs of the 2-input AND gate AD _U1 .
The negative output is connected to one input of the AND gate AD _U3 . The positive side output of the comparator C _U2 of the upper comparator 22 is connected to both inputs of the two-input AND gate AD _U2 , and the negative side output is connected to both inputs of the AND gate AD _U4 . The positive side output of the comparator C _U3 of the upper comparator 23 is 2
The input AND gate AD _U3 is connected to the other input, and the negative output is connected to both inputs of the AND gate AD _U5 .

The output of the AND gate AD _U1 is used as a control signal x ₁ for switching blocks S ₁₂ , S ₁₄ ,
Is supplied to the base of the transistor Q ₃ of S _16, S _18, the output of the AND gate AD _U2 is supplied as the control signal x ₂ to the base of the switching block S _21, S _23, the transistor Q ₃ of S _25, S _27, the output of the aND gate AD _U3 is supplied as the control signal x ₃ to the base of the switching block S _32, S _34, the transistor Q ₃ of S _36, S _38, switching block as an output the control signal x ₄ of the aND gate AD _U4 S ₄₁ , S ₄₃ ,
Is supplied to the base of the transistor Q ₃ of S _45, S _47, is supplied to the base of the transistor Q ₃ of the switching block _{S 52, S 54, S 56} , S 58 output of the AND gate AD _U5 is as a control signal x ₅ .

In the AND gates AD _{U1 to} AD _U5 , two output levels adjacent to each other simultaneously become “1”.
Specifically, AND gates AD _U1 and AD _U2 , AD _U2 and A
The binary output signal levels of D _U3 , AD _U3 and AD _U4 , and AD _U4 and AD _U5 are “1” at the same time, and the control lines (x _1, x _2, x _3, x _4, x ₄ are at “1” level) _. The transistor Q ₃ of each switching block of the matrix circuit 10 connected to x ₅ ) is turned on in units of two rows, and the quantization level is finely digitized.

The lower comparators 101 to 108 respectively have a comparator C _N1 whose gain is set to _N and a gain n.
Comparator C _n1 set to ₁ (n ₁ <N) and gain n
₂ (where n ₁ = n ₂ <N, n ₁ + n ₂ = N) and the comparator C _n1 .

Each comparator C _N1 of the lower comparator 101,
The first of the matrix circuit 10 is connected to one of the inputs of C _n1 and C _n2 .
The collector output of the transistor Q ₁ of the switching blocks S ₂₁ , s _{41 in} the column is supplied, and the collector output (differential output) of the transistor Q ₂ of the switching blocks S ₂₁ , S ₄₁ is supplied to the other input.

Each comparator C _N1 of the lower comparator 102,
The second of the matrix circuit 10 is connected to one of the inputs of C _n1 and C _n2 .
The collector output of the transistor to Q ₁ th column switching block S _12, S _32, S ₅₂ are supplied, the collector output of the transistor Q ₂ of the switching block S _12, S _32, S ₅₂ are supplied to the other input .

Each comparator C _N1 of the lower comparator 103,
One of the inputs of C _n1 and C _n2 is the third input of the matrix circuit 10.
The collector output of the transistor Q ₁ of the switching blocks S ₂₃ and S _{43 in} the column is supplied, and the collector output of the transistor Q ₂ of the switching blocks S ₂₃ and S ₄₃ is supplied to the other input.

Each comparator C _N1 of the lower comparator 104,
The fourth of the matrix circuit 10 is connected to one input of C _n1 and C _n2 .
The collector output of the transistor Q ₁ of the switching blocks S ₁₄ and S _{34 in} the column is supplied, and the collector output of the transistor Q ₂ of the switching blocks S ₁₄ and S ₃₄ is supplied to the other input.

Each comparator C _N1 of the lower comparator 105,
The fifth of the matrix circuit 10 is connected to one input of C _n1 and C _n2 .
The collector output of the transistor Q ₁ of the switching blocks S ₂₅ and S _{45 in} the column is supplied, and the collector output of the transistor Q ₂ of the switching blocks S ₂₅ and S ₄₅ is supplied to the other input.

Each comparator C _N1 of the lower comparator 106,
The sixth of the matrix circuit 10 is connected to one input of C _n1 and C _n2 .
The collector output of the transistor Q ₁ of the switching blocks S ₁₆ and S _{36 in} the column is supplied, and the collector output of the transistor Q ₂ of the switching blocks S ₁₆ and S ₃₆ is supplied to the other input.

Each comparator C _N1 of the lower comparator 107,
The seventh input of the matrix circuit 10 is connected to one input of C _n1 and C _n2 .
The collector output of the transistor Q ₁ of the switching blocks S ₂₇ and S _{47 in} the column is supplied, and the collector output of the transistor Q ₂ of the switching blocks S ₂₇ and S ₄₇ is supplied to the other input.

Each comparator C _N1 of the lower comparator 108,
The eighth of the matrix circuit 10 is connected to one of the inputs of C _n1 and C _n2 .
The collector output of the transistor Q ₁ of the switching blocks S ₁₈ and S _{38 in} the column is supplied, and the collector output of the transistor Q ₂ of the switching blocks S ₁₈ and S ₃₈ is supplied to the other input.

Both the positive and negative outputs of the comparators C _N1 , C _n1 and C _n2 of the lower comparators 101 to 108 are connected to the load resistance element r which is connected to the ground level, and the respective latches. It is connected to the circuits 111 to 118 and lower comparators corresponding to adjacent columns or columns skipped by one column.

That is, both the positive and negative outputs of the comparator C _N1 of the lower comparator 101 are connected to the latch circuit 111. Comparator C _{n1 of the} lower comparator 101
With positive and negative output of which is connected to the latch circuit 111, the positive output is connected to the positive output of the comparator C _n1 lower comparator 102, comparator C _n1 of negative output is low-order comparator 102 Is connected to the negative output of. The positive side output of the comparator C _n2 of the lower comparator 101 is connected to the latch circuit 111 and the positive side output of the comparator C _n1 of the lower comparator 103, and the negative side output is the comparator C of the lower comparator 103. Connected to the negative output of _n1 .

Both the positive and negative outputs of the comparator C _N1 of the lower comparator 102 are connected to the latch circuit 112,
The positive output of the comparator C _n1 is connected to the latch circuit 112. The positive and negative outputs of the comparator C _n2 of the lower comparator 102 are connected to the latch circuit 112, the positive output is connected to the positive output of the comparator C _n1 of the lower comparator 104, and the negative output is Lower comparator 10
4 is connected to the negative output of the comparator C _n1 .

Comparator C of the lower comparator 103_N1, C
_n1Both the positive side and negative side of the output are connected to the latch circuit 113.
Has been done. Comparator C of the lower comparator 103_n2Positive
The side output is connected to the latch circuit 113, and
Comparator C of the lower comparator 105_n1Connect to the positive output of
And the negative output is the comparator C of the lower comparator 105. _n1
Is connected to the negative output of.

Both the positive and negative outputs of the comparator C _N1 of the lower comparator 104 are connected to the latch circuit 114,
The positive side output of the comparator C _n1 is connected to the latch circuit 114. The positive and negative outputs of the comparator C _n2 of the lower comparator 104 are connected to the latch circuit 114, the positive output is connected to the positive output of the comparator C _n1 of the lower comparator 106, and the negative output is Lower comparator 10
6 is connected to the negative output of the comparator C _n1 .

Comparator C of the lower comparator 105_N1, C
_n1Both the positive side and negative side of the output are connected to the latch circuit 115.
Has been done. Comparator C of the lower comparator 105_n2Positive
The side output is connected to the latch circuit 115, and
Comparator C of the lower comparator 107_n1Connect to the positive output of
And the negative output is the comparator C of the lower comparator 107. _n1
Is connected to the negative output of.

Both the positive and negative outputs of the comparator C _N1 of the lower comparator 106 are connected to the latch circuit 116,
The positive side output of the comparator C _n1 is connected to the latch circuit 116. The positive and negative outputs of the comparator C _n2 of the lower comparator 106 are connected to the latch circuit 116, the positive output is connected to the positive output of the comparator C _n1 of the lower comparator 108, and the negative output is Lower comparator 10
8 is connected to the negative side output of the comparator C _n1 .

Comparator C of the lower comparator 107_N1, C
_n1Both the positive and negative outputs of the are connected to the latch circuit 117
Has been done. Comparator C of the lower comparator 107_n2Positive
The side output is connected to the latch circuit 117, and
Comparator C of the lower comparator 108_n2Connect to the positive output of
And the negative output is the comparator C of the lower comparator 108. _n2
Is connected to the negative output of.

Comparators C _N1 and C of the lower comparator 108
Both the positive side and negative side outputs of _n2 are connected to the latch circuit 118, and the positive side output of the comparator C _n1 is connected to the latch circuit 118.

Thus, the lower comparators 101 to 1
The outputs of the comparators C _n1 and C _{n2 having} gains n ₁ and n ₂ of 08 are connected to the comparators C _n1 or C _n2 of the lower comparators corresponding to the adjacent columns or skipped by one column, and are connected. The two comparators C _N1 having the gain N of the two lower comparators and the comparators C _n1 and C _n2 having the gains n ₁ and n _{2 form} a comparison circuit having an interpolation structure. The basic configuration and function of the interpolating comparison circuit configured between two lower comparators will be described below with reference to FIGS.
Will be described in detail.

FIG. 2 is a block diagram showing the basic structure of this comparison circuit. In FIG. 2, CMP ₁ is a first comparator, CMP ₂ is a second comparator, CMP ₃ is a third comparator, CMP ₄ is a fourth comparator, ADD ₁ is a first adder, ADD. ₂ is a second adder, V _IN is an input analog signal (hereinafter, simply referred to as an input signal), V _R1 is a first reference voltage, V _R2 is a second reference voltage, and A to E are comparison outputs. ing.

The first comparator CMP ₁ is composed of, for example, a 2-input 2-output differential amplifier that obtains a complementary output in which output weighting, that is, gain is set to N times, and one input thereof is an input signal V _IN. Of the first reference voltage V _R1 and the other input is connected to the input line of the first reference voltage V _R1 . The first comparator CMP ₁ compares the input signal V _IN with the first reference voltage V _R1 and outputs the signal S ₁ from the negative side output and the signal S ₂ from the positive side output. The positive side and negative side outputs of the first comparator CMP ₁ constitute the output A of the comparison circuit.

The second comparator CMP ₂ is composed of, for example, a 2-input 2-output differential amplifier which obtains a complementary output in which the weighting of the output is set to N, one input of which is the input signal V _IN.
Of the second reference voltage V _R2 and the other input is connected to the input line of the second reference voltage V _R2 . Second comparator CM
P ₂ compares the input signal V _IN with the second reference voltage V _R2 and outputs the signal S ₃ from the negative output and the signal S ₄ from the positive output. The positive and negative outputs of the second comparator CMP _{2 form} the output E of the comparison circuit.

The third comparator CMP ₃ is composed of, for example, a 2-input 2-output differential amplifier which obtains a complementary output whose output weight is set to n ₁ (n ₁ <N), and one input of which is an input. It is connected to the input line of the signal V _IN and the other input is connected to the input line of the first reference voltage V _R1 . The third comparator CMP ₃ compares the input signal V _IN with the first reference voltage V _R1 and outputs the signal S ₅ from the negative side output and the signal S ₆ from the positive side output.

The fourth comparator CMP ₄ is, for example, a ₂ -input 2-output differential amplifier which obtains complementary outputs in which the output weighting is set to n ₂ (where n ₂ <N, n ₁ + n ₂ = N). One input is connected to the input line of the input signal V _IN and the other input is connected to the input line of the second reference voltage V _R2 . The fourth comparator CMP ₄ compares the input signal V _IN with the second reference voltage V _R2 and outputs the signal S ₇ from the negative side output and the signal S ₈ from the positive side output.

The first adder ADD ₁ has a third comparator C
Calculates the sum (S ₅ + S ₇₎ the negative output signal S ₅ and the negative output signal S ₇ of the fourth comparator CMP ₄ MP _3, signal S ₉
Output as.

The second adder ADD ₂ has a third comparator C.
Calculates the sum (S ₆ + S ₈₎ of the positive output signal S ₆ of the MP ₃ and the positive output signal S ₈ of the fourth comparator CMP _4, signal S ₁₀
Output as.

These first and second adders ADD ₁ ,
The output signals S ₉ and S ₁₀ of ADD _{2 form} the output C of the comparison circuit. Further, the output signal S ₉ of the first adder ADD ₁ and the positive side output signal S ₉ of the first comparator CMP _1
2 constitutes the output B of the comparison circuit, and the second adder A
The output signal S _{10 of} DD ₂ and the negative side output signal S ₃ of the second comparator CMP ₂ constitute the output D of the comparison circuit.

As described above, in the present comparison circuit, the output of the _third comparator CMP _{3 and} the output of the fourth comparator CMP ₄ are weighted by n ₁ : n ₂ , and both are added. Then, n ₁ + n ₂ (= N), and the gain is set so that the weights are the same as the outputs of the first and second comparators CMP ₁ and CMP ₂ . Also, the output A of this comparison circuit
˜E are connected to a latch circuit (not shown).

The input / output characteristics of each part of the circuit of FIG. 2 will be described with reference to FIG. In FIG. 3, the horizontal axis represents the input voltage and the vertical axis represents the relative output level.

First, the output signal S of the _first adder ADD ₁
Consider item ₉ . The signal S ₉ has the following formula:
A negative output signal S ₅ of the third comparator CMP ₃ is the sum of the negative output signal S ₇ of the fourth comparator CMP _4. S ₉ = S ₅ + S ₇ (1) Here, the first comparator CMP ₁ and the third comparator CMP ₃
Means that the same voltage is supplied to the two inputs, respectively, and the weights of the outputs of both are N: n ₁ .
The following relational expression holds between the negative output signals S ₁ and S ₅ . N: n ₁ = S ₁ : S ₅ (2) The signal S ₅ can be expressed by the following equation by this equation (2). S ₅ = (n ₁ / N) · S ₁ (3)

Similarly, the second comparator CMP ₂ and the fourth comparator CMP ₄ are supplied with the same voltage at their two inputs, and the weights of their outputs are N: n ₂ . Therefore, the following relational expression holds between the negative output signals S ₃ and S ₇ . N: n ₂ = S ₃ : S ₇ (4) The signal S ₇ can be expressed by the following equation by the equation (4). S ₇ = (n ₂ / N) · S ₃ (5)

Therefore, the above equations (3) and (5)
By substituting into (1), equation (1) can be rewritten as follows. S ₉ = (n ₁ / N) · S ₁ + (n ₂ / N) · S ₃ (6) Considering equation (6) with reference to FIG. 3, the signal S ₉ is the signal S ₁
And the signal S ₃ are internally divided into n ₁ : n ₂ .

Next, the output signal S of the _second adder ADD ₂
Consider ₁₀ The signal S ₁₀ has the following equation:
Is the sum of the third comparator CMP ₃ and the positive-side output signal S ₆ of the fourth comparator CMP _fourth positive output signal S _8. S ₁₀ = S ₆ + S ₈ (7) As described above, the first comparator CMP ₁ and the third comparator CMP ₃ are supplied with the same voltage at their two inputs, respectively, and Since the output weighting is N: n ₁ , the following relational expression holds between the positive side output signals S ₂ and S ₆ . N: n ₁ = S ₂ : S ₆ (8) The signal S ₆ can be expressed by the following equation by the equation (8). S ₆ = (n ₁ / N) · S ₂ (9)

Similarly, the second comparator CMP ₂ and the fourth comparator CMP ₄ are supplied with the same voltage at their two inputs, and the weights of their outputs are N: n ₂ . Therefore, the following relational expression holds between the positive side output signals S ₄ and S ₈ . N: n ₂ = S ₄ : S ₈ (10) The signal S ₈ can be expressed by the following equation by the equation (10). S ₈ = (n ₂ / N) · S ₄ (11)

Therefore, the above equations (9) and (10) are transformed into
By substituting in (7), equation (7) can be rewritten as follows. S ₁₀ = (n ₁ / N) · S ₂ + (n ₂ / N) · S ₄ (12) Considering equation (12) with reference to FIG. 3, the signal S ₁₀ is the signal S ₂
And the signal S ₄ are internally divided into n ₁ : n ₂ .

The result of consideration of the above equations (6) and (12)
Signal S in FIG.₉And signal S _TenIntersection P with
₂Is the signal S₁And signal S₂Intersection P with₁And signal S₃Belief
Issue S_FourIntersection P with₃And n₁: N₂At the point divided into
It Therefore, the signal S₉And signal S_TenOutput consisting of
Signal C (S₉, S_Ten) Is the input signal voltage and the temporary
Thought voltage V_CIt becomes the comparison result with. V_C= V_R1+ (V_R2-V_R1) ・ (N₁/ N) (13) where N = n₁+ N₂

The level of the output signal B (S ₂ , S ₉ ) consisting of the signal S ₂ and the signal S ₉ changes depending on the level of P ₄ , which is the intersection of the two. Intersection P _{4 of} signal S ₂ and signal S ₉
Is a point of intersection P ₂ between the intersection P ₁ and the signal S ₉ and the signal S ₁₀ with signals S ₁ and the signal S ₂ 1: a point which internally divides 1. Therefore, the output signal B consisting of the signals S ₂ and S ₉
(S ₂ , S ₉ ) is the result of comparison between the input signal voltage and the virtual voltage V _B expressed by the following equation. V _B = V _R1 + (V _R2 −V _R1 ) · (n ₁ / 2N) (14)

Similarly, the level of the output signal D (S ₃ , S ₁₀ ) consisting of the signal S ₃ and the signal S ₁₀ changes depending on the level of P ₅ , which is the intersection of the two. Intersection P between signal S ₃ and signal S _10
5, the intersection point P ₃ between the intersection P ₂ and the signal S ₃ and the signal S ₄ and the signal S ₉ and the signal S ₁₀ 1: a point which internally divides 1. Therefore, the output signal D composed of the signals S ₃ and S ₁₀
(S ₃ , S ₁₀ ) is the result of comparison between the input signal voltage and the virtual voltage V _D expressed by the following equation. V _D = V _R2 − (V _R2 −V _R1 ) · (n ₂ / 2N) (15)

As described above, this comparison circuit has two groups.
Sub-voltage V_R1And V_R2To three interpolation points P₂, P_FourAnd
And P_FiveThe comparison result of can be obtained. Each interpolation point P₂，
P_FourAnd P_FiveVirtual voltage V at_C, V_B, V_DIs
From the above equations (13) to (15) and FIG. 3, the following relationships are satisfied. V_R1<V_B, V_C, V_D<V_R2 (16) Further, the third and fourth comparators CMP₃, CMP_FourOut of
Force weight n₁, N₂Is n₁+ N₂Satisfies the condition of = N
It can be set to any value as long as Therefore,
n₁, N₂By selecting the value of
V_B, V _C, V_DValue of the first reference voltage V_R1And the second group
Sub-voltage V_R2It can be set to any value between and.
For example, as in this embodiment, n₁= N₂= N / 2
In this case, V from equation (13)_C= V_R1+ (V_R2-V_R1) ・
From equations (1/2) and (14), V_B= V_R1+ (V_R2−
V_R1) ・ (1/4) 、 V from equation (15)_D= V_R2-(V
_R2-V_R1) ・ (1/4) = V_R1+ (V_R2-V_R1) ・ (1
/ 4) is obtained. These are V_R1And V_R2Voltage of 4
The result of comparison between the input signal and the virtual voltage divided equally is obtained.
And represents.

A comparison circuit having such an interpolation structure is
When applied to the / D conversion circuit, the weights n ₁ and n ₂ of the outputs of the third and fourth comparators CMP ₃ and CMP ₄ are n
It is desirable to satisfy the condition of ₁ = n ₂ = N / 2.

In the configuration of FIG. 1, as described above,
Two comparators C _N1 with gain N of two lower comparators
And the comparators C _n1 and C _n2 having the gains n ₁ and n _{2 form} a comparison circuit having an interpolation structure capable of obtaining two interpolation outputs. For example, comparators C _N1 and C of lower comparator 101
_n1 first comparator CMP ₁ and the third comparator CMP ₃ in FIG. 2 are respectively made, the lower comparator 10
Two comparators C _N1 and C _n1 allow the second comparator C of FIG.
MP ₂ and the fourth comparator CMP ₄ are respectively configured and function as the comparison circuit of FIG. However, the output of the comparison circuit in this case is equivalent to the outputs A, C and E in FIG. Similarly, lower comparator 1
The comparators C _N1 and C _n2 of 01 form the first comparator CMP ₁ and the third comparator CMP ₃ of FIG. 2, respectively, and the comparators C _N1 and C _n1 of the lower comparator 103 form the second comparator of FIG. Comparator CMP ₂ and fourth comparator C
Each MP ₄ is configured and functions as the comparison circuit of FIG.

Hereinafter, the comparator C of the lower comparator 102
The first comparator CMP ₁ and the third comparator CMP ₃ of FIG. 2 are configured by _N1 and C _n2, respectively, and the comparators C _N1 and C _n1 of the lower comparator 104 are the second comparator of FIG.
The comparator CMP ₂ and the fourth comparator CMP ₄ are respectively configured and function as the comparison circuit of FIG. First comparator CMP ₁ and the third comparator CMP ₃ in FIG. 2 are constituted respectively by a comparator C _N1 and C _n2 of the low-order comparator 103, comparator C _N1 of the low-order comparator 105
The second comparator CMP ₂ and the fourth comparator CMP ₄ of FIG. 2 are configured by C _n1 and C _n1, respectively, and function as the comparison circuit of FIG. The comparators C _N1 and C _n2 of the lower comparator 104 constitute the first comparator CMP ₁ and the third comparator CMP ₃ of FIG. 2, respectively, and the comparators C _N1 and C _n1 of the lower comparator 106 of FIG. The second comparator CMP ₂ and the fourth comparator CMP ₄ are respectively configured and function as the comparison circuit of FIG. By the comparators C _N1 and C _n2 of the lower comparator 105, FIG.
The first comparator CMP ₁ and the third comparator CMP ₃ of the
The second comparator CMP ₂ and the fourth comparator CMP ₄ of FIG. 2 are configured by _N1 and C _n1, respectively, and function as the comparison circuit of FIG. The comparators C _N1 and C _n2 of the lower comparator 106 configure the first comparator CMP ₁ and the third comparator CMP ₃ of FIG. 2, respectively, and the comparators C _N1 and C _n1 of the lower comparator 108 of FIG. The second comparator CMP ₂ and the fourth comparator CMP ₄ are respectively configured and function as the comparison circuit of FIG. The comparators C _N1 and C _n2 of the lower comparator 107 allow the first comparator CMP ₁ and the third comparator CMP _{3 of FIG.}
2, and the comparators C _N1 and C _n2 of the lower comparator 108 constitute the second comparator CMP ₂ and the fourth comparator CMP ₄ of FIG. 2, respectively, and function as the comparison circuit of FIG.

In each of these comparison circuits, even if the positions of the first and third comparators and the positions of the second and fourth comparators are reversed, the function itself does not change.

Each of the latch circuits 111 to 118 has two
It is composed of input 2 output amplifiers a to d. Deterrence times
Road 121 is an OR gate OR_D1, OR_D2And Andge
AD_D1~ AD _D3And the suppression circuit 122 is turned off.
Agate OR_D3, OR_D4And AND gate AD_D4~ A
D_D6It is composed by. The AND gate circuit 130
Inverter I₁(A_D0), I₂(A_D33) And And
Gate A_D1~ A_D32It is composed by. Configuration of FIG.
, The latch circuits 111 to 118
Roads 121 and 122, AND gate 130 and lower level
A so-called ring comparator is provided by the parators 101 to 108.
And an inverter of the AND gate circuit 130 is configured.
Ta I ₁(A_D0), I₂(A_D33) And AND gate A
_D1~ A_D32Only one of the two is active
It is configured to output a bell. Below,
Outputs of comparators 101-108 and latch circuits 111-
Connection relationship with 118 and latch circuits 111 to 118
Output and suppression circuits 121 and 122 and AND gate circuit
The connection relationship with the path 130 will be described.

The positive side output of the comparator C _n1 of the lower comparator 101 is connected to one input of the amplifier a of the latch circuit 111, and the negative side output is connected to the other input of the amplifier a and one input of the amplifier b. ing. Lower comparator 1
The positive side output of the comparator C _N1 of 01 is connected to the other input of the amplifier b of the latch circuit 111 and one input of the amplifier c, and the negative side output is connected to the other input of the amplifier c and one input of the amplifier d. It is connected. Lower comparator 101
The output of the comparator C _{n2 on} the positive side is the amplifier d of the latch circuit 111.
Connected to the other input of.

The positive side output of the amplifier a of the latch circuit 111 is connected to one input of the AND gate A _D1 of the AND gate circuit 130, and the negative side output is connected to one input of the AND gate AD _D1 of the inhibition circuit 121. , The positive side output of the amplifier b is connected to one input of the AND gate A _D2 of the AND gate circuit 130, the negative side output is connected to one input of the AND gate AD _D2 of the inhibition circuit 121, and the positive side of the amplifier c. The output is connected to one input of the AND gate A _D3 of the AND gate circuit 130, and the negative side output is connected to one input of the AND gate AD _D3 and one input of the OR gate OR _D1 of the inhibition circuit 121 and is connected to the amplifier d. positive output is connected to one input of the aND gate a _D4 of the aND gate circuit 130, the negative side output to the other input of the aND gate a _D3 of the aND gate circuit 130 It is connected.

AND gates AD _{D1 to} A of the inhibition circuit 121
D _{D3 and} the other input of the OR gate OR _D1 are connected to the upper side other output buffers B _U1 and B _U3 (the upper side comparators 21 and 21).
The output of the inverter 80 for inverting the output level of the AND gates A _U1 and A _U3 ) of _No. 3 is connected. The output of the OR gate OR _D1 is the inverter I of the AND gate circuit 130.
_{1 and} the output of the AND gate AD _D1 is connected to _one input of the AND gate A _D5 of the AND gate circuit 130, and the output of the AND gate AD _D2 is the other of the AND gate A _D1 of the AND gate circuit 130. Connected to the input,
The output of the AND gate AD _D3 is connected to the other input of the AND gate A _D2 of the AND gate circuit 130.

The positive side output of the comparator C _n1 of the lower comparator 102 is connected to one input of the amplifier d of the latch circuit 112. The positive side output of the comparator C _N1 of the lower comparator 102 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 112, and the negative side output thereof is the other input of the amplifier c and the other input of the amplifier d. Connected to input. The positive side output of the comparator C _n2 of the lower comparator 102 is connected to one input of the amplifier a of the latch circuit 112, and the negative side output thereof is the other input of the amplifier a and the amplifier b.
Connected to the other input of.

The positive side output of the amplifier d of the latch circuit 112 is
AND gate A of AND gate circuit 130_D5The other input
Connected to the output and the negative output is the OR gate of the suppression circuit 121.
OR _D2Is connected to one input of
AND gate A of AND gate circuit 130_D6One of
The output of the AND gate circuit 130.
NAND Gate A_D7It is connected to one input of
The side output is the AND gate A of the AND gate circuit 130._D7of
It is connected to the other input and the negative output is AND gate circuit 1.
30 AND GATE A_D8Connected to one input of
The positive output of the gate a is the AND gate of the AND gate circuit 130.
To A_D8Is connected to the other input of the
AND gate A of the circuit 130_D13Connect to one input
Has been done.

The other input of the OR gate OR _D2 of the inhibition circuit 121 is connected to the outputs of the upper buffers B _U1 and B _U3 (AND gates A _U1 and A _{U3 of the} upper comparators 21 and 23). The output of the OR gate OR _D1 is connected to the other input of the AND gate A _D6 of the AND gate circuit 130.

The positive side output of the comparator C _n1 of the lower comparator 103 is connected to one input of the amplifier a of the latch circuit 113, and the negative side output is connected to the other input of the amplifier a and one input of the amplifier b. ing. Lower comparator 1
The positive side output of the comparator C _N1 of 03 is connected to the other input of the amplifier b of the latch circuit 113 and one input of the amplifier c, and the negative side output is connected to the other input of the amplifier c and one input of the amplifier d. It is connected. Lower comparator 103
The positive side output of the comparator C _n2 is the amplifier d of the latch circuit 113.
Connected to the other input of.

The positive side output of the amplifier a of the latch circuit 113 is connected to one input of the AND gate A _D9 of the AND gate circuit 130, and the negative side output is connected to the other input of the AND gate A _D4 of the AND gate circuit 130. The positive output of the amplifier b is the AND gate A _D10 of the AND gate circuit 130.
Connected to one input, the negative side output is connected to the other input of the AND gate A _D9 of the AND gate circuit 130, and the positive side output of the amplifier c is connected to one input of the AND gate A _D11 of the AND gate circuit 130. The negative side output is connected to the other input of the AND gate A _D10 of the AND gate circuit 130, and the positive side output of the amplifier d is the AND gate circuit 13.
0 is connected to one input of the AND gate A _D12 , and the negative side output is connected to the other input of the AND gate A _D11 of the AND gate circuit 130.

The positive output of the comparator C _n1 of the lower comparator 104 is connected to one input of the amplifier d of the latch circuit 114. The positive side output of the comparator C _N1 of the lower comparator 104 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 114, and the negative side output is the other input of the amplifier c and the other input of the amplifier d. Connected to input. The positive side output of the comparator C _n2 of the lower comparator 104 is connected to one input of the amplifier a of the latch circuit 114, and the negative side output thereof is the other input of the amplifier a and the amplifier b.
Connected to the other input of.

The positive side output of the amplifier d of the latch circuit 114 is connected to the other input of the AND gate A _D13 of the AND gate circuit 130, and the negative side output is connected to one input of the AND gate A _D14 of the AND gate circuit 130. And the amplifier c
The positive side output of AND gate A of AND gate circuit 130
_It is connected to the other input of _D14 , the negative side output is connected to one input of the AND gate A _D15 of the AND gate circuit 130, and the positive side output of the amplifier b is the other input of the AND gate A _D15 of the AND gate circuit 130. The negative side output is connected to one input of the AND gate A _D16 of the AND gate circuit 130, and the positive side output of the amplifier a is connected to the other input of the AND gate A _D16 of the AND gate circuit 130. The side output is connected to one input of an AND gate A _D21 of the AND gate circuit 130.

The positive side output of the comparator C _n1 of the lower comparator 105 is connected to one input of the amplifier a of the latch circuit 115, and the negative side output is connected to the other input of the amplifier a and one input of the amplifier b. ing. Lower comparator 1
The positive side output of the comparator C _N1 of 05 is connected to the other input of the amplifier b of the latch circuit 115 and one input of the amplifier c, and the negative side output is connected to the other input of the amplifier c and one input of the amplifier d. It is connected. Lower comparator 105
The positive side output of the comparator C _n2 is the amplifier d of the latch circuit 115.
Connected to the other input of.

The positive side output of the amplifier a of the latch circuit 115 is connected to one input of the AND gate A _D17 of the AND gate circuit 130, and the negative side output is connected to the other input of the AND gate A _D12 of the AND gate circuit 130. , The positive output of the amplifier b is the AND gate A of the AND gate circuit 130.
_It is connected to one input of _D18 , the negative side output is connected to the other input of AND gate A _D17 of AND gate circuit 130, and the positive side output of amplifier c is one input of AND gate A _D19 of AND gate circuit 130. The negative side output is connected to the other input of the AND gate A _D18 of the AND gate circuit 130, and the positive side output of the amplifier d is connected to one input of the AND gate A _D20 of the AND gate circuit 130, The side output is connected to the other input of the AND gate A _D19 of the AND gate circuit 130.

The positive side output of the comparator C _n1 of the lower comparator 106 is connected to one input of the amplifier d of the latch circuit 116. The positive side output of the comparator C _N1 of the lower comparator 106 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 116, and the negative side output thereof is the other input of the amplifier c and the other input of the amplifier d. Connected to input. The positive side output of the comparator C _n2 of the lower comparator 106 is connected to one input of the amplifier a of the latch circuit 116, and the negative side output thereof is the other input of the amplifier a and the amplifier b.
Connected to the other input of.

The positive side output of the amplifier d of the latch circuit 116 is connected to the other input of the AND gate A _D21 of the AND gate circuit 130, and the negative side output is connected to one input of the AND gate A _D22 of the AND gate circuit 130. And the amplifier c
The positive side output of AND gate A of AND gate circuit 130
_It is connected to the other input of _D22 , the negative side output is connected to one input of an AND gate A _D23 of the AND gate circuit 130, and the positive side output of the amplifier b is the other input of the AND gate A _D23 of the AND gate circuit 130. The negative side output is connected to one input of an AND gate A _D24 of the AND gate circuit 130, and the positive side output of the amplifier a is connected to the other input of the AND gate A _D24 of the AND gate circuit 130. The side output is connected to one input of an AND gate A _D29 of the AND gate circuit 130.

The positive side output of the comparator C _n1 of the lower comparator 107 is connected to one input of the amplifier a of the latch circuit 117, and the negative side output is connected to the other input of the amplifier a and one input of the amplifier b. ing. Lower comparator 1
The positive side output of the comparator C _N1 of 07 is connected to the other input of the amplifier b of the latch circuit 117 and one input of the amplifier c, and the negative side output is connected to the other input of the amplifier c and one input of the amplifier d. It is connected. Lower comparator 107
The positive side output of the comparator C _n2 is the amplifier d of the latch circuit 117.
Connected to the other input of.

The positive side output of the amplifier a of the latch circuit 117 is connected to one input of the AND gate A _D25 of the AND gate circuit 130, and the negative side output is connected to the other input of the AND gate A _D20 of the AND gate circuit 130. And amplifier b
The positive side output of AND gate A of AND gate circuit 130
_It is connected to one input of _D26 , the negative side output is connected to the other input of AND gate A _D25 of AND gate circuit 130, and the positive side output of amplifier c is one input of AND gate A _D27 of AND gate circuit 130. , The negative side output is connected to the other input of the AND gate A _D26 of the AND gate circuit 130, and the positive side output of the amplifier d is connected to one input of the AND gate A _D28 of the AND gate circuit 130. The side output is connected to one input of the OR gate OR _D3 of the inhibition circuit 122.

The other input of the OR gate OR _D3 of the inhibition circuit 122 is the output of the inverter 80 which inverts the output level of the upper-side other output buffers B _U1 and B _U3 (AND gates A _U1 , A _{U3 of the} upper comparators 21 and 23). Are connected. The output of OR gate OR _D3 is AND gate circuit 1
It is connected to the other input of 30 AND gate A _D27 .

The positive output of the comparator C _n1 of the lower comparator 108 is connected to one input of the amplifier d of the latch circuit 118. The positive side output of the comparator C _N1 of the lower comparator 108 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 118, and the negative side output is the other input of the amplifier c and the other side of the amplifier d. Connected to input. The positive side output of the comparator C _n2 of the lower comparator 108 is connected to one input of the amplifier a of the latch circuit 118, and the negative side output thereof is the other input of the amplifier a and the amplifier b.
Connected to the other input of.

The positive side output of the amplifier d of the latch circuit 118 is connected to the other input of the AND gate A _D29 of the AND gate circuit 130, and the negative side output is connected to one input of the AND gate A _D30 of the AND gate circuit 130. And the amplifier c
The positive side output of AND gate A of AND gate circuit 130
Connected to the other input of _D30 , the negative side output is the suppression circuit 12
2 is connected to one input of the AND gate AD _D4 and one input of the OR gate OR _D4 , the positive side output of the amplifier b is connected to one input of the AND gate A _D31 of the AND gate circuit 130, and the negative side output is connected. The inhibition circuit 122 is connected to one input of an AND gate AD _D5 , the positive side output of the amplifier a is connected to one input of an AND gate A _D32 of the AND gate circuit 130, and the negative side output is connected to the AND gate of the inhibition circuit 122. It is connected to one input of AD _D6 .

AND gates AD _{D4 to} A of the inhibition circuit 122
The outputs of the upper side buffers B _U1 and B _U3 (AND gates A _U1 and A _U3 of the upper side comparators 21 and 23) are connected to the other inputs of D _{D6 and the} OR gate OR _D4 . The output of the OR gate OR _D4 is connected to the input of the inverter I ₂ of the AND gate circuit 130, the output of the AND gate AD _D4 is connected to the other input of the AND gate A _D31 of the AND gate circuit 130, and the output of the AND gate AD _D5 . Is connected to the other input of the AND gate A _D32 of the AND gate circuit 130, and the output of the AND gate AD _D6 is connected to the other input of the AND gate A _D28 of the AND gate circuit 130.

Each inverter I of the AND gate circuit 130
Outputs of ₁ and I ₂ and AND gates A _{D1 to} A _D32 are output to the lower encoder 1 via buffers B _{D0 to} B _D33 , respectively.
Connected to 40.

Although the ring comparator is constructed by the above connection configuration, when the ring comparator is constructed by using the comparison circuit having the interpolation structure of FIG. 2, it is necessary to cut the ring left or right, and the suppression circuit 121 and 1
22 has this ring cutting function. Suppression circuit 12
1 is a circuit that cuts the left side of the ring, and the inhibition circuit 122 is a circuit that cuts the right side of the ring. Here, the basic operation of the inhibition circuit will be described with reference to FIG.

In FIG. 4, CN1 to CN8 are reference resistance elements R.
Reference voltage and input signal V divided by _INTo compare
Cn is a comparison circuit by interpolation.
FIG. 4 shows a case where the left side of the ring is cut. this
In this case, the lowest reference voltage is supplied to the comparison circuit CN1,
The highest reference voltage is supplied to the comparison circuit CN8. this
Therefore, Cn in the figure_a, Cn_b, Cn_C3 interpolation comparison times
The output of the path is unnecessary, and these outputs are
In order to prevent 40 from inputting, the suppression circuit 121 uses interpolation comparison.
Circuit Cn_a, Cn_b, Cn_CI will suppress the three outputs of
Acts like The same applies when cutting the right side of the ring.

The lower encoder 140 uses the conversion code data.
TA D₂~ D₆Generating data line LN₁₄₁And Anne
AND gate A of the gate circuit 130_D1, A_D2, A_D5~
A_D8, A_D13, A_D14One of the outputs of "1"
Selection signal SEL indicating that ₁Line L for generating
N₁₄₂And the inverter I of the AND gate circuit 130₁,
And Gate A_D2, A_D3, A_D4, A_D9~ A_D12, A_D17
~ A_D20, A_D25~ A _D28, A_D31, A_D32Output of
Selection signal SEL indicating that the shift is "1"₂To
Generated selection line LN₁₄₃And AND gate circuit 13
AND gate A of 0_D15, A_D16, A_D21~ A_D24, A
_D29, A_D30, Inverter I₂Any of the output of
Selection signal SEL indicating that it has become "1"₃To generate
Selection line LN₁₄₄It consists of and.

FIG. 5 shows the lower AND gate circuit 130.
When the outputs of the inverters I ₁ , I ₂ and A _{D1 to} A _D32 of “1” are “1”, the output conversion code data D _{2 to} D ₆ and the selection line data LN _{142 to} LN ₁₄₄ which are the encoding results of the lower encoder 140. Shows the correspondence relationship of.

Next, the operation of the above configuration will be described. Was
Sampling of sampled analog signals
Voltage V_sIs V_RB<V_S<V₃(= E₁₂) If above
Comparator C of the position comparators 21-23_U1~ C _U3Output of
"L" and AND gate A_U1~ A_U3From "0"
Binary signals are output respectively. as a result,

[000]
Binary signal is buffer B_U1~ B_U3Top Enco through
Input to the decoder 30, and AND gate A_U1, A_U3of
Output is buffer B_U1, B _U3Directly or after
Inverter circuit 80 reverses the level to suppress circuits 121 and 1
22 is input. In the upper encoder 30, the so-called
Generates predetermined data by wired OR circuit 3
Row encoder line [LN₃₁] ~ [LN₃₃] To [00
0] upper data is generated and output to the select gate 70.
Be done. At this time, the upper AND gate AD_U1~ A
D_U5Of which, Andgate AD_U4, AD_U5Output is only
It becomes "H", and AND gate AD_U4, AD_U5From
"1" control signal x_Four, X_FiveIs output.

The sampling voltage V_sIs V₃<V_S
<V₂(= E₈), The upper comparators 21 and 2
Two comparators C_U1, C_U2Output is "L", high-level comparator
Comparator C of data 23_U3Output becomes "H", and the upper comparator
AND gate A of the transmitters 21 and 22_U1And A_U2From
“0”, AND gate A of upper comparator 23_U3From
Outputs a binary signal of "1". as a result,
The binary signal of [001] is the buffer B_U1~ B_U3Through
Input to the upper encoder 30, and AND gate A
_U1, A_U3Output is buffer B_U1, B _U3Directly after
Or the level is inverted by the inverter 80 and the suppression circuit 12
1 and 122. With the upper encoder 30
Is the encoder line [LN₃₁] ~ [LN₃₃] To [00
1] upper data is generated and output to the selection gate 70.
Be done. At this time, the upper AND gate AD_U1~ A
D_U5Of which, Andgate AD_U3, AD_U4Output is only
It becomes "H", and AND gate AD_U3, AD_U4From
"1" control signal x₃, X_FourIs output.

The sampling voltage V_sIs V₂<V_S
<V₁If so, the comparator of the upper comparators 22 and 23
C_U12C_U3Output is "H", the ratio of the upper comparator 21
Comparator C_U1Output becomes "L", and the upper comparator 22
And gate A_U2From "1", upper comparator 2
1,2 3 AND gate A_U1And A_U3From "0"
Binary signals are output respectively. As a result, [010]
Binary signal is buffer B_U1~ B_U3Top Enco through
Input to the decoder 30, and AND gate A_U1, A_U3of
Output is buffer B_U1, B _U3Directly or after
Inverter circuit 80 reverses the level to suppress circuits 121 and 1
22 is input. In the upper encoder 30, the encoder
Dahrain [LN₃₁] ~ [LN₃₃] To the higher rank of [011]
Data is generated and output to the selection gate 70. Also,
At this time, the upper side AND gate AD_U1~ AD_U5Out of
And gate AD_U2, AD_U3Output is "H" only
And AND gate AD_U2, AD_U3From the control of "1"
Roll signal x₂, X₃Is output.

The sampling voltage V_sIs V₁<V_S
<V_RTIf so, the comparator of the upper comparators 21-23
C_U1~ C_U3Output becomes “H” and the upper comparator 2
AND gate A of 1_U1From "1", upper comparator
22 and 23 AND gate A _U2And A_U3From "0"
2 binary signals are output. As a result, [10
0] binary signal is buffer B_U1~ B_U3Through the upper
Input to the encoder 30, and AND gate A_U1, A
_U3Output is buffer B_U1, B _U3Directly or after
The level is inverted by the inverter 80 and the suppression circuit 121 and
And 122. In the high-order encoder 30,
Coda line [LN₃₁] ~ [LN₃₃] On [110]
The position data is generated and output to the selection gate 70. Well
At this time, the upper side AND gate AD_U1~ AD_U5Nou
CHI AND Gate AD_U1, AD_U2Output is only "H"
Become and AND gate AD_U1, AD_U2From "1"
Troll signal x₁, X₂Is output.

In parallel with this, each upper AND gate A
Connected to the control lines (x _1, x _2, x _3, x _4, x ₅ ) where the binary output signal is “1” in D _{U (1,2,3,4,5)} The transistor Q ₃ of each switching block of the matrix circuit 10 is turned on in units of two rows, and the quantization level is finely digitized.

For example, AND gate AD_U4, AD_U3of
Output control signal x_Four,x₃Output goes to "1" level
When it becomes (and gate A at this time_U3Output is "1"
Level), switching block in the second row from the bottom in the figure
S₄₁, S₄₃, S₄₅, S₄₇, And the third row adjacent to it
Eye switching block S₃₂, S₃₄, S₃₆, S₃₈Each of
Transistor Q₃Turns on and the reference resistance R₇~ R₁₆so
Reference voltage e divided ₇~ E₁₅And sampling voltage V_S
But each switching block S₄₁, S₄₃, S₄₅, S₄₇common
Every S₃₂, S₃₄, S₃₆, S₃₈Differentially amplified by
The output is the comparator C of the lower comparators 101 to 108._N1，
C_n1, C_n2Is input to the two input terminals of. Similarly, Ande
AD_U3, AD_U2Output control signal x_3,x₂of
When the output goes to "1" level (at this time, AND gate A
_U2Output is only "1" level), switch on the 3rd line
Gublock S₃₂, S₃₄, S₃₆, S₃₈, And adjacent to this
Switching block S on the second row_{twenty one}, S_{twenty three}，
S_{twenty five}, S₂₇Is activated_,Differential amplification
The differential output is the ratio of the lower comparators 101-108.
Comparator C_N1, C_n1, C_n2Is input to the two input terminals of. for example
If and gate A_U2When the output of is at "1" level
Is the switching block S_{twenty one}, S_{twenty three}, S₃₂, S₃₄By
Lower conversion code is detected, switching block S
_{twenty five}, S₂₇, S₃₆, S₃₈The lower conversion code redundancy bit
Are detected.

Gay of each lower comparator 101-108
N is₁(Or n₂) Comparator C _n1, C_n2Output next to
Lower comparators that correspond to adjacent columns or skip one column
Data comparator C_n1, C_n2Connected to the ring compar
Configured with an activated switching block.
The sampled voltage V obtained at_SAnd reference resistance
The differential output with the reference voltage divided by the element is connected
Two comparators C of two lower comparators_N1And comparator C
_n1Each other or C_n1And C_n2Of the interpolation structure composed of and
The comparison circuit compares them, resulting in an interpolated output.
And is input to each of the latch circuits 111 to 118. latch
The output of the circuit 118 passes through the suppression circuits 121 and 122.
Or directly the inverter of the AND gate circuit 130
I₁, I₂And AND gate A_D1~ A_D32Entered in
Then, a binary signal corresponding to the comparison result is output to the lower encoder 140.
Will be output to. At this time, the suppression circuit 12
1, 122 is the output signal of the upper comparator 21, 23.
Signal to the left or right of the ring comparator,
When the disconnection is performed, the lower order of the output of the unnecessary interpolation circuit
Input to the encoder 140 is suppressed.

In the lower encoder 140, the wired audio is
As shown in FIG. 5, the AND gate circuit
130 inverters I₁, I₂And AND gate A_D1
~ A _D32Output conversion code D according to the output level of₂~ D
₆Is the line LN₁₄₁Is set to and output,
Selection line LN₁₄₂~ LN₁₄₄One of the lines
Set to "1" and select signal SEL₁~ SEL₃As
AND gate A of selection gate 70₁~ A₃Enter each
I will be forced. At this time, for example, the AND gate circuit 130
And gate A_D1If the output of is at "1" level, conversion
Code D₂~ D₆Is set to [00110] and output
Selection signal SEL₁Select gate 70 at "1" level
And gate A₁To the selection signal SEL₂, SEL₃But
Select gate AND gate A at "0" level₂, A ₃To
Is entered.

In the select gate 70, only the AND gate A ₁ is activated in response to the input of only the select signal SEL ₁ at "1" level. The high-order data generated on the line LN ₃₁ of the high-order encoder 30 is supplied to the AND gate A ₁ . Therefore, in the select gate 70,
The upper data generated on the line LN ₃₁ is selected and, as a result, is output as the upper conversion code D ₁ via the OR gate OR ₁ .

As described above, according to this embodiment,
Lower comparator for each column of switching blocks
Comparator C having gain N_N1And gain
n₁(Or n₂) Comparator C_n1, C_n2Consist of
Together with the comparator C_n1, C_n2Output of adjacent columns
Or the comparator C of the lower comparator corresponding to the column skipped by one column
_n1, C_n2To form a ring comparator and
Sampling obtained by the integrated switching block
Voltage V_SAnd the reference voltage divided by the reference resistance element
And the differential output of the two connected lower comparators
Two comparators C _N1And comparator C_n1Each other or C_n1And C
_n2Interpolation by comparing with an interpolation structure comparison circuit composed of
Upper comparator 2 which is configured to obtain a dynamic output.
The left side of the ring comparator or
Cuts on the right side, and the output of unnecessary interpolation circuit
Suppression circuit 12 for suppressing input to the lower encoder 140
Since 1,122 is provided, the resolution can be significantly improved,
A highly accurate A / D conversion circuit can be realized.

Further, restrictions on the emitter size of the reference resistance element and the transistor are relaxed, and as a result, the element can be made smaller, which has an advantage that the chip area can be reduced.

Further, in the above-described embodiment, the configuration in which the other output pin buffers B _{U1 to} B _U3 and B _{D0 to} B _D33 are arranged on the input side of the upper encoder 30 and the lower encoder 140 is shown. Buffers B _{U1 to} B _U3 ,
B _{D0 to} B _D33 are provided to reliably drive the upper encoder 30 and the lower encoder 140, and need not be provided depending on the capacities of the upper encoder 30 and the lower encoder 140 that are so-called loads.

[0126]

As described above, according to the present invention,
The resolution can be significantly improved, and an A / D conversion circuit with high accuracy can be realized. Further, restrictions on the emitter size of the reference resistance element and the transistor are relaxed, and as a result, the element can be made smaller, which has an advantage that the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an A / D conversion circuit according to the present invention.

FIG. 2 is a diagram showing a basic configuration of a comparison circuit having an interpolation structure according to the present invention.

FIG. 3 is a diagram for explaining input / output characteristics of each part of the circuit of FIG.

FIG. 4 is a diagram for explaining the basic operation of the inhibition circuit according to the present invention.

FIG. 5 is a diagram showing encoded data of a lower encoder according to the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a conventional A / D conversion circuit.

7 is a diagram showing a higher conversion code pattern of the circuit of FIG. 6;

8 is a diagram showing a lower conversion code pattern of the circuit of FIG. 6;

FIG. 9 is a diagram showing a basic configuration of a comparison circuit having a conventional interpolation structure.

[Explanation of symbols]

10 ... Matrix circuit 21-23 ... High-order comparator A _U1 -A _U3 ... High-order side AND gate 30 ... High-order encoder 70 ... Selection gate 80 ... Inverter 101-108 ... Low-order comparator C _N1 ... Gain N comparator C _n1 ... Gain n _first comparator C _n2 ... comparator 111 to 118 ... the latch circuits 121 and 122 ... inhibit circuit 130 ... lower aND gate circuit I ₁ of the gain n _2, I ₂ ... inverter a _D1 to a _D32 ... aND gates 140 ... lower encoder LN ₁₄₁ ... data line _{LN 142, LN 143, LN 144} ... selection line AD _U1 ~AD _U5 ... upper side aND gates OR ₁ ... selection gate

Claims (3)

[Claims] 1. A plurality of reference resistance elements connected in series between two reference potentials, arranged in a matrix form, activated in row units by a higher conversion output signal, and divided by the reference resistance elements. A plurality of switching blocks that compare each compressed reference voltage with the converted input signal to detect the presence or absence of lower bit data and redundant bit data and obtain a differential output, and are located at specific positions of the switching block matrix. A reference encoder supplied to the switching block and the input signal to be converted are compared with each other, and an upper encoder for obtaining a plurality of conversion codes of upper bits according to the comparison result, and an output weight set to N to obtain complementary outputs. The first and second comparators, the third comparator whose output weight is set to n ₁ to obtain a complementary output, and the output weight which is n ₂ (where n ₁
+ N ₂ = N) to obtain a complementary output, and a first adder for adding one output of the third comparator and one output of the fourth comparator. , A second adder for adding the other output of the third comparator and the other output of the fourth comparator, and a second adder for adding the other output of the third comparator to the first comparator and the third comparator. A lower comparator in which a differential output of one column of the switching block matrix is connected to an input, and a differential output of another column of the switching block matrix is connected to inputs of the second and fourth comparators, The complementary output of each comparator of the lower comparator obtains a predetermined lower conversion code according to the presence or absence of lower bit data and redundant bit data, and any one of the upper bit conversion codes of the upper encoder. To select A lower-order encoder that generates a selection signal for selecting the upper-order encoder, and one of the conversion codes of the higher-order bits output from the higher-order encoder is selectively selected based on the selection signal output from the lower-order encoder. An analog / digital conversion circuit having a selection gate for outputting to. 2. The lower comparator comprises a first comparator or a second comparator and third and fourth comparators corresponding to respective columns of the switching block, and inputs of the respective comparators correspond to each other. A plurality of comparators connected to the differential outputs of the switching blocks of the column, the outputs of the third and fourth comparators of each comparator being the third comparator or the fourth comparator of the other comparator. It is composed of a ring comparator connected to the output, and is equipped with a suppression circuit that cuts off a predetermined part of the ring comparator according to the upper conversion output signal and suppresses unnecessary input of comparator output to the lower comparator. The analog / digital conversion circuit according to claim 1. 3. The analog / digital conversion circuit according to claim 1, wherein the weights of the outputs of the third and fourth comparators are set to n ₁ = n ₂ = N / 2.