JPH06283971A - Band-pass separation synthesis filter - Google Patents

Abstract

PURPOSE:To compress a circuit scale by suppressing the circuit scale to the one of around 1/2 when a complicated multiplier is used by sharing the weight circuit of a band-pass separation synthesis filter by a transmission side and a reception side. CONSTITUTION:This filter is a digital band-pass separation synthesis filter constituted in such a manner that a digital signal which forms input is separated to two bands by using a low-pass filter and a high-pass filter at a separation side, and they are sampled to 1/2, respectively, and sampled signals in two bands are interpolated by two times at a synthesis side, then, the signal of low-pass area is passed through the low-pass filter, and the one of high-pass area through the high-pass filter, and output is issued by adding them. Taps with equal tap coefficient in the low-pass filter on a separation side and the high-pass filter on a synthesis side, and the high-pass filter on the separation side and the low-pass filter on the synthesis side are comprised of an adder 14, the multiplier or the weight circuit 13, a selection circuit 16, and a code inversion circuit 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a band separating / synthesizing filter for separating (storing) a signal such as an image or a sound into a plurality of frequency components, and for analyzing in a frequency domain.

[0002]

2. Description of the Related Art Subband coding is one of the techniques for efficiently compressing voice and images. This method is realized by a so-called band separation / synthesis filter. Hereinafter, FIG. 3 and FIG.
The principle will be briefly described with reference to FIGS. Note that, generally, processing such as quantization associated with transmission is performed, but here, for the sake of simplification of description, it is assumed that the separated signals are combined as they are.

As shown in FIG. 3, the band separation / synthesis filter is composed of a transmission side for separation and a reception side for synthesis.

On the transmission side, the sampled digital input signal X (n) is a low pass filter (LPF; H).
₀ (z)) and high-pass filter (HPF; H ₁ (z))
Is separated into low-frequency components and high-frequency components. These signals are ½ subsamples, that is, decimated every other sample, and are output on the transmission side.

On the other hand, on the receiving side, the reverse conversion is performed on the receiving side. That is, for the sub-sampled low-frequency and high-frequency signals, a value 0 is inserted every other sample by the interpolation circuit, and the low-pass filter (LPF; G ₀ (z))
And is input to the high pass filter (HPF; G ₁ (z)). The signal obtained by adding these filter outputs becomes the output signal (Y (n)) on the receiving side.

That is, on the transmitting side, n input signals are converted into n / 2 high frequency signals and n / 2 low frequency signals,
At the receiving side, it is converted back into n output signals.

Generally, since the high band signal and the low band signal have different statistical properties, signal processing (quantization, entropy coding, etc.) is performed by different parameters. In addition,
In the case of an image signal, the low frequency component of n / 2 corresponds to a reduced image having a resolution of 1/2 and can be used as a small screen or the like.

Furthermore, by performing band separation on the cascode, it is possible to separate into four bands (or higher) of low low, low high, high low and high high. In addition, octave separation may be used in which only low-frequency components are separated.

For example, in image transmission and the like, the following conditions are required for this band separation / synthesis filter.

(A) Perfect reconstruction (When the separated signals are directly combined without performing processing such as quantization, the output signal must match the input signal) (b) Linear phase (filter tap coefficient is in the center (The taps should be symmetrical.) (C) Finite number of taps (the number of filter taps is relatively small due to the hardware configuration) Various methods have been proposed for the configuration of filters that satisfy these conditions. However, when the low-pass filter has 7 taps and the high-pass filter has 5 taps, the tap coefficient is calculated as follows. (However, z ⁻¹ represents a delay element of 1 clock.) [Equation 1] H ₀ (z) = a ₃ + a ₂ · z ⁻¹ + a ₁ · z ⁻² + a ₀ 0 · z ^{-3 _{+ A 1 · z -4 + a}} 2 · z -5 + a 3 · z -6 (1) [Equation 2] _{H 1 (z) = b 2} + b 1 · z -1 + b 0 · z -2 + b 1 · z - ³ + b ₂ · z ⁻⁴ (2) [Equation 3] G ₀ (z) = H ₁ (−z) = b ₂ −b ₁ · z ⁻¹ + b ₀ · z ⁻² −b ₁ · z ⁻³ + b ₂ · z ⁻⁴ (3) [Equation 4] G ₁ (z) = − H ₀ (−z) = −a ₃ + a ₂ · z ⁻¹ −a ₁ · z ⁻² + a ₀ 0 · z ⁻³ −a ₁ · z ⁻⁴ + a ₂ · z ⁻⁵ −a ₃ · z ⁻⁶ (4) where K ≠ −1 / 8 [Equation 5] a ₀ = (3/2 + 4K) / (1 + 8K) ( 5) [Equation 6] a ₁ = 1/2 + K (1-8K) / (1 + 8K) (6) [Equation 7] a ₂ =-(1-8K) / 4 (1 + 8K) (7) [Equation 8] a _{3 = -K (1-8K) / (} 1 + 8K) (8) [Equation 9] _{b 0 = 1/2 + 2K} (9) [Equation 10] _{b 1 = -1 / 4 (10} ) [Equation 11] b ₂ = -K (11) When K = 1/8, equations 5 to 11 are as follows, and H ₀ (z) and G ₁ (z) are substantially 3 taps, and H ₁ (z) ，
G ₀ (z) becomes 5 taps.

A ₀ = 1, a ₁ = 1/2, a ₂ = 0, a ₃ =
0, b ₀ = 3/4, b ₁ = -1 / 4, b ₂ = -1 / 8

[0012]

FIG. 4 shows a conventional configuration example of such a band separation / synthesis filter, and FIG. 5 shows a timing chart showing its operation. Here, D is a delay element 11 of 1 clock and D'is a delay element 12 of 2 clocks, and conventionally, each filter on the separation side and the synthesis side is provided independently.

That is, on the transmitting side, a ₀ , a ₁ , a ₂ ,
_On the receiving side, the weighting circuit 13 such as a ₃ , b ₀ , b ₁ , b ₂ has a ₀ , -a ₁ , a ₂ , -a ₃ , b ₀ , -b ₁ , b ₂ on the receiving side.
The weighting circuit 13 as described above is required. For this reason,
Especially, when a multiplier having a complicated circuit configuration is used, there is a drawback that the circuit scale becomes extremely large.

[0014]

According to the present invention, a low-pass filter on the separation (transmission) side and a high-pass filter on the synthesis (reception) side, and a high-pass filter on the separation (transmission) side and a low-pass filter on the synthesis (reception) side are provided. Paying attention to the fact that the corresponding tap coefficients have the same absolute value, and as a result of 1/2 sub-samples on the separation (transmission) side, 1/2 period is not substantially used, and synthesis (reception) is performed using this period. ) Side filter is also realized at the same time.

[0015]

By implementing the present invention, the weighting circuit including the multiplier can be shared between the separation (transmission) side and the synthesis (reception) side, and the circuit scale can be reduced to about 1/2 of the conventional one. It will be possible.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, the operation on the transmission (separation) side will be described.

The sampled signal on the transmitting side is shifted by one clock by the latch circuit 11. During the timing (sending) period in FIG. 2, the digital switch (multiplexer) 16 is connected to the (sending) side. At this time, the delayed signals of the respective latch circuits are weighted by the adder 14 and the multiplier 13 so as to be symmetrical with respect to the center tap. For example, on the (H) side, the coefficients of b ₂ , b ₁ , b ₀ , b ₁ , b ₂ are on the (L) side, and on the (L) side, a ₃ , a ₂ , a ₁ , a ₀ , a ₁ , a ₂ , A ₃ are multiplied by the delayed inputs, respectively, and the result of adding them is output. Note that the values of the two outputs (H, L) on the transmission side are valid during the (transmission) period (that is, equivalent to sub-sampling to 1/2).

Next, the operation on the receiving (combining) side will be described.

The receiving side inputs (H, L) are multiplexed every clock as shown in FIG. 2 and input to the latch circuit 11. For the input on the (H) side, -a ₃ , a ₂ , -a ₁ ,
The coefficients of a ₀ , −a ₁ , a ₂ and −a ₃ are the same as those of the input on the (L) side with respect to the delayed input of the coefficients of b ₂ , −b ₁ , b ₀ , −b ₁ and b ₂ . They are multiplied and the result of adding them is output. However, these tap coefficients are defined for a signal interpolated to 2/1 (a signal in which a value 0 is inserted every other clock in the input subsampled to 1/2). Therefore, in the period (reception), the tap coefficients of a ₂ , a ₀ , a ₂ and -b ₁ , -b ₁ are set in the period (transmission),
_{a 3, -a 1, -a 1} , -a 3, and b _2, b _0, the tap coefficients b ₂ becomes effective, respectively. Note that the output from the receiving side is also required during the period (sending), so two latch circuits 1
The time is adjusted by 8.

As can be seen by comparing FIG. 3 with FIG.
The weighting circuit is reduced to half of the conventional one.

In the above example, weighting (multiplication) and its addition are completed within one clock in order to simplify the description, but in order to increase the speed, a latch circuit is provided for each multiplication and each addition. It can also be provided and synchronized.

[0023]

According to the present invention, the weighting circuit of the band separation / synthesis filter can be shared by the transmitting side and the receiving side, and the circuit scale when a complicated multiplier is used is It can be suppressed to about 1/2.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing a basic configuration of a band separation / synthesis filter.

FIG. 4 is a block diagram of a conventional band separation / synthesis filter.

5 is a timing chart showing the operation of the conventional example of FIG.

[Explanation of symbols]

11 ... Latch circuit for delaying data every 1 clock, 12 ... Latch circuit for delaying data every 2 clocks, 13 ... Weighting circuit (or multiplier) for weighting corresponding to tap coefficient, 14 ... Adder, 15 ... Sign inversion circuit, 16 ... Selection circuit (multiplexer), 1
7, 18 ... Latch circuit for time adjustment.

Claims (1)

[Claims] 1. A separation side separates an input digital signal into two bands by using a low-pass filter and a high-pass filter, and then sub-samples each to 1/2, and on the combining side, the two sub-sampled bands are separated. A digital band separation / synthesis filter that doubles the signal, then passes it through a low-pass filter in the low band and a high-pass filter in the high band, and adds them to produce an output. Side high-pass filter and taps in the separation-side high-pass filter and the synthesis-side low-pass filter with the same absolute value of the tap coefficient are configured by an adder and a multiplier or a weighting circuit, a selection circuit, and a sign inversion circuit. Band separation synthesis filter.