JPH06282994A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To unnecessitate designating an address for selecting a block at the time of verifying erase of a block and facilitate operation by latching a block address using an address latch circuit for selecting a block. CONSTITUTION:An ALE 2 signal generator circuit 200 is provided in a control circuit 14, a generated ALE 2 signal is given to address buffer circuits A13-A17 for selecting blocks in an address register 6. And the generator circuit 200 and the buffer circuits A13-A17 form an address latch circuit for selecting blocks. Also, the ALE signal is given to only address signal buffer circuits A0-A12. And, the ALE 2 signal is made a 'H' state at the time of reading-out or falling of -WE in the address signal latch circuit. Further, the ALE 2 signal is made a 'H' state at the time of reading-out or falling of -WE, and the ALE 2 signal is made a 'L' state after erasing blocks, in the circuit 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a device having a unit block erasing means for erasing each unit block.

[0002]

2. Description of the Related Art FIG. 3 is a schematic block diagram of a conventional flash EEPROM. Flash E shown in FIG.
EPROM is the IEEE Journal of Solid-State Circuit
s, Vol.23, No.5, October 1988, pp1157-1163. This will be described below with reference to FIG. A Y gate 2, a source line switch 3, an X decoder 4, and a Y decoder 5 are provided around the memory cell array 1. An address register 6 is connected to the X decoder 4 and the Y decoder 5, and an address signal inputted from the outside is inputted. A sense amplifier 8 is connected to the memory cell array 1 via a Y gate 2. The sense amplifier 8 is connected to the input / output buffer 9.

A program voltage generating circuit 10 and a verify voltage generating circuit 11 are provided to generate a voltage different from the externally supplied power supplies Vcc and Vpp. This voltage is applied to the Y gate 2 and the X decoder 4, etc. Given. A command latch 12 for setting an operation mode according to data input from the outside and a command decoder 13 are provided. Further, the control circuit 14 has a write enable signal / WE and a chip enable signal which are external control signals. / CE and output enable signal / OE are applied. The address latch enable signal ALE is applied from the control circuit 14 to the address register 6 (A0 to A17).

FIG. 4 is a sectional view of the memory cell shown in FIG. Referring to FIG. 4, the memory cell is a semiconductor substrate 15
It includes a floating gate 16, a control gate 17, a source diffusion region 18, and a drain diffusion region 19 formed above. The oxide film thickness between the floating gate 16 and the substrate 15 is thin, for example, about 100 angstroms, and electrons of the floating gate 16 can be moved by utilizing the tunnel phenomenon.

FIG. 5 is a diagram showing a part of the configuration of the memory cell array shown in FIG. This will be described below with reference to FIG. The memory cell array has its drain connected to the bit line 24 and its control gate connected to the word line 25. The word line 25 is connected to the X decoder 4, and the bit line 24 is connected to the I / O line 27 via the Y gate transistor 26 to which the output of the Y decoder 5 is input. The sense amplifier 8 and the write circuit 7 are connected to the I / O line 27, and the source line 28 is connected to the source line switch 3.

Next, the operation of the conventional flash memory will be described with reference to FIGS. First, the operation of writing data in the memory cell surrounded by the dotted line shown in FIG. 5 will be described. The write circuit 7 is activated according to the data input from the outside, and the I / O line 27
Is supplied with a program voltage Vpp (about 7V). At the same time, the Y decoder 5 and the X decoder 4 are driven by the address signal.
Y gate 26 and word line 25 are selected via Vpp
Is applied to the memory cell. The source line 28 is grounded by the source line switch 3 during programming. In this manner, the current flows only in the memory cell surrounded by the dotted line shown in FIG. 5 which is selected by the X and Y decoders,
Hot electrons are generated and the threshold voltage becomes high.

On the other hand, erasing is performed as follows.
First, the X decoder 4 and the Y decoder 5 are deactivated,
All memory cells are deselected, that is, the word line 25 of each memory cell is grounded and the drain is open. On the other hand, a high voltage is applied to the source line 28 by the source line switch 3. In this way, the threshold value of the memory cell array shifts to the lower side due to the tunnel phenomenon.

Since the source line is divided for each block, it can be divided and erased for each block by the block selection address.

Next, the read operation will be described. Similar to the write operation, reading of the memory cell surrounded by the dotted line in FIG. 5 will be described. First, the address signal is decoded by the Y decoder 5 and the X decoder 4, and the selected Y gate 26 and word line 25 are set to the “H” level. At this time, the source line 28 is grounded by the source line switch 3. In this way, if data is written in the memory cell and the threshold value is high,
Even if a "H" level signal is applied to the control gate of the memory cell from the word line 25, the memory cell does not turn on, and no current flows from the bit line 24 to the source line 28.

On the other hand, when the memory cell is erased, the memory cell is turned on, so that a current flows from the bit line 24 to the source line 28. The sense amplifier 8 detects whether or not a current flows through the memory cell, and the read data "1" and "0" are obtained. In this way, writing and reading of data in the flash memory are performed.

Next, write and erase operations will be described with reference to FIGS. 3, 6, 7, 8, 9 and 10. Conventionally, in a flash memory, mode setting for writing and erasing is performed by a combination of input data. That is, the operation mode is set by the rising data of the write enable signal / WE. First, the case of writing will be described with reference to FIGS. 3, 7, and 9. First, Vcc and Vpp are raised in step (abbreviated as S in the drawing) S1, and subsequently, write enable signal / WE is lowered in step S2.
Thereafter, the input data 40H (D0 to D15) is latched in the command latch 12 at the rising timing of the write enable signal / WE. After that, the input data is decoded by the command decoder 13, and the operation mode is set to the program mode.

Next, in step S3, the write enable signal / WE is fallen again, the address signal from the outside is latched in the address register 6, and the data DIN (D0-D0-D0) is latched at the rising edge of the write enable signal / WE.
D15) is latched.

Next, in step S4, a program pulse is generated from the program voltage generation circuit 10 and X
It is applied to the decoder 4 and the Y decoder 5. In this way, the program is executed as described above.

Next, in step S5, the write enable signal / WE is lowered and the input data (C0H
) Is input and latched in the command latch 12.

Then, in step S5, the operation mode becomes the program verify mode with the rise of the write enable signal / WE. At this time, a verify voltage generating circuit 11 generates a program verify voltage (up to 6.5 V) inside the chip and applies it to the X decoder 4 and the Y decoder 5. Therefore, the voltage applied to the control gate of the memory cell array 1 becomes higher than that at the time of normal reading (up to 5 V), and those exhibiting an insufficient threshold shift are easily turned on, and a write failure can be found.

Next, in step S7, reading is performed,
Check the write data. If it is determined in step S8 that the writing is defective, the processes of steps S2 to S7 are performed again to perform writing. If the writing is done normally, the mode is set to the reading mode in step S9, and the program is ended.

Next, the chip collective erase operation will be described with reference to FIGS. First, in step S10, Vcc and Vpp are raised, and then "0" is written in all bits in step S11 according to the above-described write flow process. This is because the memory cell array 1 is over-erased when the erased memory cell is further erased.

Next, the write enable signal / WE is lowered and an erase command is input. That is, step S12
Input the input data 20H at.

Then, in step 13, an erase confirmation command is input (input data 20H is input again), and in step S14, an erase pulse is internally generated at the rising of the write enable signal / WE. That is, Vpp is applied to the source of the memory cell array 1 via the source line switch 3. After that, V is applied to the source line 28 until the write enable signal / WE falls.
pp is applied. At the same time, with the fall, the address is again latched in the address register 6.

Next, in step S15, the erase verify command (A0H) is input at the rise of the write enable signal / WE, and the erase verify mode is set.

In the erase verify mode, the verify voltage generating circuit 11 performs erase verify (up to 3.2 V).
Are applied to the X decoder 4 and the Y gate 2. For this reason,
The voltage applied to the control gate of the memory cell array 1 becomes lower than that during normal reading (5V), and it becomes difficult to turn on memory cells that are not sufficiently erased. In this way, erasure can be confirmed more reliably.

Next, in step S16, reading is performed to confirm the actual erasure (electrical level of erased state).

Next, if it is determined in step S17 that the erasure is insufficient, the erasure is further repeated,
If the erase is sufficient, the address is incremented in step S18, and the erase data of the next address is verified.

Next, when it is determined in step S19 that the verified address is the final one, the operation mode is set to the read mode in step S20, and a series of operations is ended.

Below, referring to FIGS. 3, 8 and 11,
The block erase operation will be described. First, step S
At 10, Vcc and Vpp are raised, and subsequently, in accordance with the above-described write flow process, "0" is written in the block to be erased in step S11. Next, the write enable signal / WE is lowered and a block erase command is input. That is, in step S12, (60H
) Is entered. Then, in step 12a, the block address is input.

Next, in step 13, an erase confirmation command is input and the write enable signal / WE is entered.
An erasing pulse is internally generated at the rising edge of. That is, the memory cell array 1 via the source line switch 3
Vpp is applied to the source of the block selected by the block address input in step S12a. After that, at the fall of the write enable signal / WE, the address is also latched in the address register 6 again. At step S15, the erase verify command (A0
H) is input and the erase verify mode is set.

In the erase verify mode, the erase verify voltage (up to 3.2 V) is generated by the verify voltage generating circuit.
Are applied to the X decoder 4 and the Y gate 2. For this reason,
The voltage applied to the control gate of the memory cell array becomes lower than that during normal reading (5 V), and it becomes difficult to turn on memory cells that are not sufficiently erased. In this way
It becomes possible to confirm the erasure more reliably.

Next, in step S16, reading is performed to confirm the actual erasure (electrical level of erased state).

If it is determined in step S17 that the erasure is insufficient, the erasing is repeated, and if the erasing is sufficient, the address is incremented in step S18 and the erase data of the next address is verified. When it is determined in step S19 that the verified address is the final address of the selected block, the operation mode is set to the read mode in step S20, and the series of operations ends.

[0030]

The conventional flash memory is configured as described above, and the block selection address must be designated even in the block erase verify after the block erase.

The present invention has been made to solve the above problems, and provides a non-volatile semiconductor memory device which does not require addressing for block selection in block erase verify after block erase. The purpose is to

[0032]

A non-volatile semiconductor memory device according to the present invention includes a plurality of non-volatile memory transistors arranged in an array in at least row and column directions and capable of electrically writing and erasing information. Memory cell, an address signal latch circuit for latching an input address signal, and an address signal input from the address signal latch circuit are decoded to select a memory cell in the row direction of the memory cell array. A row selection unit, a column selection unit for decoding the address signal input from the address signal latch circuit, and selecting a memory cell in the column direction of the memory cell array, and an output of the column selection unit according to the output of the column selection unit. A unit block erasing unit for erasing every unit block of the memory cell is also provided. It is.

According to the present invention, in the semiconductor memory device, the unit block erasing means receives a signal generated after block erasing as an input to generate an ALE2 signal, and outputs a column selection address signal according to the ALE2 signal. It is something that is supposed to be done.

According to the present invention, in the semiconductor memory device, the address signal latch circuit holds a column control address in response to an ALE2 signal from a control circuit for selecting a required block in the memory cell array. It has a selection address buffer circuit.

[0035]

The nonvolatile semiconductor memory device according to the present invention is
Since the block address is latched by the block selection address latch circuit having the ALE2 signal generation circuit and the block selection address buffer circuit, the block selection address for block erase verification after block erase can be eliminated. .

Further, the number of processing steps in the control circuit for executing the unit block erasing means can be reduced.

[0037]

【Example】

Example 1. FIG. 1 is a schematic block diagram showing the overall structure of a nonvolatile semiconductor memory device according to an embodiment of the present invention. The embodiment shown in FIG. 1 is the same as the conventional example shown in FIG. 3 except for the following points. That is, the AL in the control circuit 14
An E2 signal generation circuit 200 is provided, and the ALE2 signal generated by the ALE2 signal generation circuit 200 is used as a block selection address buffer circuit A13 in the address register 6.
Given to A17. From the ALE2 signal generation circuit 200, the block selection address buffer circuits A13 to A13
The circuits up to 17 are referred to as block selection address latch circuits.

The conventional ALE signal generating circuit 10
The ALE signal generated at 0 is the address register 6
It is applied only to the internal address signal buffer circuits A0 to A12.

FIG. 2A is a concrete block diagram of the ALE signal generating circuit 100 in the address signal latch circuit. Referring to FIG. 2A, the signal A is an "L" level at the time of reading, and the signals B and C are pulses output at the falling edge of / WE. Therefore, by this circuit, ALE becomes "H" level at the time of reading or the fall of / WE.

FIG. 2B is a concrete block diagram of the ALE2 signal generation circuit 200 in the block selection address latch circuit. Referring to FIG. 2 (b), the signal A is an "L" level at the time of reading, and the signals B and C are pulses output at the falling edge of / WE. The signal D is a signal output after block erasing, and "H" is output after block erasing. Therefore, by this circuit, when reading or when / WE falls, A
The LE2 signal becomes "H", and the ALE2 signal becomes "L" after block erasing.

2C and 2D are concrete block diagrams of the address register circuit 6 shown in FIG.
2 is a circuit diagram of a block selection address buffer (register) circuit, and FIG. 2D is a circuit diagram of an X, Y selection address register circuit.

In FIG. 2 (c), CEB is a chip enable signal, Q1, Q2, Q3 and Q4 are p channel transistors, Q11, Q12, Q13 and Q14 are n channel transistors, I1 to I5 are inverters, and Add and / Add. Is an address signal.

In FIG. 2D, CEB is a chip enable signal, Q1, Q2, Q3 and Q4 are p channel transistors, Q11, Q12, Q13 and Q14 are n channel transistors, I6 to I10 are inverters, and Add and / Add. Is an address signal.

FIG. 2 (c) The ALE2 signal, the CEB signal, and the block selection address signal are input to the block selection address register, and the address input to the block selection address signal end is latched according to the condition of the ALE2 signal. , Or unlatched. That is, as described above, the ALE2 becomes "L" only after the block is erased, and the address is latched.

In addition, the ALE signal, the CEB signal, the X, Y selection address signal are input to the X, Y selection address register of FIG. 2 (d), and the X, Y selection address signal ends at the ALE signal condition. The input address is a latch,
Or unlatched. That is, as described above, ALE becomes “L” and the address is latched except at the time of reading or / WE falling, but at the time of reading or / W.
When E falls, the address is not latched. That is, after block erasing, ALE becomes "H" and the address is not latched.

In this embodiment, since the block address is latched by the block selection address latch circuit, it is possible to eliminate the need to specify the block selection address for block erase verify after block erase. Is obtained.

[0047]

As described above, according to the semiconductor memory device of the present invention, since the block address is latched by the block selection address latch circuit, the block is erased during the block erase verify after the block erase. It is not necessary to specify the selection address, which has the effect of simplifying the operation.

Further, there is an effect that the number of processing steps in the control circuit for executing the unit block erasing means can be reduced and the processing speed can be improved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a specific block diagram of an address signal latch circuit of the above embodiment.

FIG. 3 is a schematic block diagram of a conventional nonvolatile semiconductor memory device using a flash memory.

FIG. 4 is a cross-sectional view of a memory cell of a general flash memory.

FIG. 5 is a circuit diagram around a memory cell array.

FIG. 6 is a flowchart for explaining a chip collective erase operation of a conventional flash memory.

FIG. 7 is a flowchart for explaining a program operation of a conventional flash memory.

FIG. 8 is a flowchart for explaining a block erase operation of a conventional flash memory.

FIG. 9 is an operation timing chart for explaining a program operation of a conventional flash memory.

FIG. 10 is an operation timing chart for explaining a chip collective erase operation of a conventional flash memory.

FIG. 11 is an operation timing chart for explaining a block erase operation of a conventional flash memory.

[Explanation of symbols]

 1 Memory Cell Array 2 Y Gate 3 Source Line Switch 4 X Decoder 5 Y Decoder 6 Address Register 8 Sense Amplifier 9 Input / Output Buffer 10 Program Voltage Generating Circuit 11 Verify Voltage Generating Circuit 12 Command Latch 13 Command Decoder 14 Control Circuit

Claims (3)

[Claims] 1. A plurality of memory cells, which are arranged in an array at least in the row and column directions and include a nonvolatile memory transistor capable of electrically writing and erasing information, and an address signal for latching an input address signal. A latch circuit, row selecting means for decoding the address signal input from the address signal latch circuit and selecting a memory cell in the row direction of the memory cell array, and an address input from the address signal latch circuit. A column selection unit for decoding a signal and selecting a memory cell in the column direction of the memory cell array, and a unit block for erasing for each unit block of the memory cell array according to the output of the column selection unit. A non-volatile semiconductor memory device comprising: an erasing unit. 2. The semiconductor memory device according to claim 1, wherein the unit block erasing means receives a signal generated after block erasing, and thereby generates an ALE2 signal,
A semiconductor memory device, which outputs a column selection address signal in response to the ALE2 signal. 3. The semiconductor memory device according to claim 1, wherein the address signal latch circuit performs A selection from a control circuit for selecting a required block in the memory cell array.
A semiconductor memory device having a block selection address buffer circuit for holding a column control address according to an LE2 signal.