JPH06282518A - Information processor - Google Patents

Abstract

PURPOSE:To facilitate the primary investigation of an abnormal portion even when plural abnormalities are overlapped and to prevent the lowering of working ratio by detecting the state of a device card by the reply signal for the device card and the detection signal of the presence or absence of the mounting of the device card. CONSTITUTION:A reply control generation logic 10 controls and generates the reply signal for a device card 3. The logic 10 outputs the reply signal or a no-reply signal to an output signal line 13. In a buffer 11, the signal of a device card mounting state signal line 9 and the output signal of the logic 10 are inputted. The information on the state of the device card 3 is transmitted as the output signal of the buffer 11 to an exclusive information line 12, and the no-reply signal and a device card non-mounting signal are transmitted as each signal for interruption to a CPU card 2. Thus, the CPU card 2 is capable of deciding the abnormality of the device card 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit card (hereinafter referred to as a CPU card) having a plurality of mounting slots.
Also, the present invention relates to an information processing apparatus including a motherboard to which various device cards are attached and which are connected by a system bus.

[0002]

2. Description of the Related Art FIG. 17 is a block diagram showing a conventional motherboard. In the figure, 1 is a motherboard, 2 is C
PU card, 3 is a device card, 4 is a system bus to which the CPU card 2 and device card 3 are connected,
5 is an address line for connecting the device card 3 to the system bus 4, 6 is a space independent of the memory area of the CPU card 2, for example, an input / output area,
It is operated by bit manipulation of data in the input / output address from the input / output area, and a control signal for controlling permission / prohibition of address code supply is generated for each mounting slot in which each device card 3 is mounted. A bank memory as an address supply control means, 7 is an address buffer which is inserted into each address line 5 from the system bus 4 to each device card 3, and is opened / closed by a control signal from the bank memory 6, and 8 is a bank. An address supply control line for transmitting the control signal generated by the memory 6 to the address buffer 7.

Next, the operation of this conventional example will be described.
In FIG. 17, the CPU card 2 operates the bank memory 6 assigned to the input / output area by the bit operation of data in the input / output address from the input / output area, and the bank memory 6 is attached with the device card 3 to be controlled. A group of mounting slots including the mounted mounting slots is selected, and a control signal for controlling permission / prohibition of the address code supply is generated and sent to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes "permitted" only in each of the selected mounting slots, the predetermined address buffer 7 is opened, and the signal on the address line 5 from the CPU card 2 is opened. However, it can be supplied to the predetermined device card 3 attached to the selected mounting slot via the address buffer 7.

Here, the CPU card 2 sends the address code to which the device card 3 to be controlled is assigned to the address line 5. This address code is
The device card 3 is supplied only to the above-mentioned group of device cards 3 through the address buffer 7 which is opened by the control signal from the bank memory 6, and the predetermined address code in the device card 3 is assigned.
Only becomes controllable. Therefore, even if there is a device card 3 to which the same address code is assigned in addition to the group of device cards 3, the control signal from the address supply control line 8 becomes "inhibited" and the address buffer in the closed state is closed. The device card 3 to which 7 corresponds does not become controllable, which makes it possible to allocate a plurality of device cards 3 to the same address code. In this case, it is not necessary to modify the hardware of each device card 3, and the conventional device card 3 can be used as it is.

[0005]

Since the conventional information processing apparatus is configured as described above, information (data) is normal even if various device cards are not mounted or hardware troubles occur. Even if I / O cannot be performed, the CPU card must process as the same abnormality in both cases, and when multiple abnormalities as described above overlap, it becomes very difficult to find the original abnormal location. However, there was a problem that the operating rate was expected to drop significantly.

The present invention has been made in order to solve the above problems, and makes it possible to determine the specific cause of a failure, such as what kind of trouble has occurred, and therefore the equipment restoration time is greatly shortened. An object of the present invention is to obtain an information processing device that improves the operating rate of equipment.

[0007]

As shown in FIG. 1, an information processing apparatus according to the first aspect of the present invention includes reply management generation means (management management means for managing generation of reply signals for various device cards (device card 3 and the like)). The reply management generating logic 10), the reply signal and the presence / absence detection signal of the various device cards are used to detect the states of the various device cards, and the central processing unit card (CPU) is detected.
Means for transmitting information about the status of the device card 3 to the card 2) as an interrupt signal (buffer 1)
1) and are provided. In the information processing apparatus according to the second aspect of the present invention, as shown in FIG. 4, an address buffer 7 for setting whether or not to send an address code to the device card is housed in each of the various device cards 3. As shown in FIG. 5, the information processing apparatus according to the third aspect of the present invention includes reply management generation means (reply / no reply signal generation circuit 30 and the like) that manages and generates reply signals for the various device cards 3 described above. It was stored in each device card 3. The information processing apparatus according to the fourth aspect of the present invention, as shown in FIG. 6, has an address buffer 7 for setting whether or not to send an address code to the device card 3.
And reply management generation means (reply / no reply signal generation circuit 30) for managing and generating reply signals for the various device cards 3 are housed in each device card 3.

In the information processing apparatus according to the fifth aspect of the present invention, as shown in FIG. 10, the central processing unit card (CPU card 2) and the address code sent by the central processing unit card are stored in the address line of the system bus. In the information processing apparatus including the motherboard 1 for supplying the predetermined device card 3 to the predetermined device card 3 via the address buffer 7 in the open state and controlling the device card to which the address code is assigned, the various device cards Reply management generation means (reply management generation logic 10) that manages and generates a reply signal to the device card, and a device card status that detects the status of the various device cards based on the reply signal and the presence / absence detection signal of the various device cards. Detecting means (buffer 11) and this device card status detection The detection result from the stage, the central processing unit card is to comprise a memory means for storing in a predetermined area to poll (bank memory 6). In the information processing apparatus according to the sixth aspect of the invention, the reply management generating means and the address buffer are housed in the motherboard 1. In the information processing apparatus according to the seventh aspect of the invention, the reply management generating means is housed in the mother board 1 and the address buffer is housed in the device card 3. In the information processing apparatus according to the eighth aspect of the invention, the reply management generating means is housed in the device card 3 and the address buffer is housed in the motherboard 1. An information processing apparatus according to the ninth invention includes the reply management generating means and the address buffer,
The device card is stored in the device card.

[0009]

In the information processing apparatus according to the first aspect of the present invention, reply management generation means (reply management generation logic 10) manages and generates reply signals for various device cards 3, and the reply signals and the various device cards described above are generated. Based on the mounting presence / absence detection signal, the means (buffer 11) detects the states of the various device cards, and information about the states of the device cards is sent to the central processing unit card (CPU card 2) as an interrupt signal. Transmitted. In the information processing apparatus according to the second aspect of the present invention, whether or not to send the address code to the various device cards is set by the address buffer 7 housed in the various device cards 3. In the information processing apparatus according to the third aspect of the present invention, the reply management generation means (reply / no reply signal generation circuit 30) housed in various device cards 3 manages and generates reply signals for the various device cards. . In the information processing apparatus according to the fourth aspect of the present invention, whether or not to send the address code to the various device cards is set by the address buffer 7 housed in the various device cards 3, The reply management and generation means (reply / no reply signal generation circuit 30) housed in the management and management means generates and manages reply signals for the various device cards.

The information processing apparatus according to the fifth aspect of the present invention includes reply management generation means (reply management generation logic 10).
Thus, reply signals for the above various device cards are managed and generated. Next, the device card state detection means (buffer 11) detects the states of the various device cards by the reply signal and the presence / absence detection signal of the various device cards. Finally, the storage means (bank memory 6) stores the detection result from the device card state detection means in a predetermined area polled by the central processing unit card. In the information processing apparatus according to the sixth aspect of the invention, the place for accommodating the reply management generating means and the address buffer is inside the motherboard 1. The information processing apparatus according to the seventh invention is
A place for storing the reply management generating means is set in the motherboard 1, and a place for storing the address buffer is set in the device card 3. In the information processing apparatus according to the eighth aspect of the present invention, the place for storing the reply management generating means is in the device card 3, and the place for storing the address buffer is in the mother board 1.
The information processing apparatus according to the ninth aspect of the invention stores the reply management generating means and the address buffer in the device card.

[0011]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a circuit block diagram of an information processing apparatus showing a first embodiment of the present invention, FIG. 8 is a time chart of each signal line of the present invention, and FIG. 9 is a buffer for transmitting a state of a device card of the present invention to a CPU card 2. 28 is a circuit block diagram of input / output states of 28, and the same components as those in FIG. 1 are denoted by the same reference numerals. In FIGS. 1, 8 and 9, 1 is a motherboard, 2 is a CPU card as a central processing unit card,
3 is a device card, 4 is a system bus, 5 is an address line, 6 is a space independent of the memory area of the CPU card 2, for example, an input / output area, and bit operation of data in the input / output address from the input / output area is performed. Operated by the bank memory 7 for generating a control signal for controlling permission / prohibition of address code supply for each mounting slot to which each device card 3 is attached, and 7 is an address line 5 from the system bus 4 to each device card 3. Address buffers which are inserted into each of the above and are opened / closed by the control signal from the bank memory 6, 8 is an address supply control line for transmitting the control signal generated by the bank memory 6 to the address buffer 7, and 9 is a mounting state of the device card 3. The device card mounting state signal line for transmitting the message 10 to the device card 3 A reply management generation logic as a reply management generation unit that manages and generates the reply signal 17, 11 is a signal of the device card mounting state signal line 9 and an output signal of the reply signal management generation logic 10 for the device card 3 CP state
A buffer for transmitting to the U card 2, 12 is a dedicated information line for directly transmitting information from the buffer 11 for transmitting the state of the device card 3 to the CPU card 2 to the CPU card 2, 13
Is an output signal line of the reply management generation logic 10 that manages and generates a reply signal 17 for the device card 3, 14 is an address line signal, 15 is a data line signal, 16 is a command (control command) line signal, 1
Reference numeral 7 is a reply signal, 18 is a reply management generation logic 10 that manages and generates a reply signal 17 for the device card 3, and a no reply timer signal for making a no reply judgment of the device card 3, 19 is a device card 3 The device card mounting status signal that conveys the mounting status of the device card, and 22 is the CP when the device card no reply
An interrupt signal to the U card 2 and an interrupt signal 23 to the CPU card 2 when the device card 3 is not mounted. Reference numeral 24 is a memory selection signal of the same number as the device card address type, which is output from the bank memory 6. 25 inputs the device card reply signal 17, the device card no reply signal 18 and the device card unmounted signal 19 to the buffer / memory 28 which transmits to the CPU card 2, and enables the output signals of the interrupt signals 22 and 23. This signal 25 is output from the bank memory 6 as an address supply control means. Then, 28 is a buffer for transmitting the state of the device card 3 to the CPU card 2 from the device card mounting state signal 19 of the device card mounting state signal line 9 and the output signals 17 and 18 of the reply signal management generation logic 10 for the device card 3. Memory, buffer 1
This is a part corresponding to 1.

FIG. 2 is a perspective view showing a concrete example of a mother board used in the device of the first embodiment. In FIG. 2, connectors (female) 51a to 51d for connecting device cards are attached to the mother board 1. By mating the corresponding connectors (male) of the device card 3, the mother board 1 and the device are connected. Connect with the card 3. Further, FIG. 3 shows a connecting portion of the mother board 1 and the device card. In FIG. 3, the connector 51a on the motherboard 1 side
Signals of the card mounting state signal line 9 are supplied to predetermined connection terminals (pins) to the terminals 51 to 51d. on the other hand,
The device card 3 side is provided with a circuit for setting the "L" (OV) level when the connectors 51a to 51d of the motherboard 1 are connected. Therefore, for example, when the connector 53 of the device card 3 is mated with the connector 51a of the motherboard 1, the signal of the card mounting state signal line 9 at a predetermined connection terminal on the motherboard 1 side becomes "L" (OV) level, This “L” level signal is transmitted to the buffer 11. Then, the insertion of the device card at the position of the connector 51a of the motherboard 1 is detected by the CPU (not shown) via the buffer 11. In this way, when each device card 3 is mounted on the mother board 1, for example, an “L” (OV) level signal is generated as an independent signal from each device card 3, and the signal is input to the buffer 11. . And
When accessing a device card from a CPU (not shown), the corresponding device card 3
When the non-mounting and no reply to the motherboard 1 are detected, the buffer 11 generates an interrupt signal to the CPU.

Next, the operation of the apparatus according to the first embodiment will be described. In FIG. 1, C as a central processing unit card
The PU card 2 operates the bank memory 6 assigned to the input / output area by bit manipulation of the data in the input / output address from the input / output area, and the bank memory 6 is a mounting slot in which the device card 3 to be controlled is attached. A group of mounting slots including the above is selected, and a control signal for controlling permission / prohibition of the address code supply is generated and sent to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes "permitted" and the predetermined address buffer 7 is opened only in each of the selected mounting slots, and the signal on the address line 5 is in this open state. It becomes possible to supply the data to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2 sends the address code to which the device card 3 to be controlled is assigned to the address line 5. This address code is supplied only to the above-mentioned group of device cards 3 via the address buffer 7 which is in an open state by the control signal from the bank memory 6, and only the device card 3 to which the address code is assigned is supplied. Can be controlled. Therefore, in addition to the group of device cards 3, the device cards 3 to which the same address code is assigned
However, if the groups are different, the device card 3 for which the control signal from the address supply control line 8 is "inhibited" will not be controllable. It becomes possible to allocate the device card 3 of. 8 and 9, the address 14, the data 15 and the command 16 from the CPU card 2
Access to the device card 3 is performed by
In FIGS. 8 and 9, for example, in the case of WR (write operation), for example, a signal 19 of “L” when the device card 3 is mounted, and “H” when the device card 3 is not mounted It is output via the device card mounting state signal line 9 that conveys the mounting state.

The reply management generation logic 10 for managing and generating the reply signal 17 for the device card 3 outputs the reply signal 17 for the device card 3 to the output signal line 13 of the reply management and generation logic 10. Specifically, the reply signal 17 is used at the time of reply, and the device card 3 is used at the time of no reply.
A reply detection timer detection signal 18 is used in the reply management generation logic 10 that manages and generates the reply signal 17 for As a result, the buffer 11 (buffer / buffer) for transmitting the state of the device card 3 to the CPU card 2
Information about the state of the device card 3 through the memory 28) is sent to the CPU card 2 as an output signal of the buffer 11 which is transmitted to the CPU card 2, and the dedicated information line 1
2, the no reply signal and the device card unmounted signal are transmitted to the CPU card 2 as interrupt signals 22 and 23, respectively. That is, in the unlikely event that no reply and no device card are mounted, the system bus signal 22 of reply-related information is, for example, "H".
Then, the system bus signal 2 of device card mounting related information
3 becomes "H", and the rising signal of each of these signals (the falling signal of each signal by reversing the significance of the signal) is C
It becomes the signals 22 and 23 for interruption to the PU card 2, and C
The PU card 2 can determine the abnormality of the device card 3. In this case, it is not necessary to modify the hardware of each device card 3, and the conventional device card 3 can be used as it is.

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. Second Embodiment FIG. 4 is a circuit block diagram of an information processing apparatus showing a second embodiment of the present invention, and the same components as those in FIG. In the second embodiment, the address buffer 7 is housed in the device card 3, and other configurations and operations are the same as those described with reference to FIGS. 1, 8 and 9. With such a configuration, the configuration on the motherboard 1 side can be simplified.

Next, the operation of the apparatus according to the second embodiment will be described. In FIG. 4, a CPU as a central processing unit card
The card 2 operates the bank memory 6 assigned to the input / output area by bit operation of the data in the input / output address from the input / output area, and the bank memory 6 is mounted with the device card 3 to be controlled. A group of mounting slots including slots is selected, and a control signal for controlling permission / prohibition of address code supply is generated and sent to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and is supplied to the device card 3 only in each of the selected mounting slots, the address buffer 7 in the device card 3 is opened, and the address The signal on the line 5 can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2 sends the address code assigned to the device card 3 to be controlled to the address line 5
Send to. This address code is supplied to the address buffer 7 in the device card 3 in the open state by the control signal from the bank memory 6, and only the device card 3 to which the corresponding address code is assigned can be controlled. . Therefore, even if there is a device card 3 to which the same address code is assigned in addition to the group of device cards 3, the device card 3 for which the control signal from the address supply control line 8 is “prohibited” is controlled. This is not possible, and this makes it possible to allocate a plurality of device cards 3 to the same address code.

In FIG. 8, the device card 3 is accessed by the address 14, data 15 and command 16 from the CPU card 2, and in FIG. 8 and FIG. 9, for example, in the case of WR (write operation), A signal 19 of “L” if the device card 3 is mounted, and “H” if not mounted is output through the card mounting state signal line 9 for transmitting the mounting state of the device card 3. The reply management generation logic 10 that manages and generates the reply signal 17 for the device card 3 outputs the reply signal 17 for the device card 3 to the output signal 13 of the reply management generation logic 10. More specifically, a reply signal 17 is used at the time of reply, and a no reply determination timer detection signal 18 is used in the reply management generation logic 10 that manages and generates the reply signal for the device card 3 at the time of no reply. With this, the buffer 1 for transmitting the state of the device card 3 to the CPU card 2
1 (buffer / memory 28) through device card 3
For information about the status of the CPU card 2
As the output signal of the buffer 11 transmitted to the card 2, the no reply signal and the device card unmounted signal are transmitted to the CPU card 2 as the interrupt signals 22 and 23 through the dedicated information line 12. That is, in the unlikely event that no reply and no device card are mounted, the system bus signal of reply-related information is, for example, "H",
The system bus signal of the device card mounting related information becomes "H", and the rising signal of each of these signals (the falling signal of each signal with the significance of the signal reversed) is C.
It becomes the signals 22 and 23 for interruption to the PU card 2, and C
The PU card 2 can determine the abnormality of the device card 3. In this case, each device card 3 needs a special circuit for the address buffer 7 and the like.

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing an apparatus according to Embodiment 3 of the present invention. In FIG. 5, 26 is a reply / no reply signal output line from each device card 3, and 30 is a reply / reply as a reply management generation means.
It is a no reply signal generation circuit.

FIG. 6 is a circuit block diagram showing the function of generating a reply / no reply signal from the device card in the device of the third embodiment. In FIG.
40 is an address coincidence circuit, 41 is a timer, 42 is a command signal, 43 is an own card enable signal, 44 is an address signal group, and 45 is a device card address setting switch. For example, when a CPU (not shown) accesses each device card, the reply signal is generated by determining that the device card is the own device card, guaranteeing the external access time, and then generating the reply signal. That is, the address matching circuit 40 generates the own card enable signal 43 on the device card 3, and sends it to the buffer 11 of the motherboard 1 as a reply signal after the timer (after the time when the external access time can be guaranteed). However, the no reply signal is provided by the function of the buffer 11 on the motherboard 1. That is, when the buffer 11 monitors the reply signal, the reply signal is not returned from the device card 3 after the address signal (address signal group 44) is output, that is, after a certain time has elapsed (set to be larger than the timer time). , No reply is determined. When the CPU (not shown) accesses each device card, the buffer 11 on the mother board sends CP when the mounting signal of the device card is normal and the reply signal is valid.
Do not generate an interrupt signal in U. However, if the corresponding device card is not mounted or is mounted but no reply is determined, an interrupt signal is generated by notifying the CPU. The CPU can confirm what kind of trouble caused the interrupt by looking at these status states during the interrupt processing.

Next, the operation of the apparatus of the third embodiment will be described. In FIG. 5, the CPU as the central processing unit card
The card 2 operates the bank memory 6 assigned to the input / output area by bit operation of the data in the input / output address from the input / output area, and the bank memory 6 is mounted with the device card 3 to be controlled. A group of mounting slots including slots is selected, and a control signal for controlling permission / prohibition of address code supply is generated and sent to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes "permitted" only in each of the selected mounting slots, and the address buffer 7
Is opened, and the signal on the address line 5 can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2 sends the address code assigned to the device card 3 to be controlled to the address line 5
Send to. This address code is supplied only to the group of device cards 3 via the address buffer 7 which is in an open state by the control signal from the bank memory 6, and only the device card 3 to which the address code is assigned is supplied. Can be controlled. Therefore, even if there is a device card 3 to which the same address code is assigned in addition to the group of device cards 3, the device card 3 for which the control signal from the address supply control line 8 is “prohibited” is controlled. This is not possible, and this makes it possible to allocate a plurality of device cards 3 to the same address code.

In FIG. 5, the device card 3 is accessed by the address 14, the data 15 and the command 16 from the CPU card 2. In FIGS. 8 and 9, for example, in the case of WR (write operation), the device card 3 The signal 19 of "L" when the device is mounted, and "H" when the device is not mounted is output through the device card mounting state signal line 9 for transmitting the mounting state of the device card 3. The reply / no reply signal to the device card 3 is directly supplied through the reply / no reply signal output line 26 from each device card 3. More specifically, the reply signal 17 at the time of reply, and the reply management generation logic 10 for managing and generating the reply signal 17 supported in the device card 3 at the time of no reply (corresponding to the reply / no reply signal generation circuit 3).
The no-reply judgment timer detection signal 18 in 0) is used. With this, the buffer 11 (buffer / memory 28) for transmitting the state of the device card 3 to the CPU card 2
For information on the status of the device card 3 via
As an output signal of the buffer 11 transmitted to the CPU card 2 to the PU card 2, a no reply signal and a device card unmounted signal are transmitted through the dedicated information line 12 to the CPU.
The interrupt signals 22 and 23 are transmitted to the card 2. As a result, in the unlikely event that no reply occurs and the device card is not mounted, the system bus signal of reply-related information becomes "H" and the system bus signal of device card mounting-related information becomes "H". The rising signal (the falling signal of each signal with the significance of the signal reversed) is the interrupt signal 22 to the CPU card 2,
23, the CPU card 2 can determine the abnormality of the device card 3. In the case of the third embodiment, each device card 3 requires a special circuit corresponding to the reply management generation logic 10 such as the reply / no reply signal generation circuit 30, but the configuration on the motherboard 1 side can be simplified.

Example 4. Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a fourth embodiment of the present invention. The symbols in FIG. 7 are the same as those in the first embodiment.

Next, the operation of the apparatus according to the fourth embodiment will be described. In FIG. 7, the CPU card 2 operates the bank memory 6 assigned to the input / output area by bit operation of the data in the input / output address from the input / output area, and the bank memory 6 is attached with the device card 3 to be controlled. A group of mounting slots including the mounting slots are selected, and a control signal for controlling permission / prohibition of address code supply is generated and sent to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and is supplied to the device card 3 only in each of the selected mounting slots, the address buffer 7 in the device card 3 is opened, and the address The signal on the line 5 can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2
The address code to which the device card 3 to be controlled is assigned is sent to the address line 5. This address code is supplied to the address buffer 7 in the open device card 3 by the control signal from the bank memory 6, and only the device card 3 to which the relevant address code is assigned can be controlled. . Therefore, even if there is a device card 3 to which the same address code is assigned in addition to the group of device cards 3, the device card 3 for which the control signal from the address supply control line 8 is “prohibited” is controlled. This is not possible, and this makes it possible to allocate a plurality of device cards 3 to the same address code.

In FIG. 8, access to the device card 3 is performed by the address 14, data 15 and command 16 from the CPU card 2. In FIG. 8 and FIG. 9, for example, in the case of WR (write operation), the device A device card mounting state signal 19 of “L” if the card 3 is mounted and “H” if not mounted is output through the device card mounting state signal line 9 for transmitting the mounting state of the device card 3. . The reply / no reply signal to the device card 3 is directly supplied through the reply / no reply signal output line 26 from each device card 3. Specifically, no reply in the reply management generation logic 10 equivalent (reply / no reply signal generation circuit 30) that manages and generates the reply signal 17 at the time of reply and the reply signal 17 supported in the device card 3 at the time of no reply. The judgment timer detection signal 18 is used. As a result, the buffer 11 (buffer / memory 28) for transmitting the state of the device card 3 to the CPU card 2 is passed, and information on the state of the device card 3 is output to the CPU card 2 by the buffer 11 for transmitting to the CPU card 2. As signals, the no reply signal and the device card unmounted signal are transmitted to the CPU card 2 as interrupt signals 22 and 23 through the dedicated information line 12. As a result, if no reply occurs and the device card is not mounted, the system bus signal of reply-related information is, for example, "H", and the system bus signal of device-card mounting-related information is "H".
Thus, the rising signal of each signal (the falling signal of each signal with the significance of the signal being reversed) is the CPU card 2
The interrupt signals 22 and 23 are sent to the CPU card 2, and the CPU card 2 can determine the abnormality of the device card 3. in this case,
Each device card 3 requires a special circuit corresponding to the reply management generation logic 10 such as the address buffer 7 and the reply / no reply signal generation circuit 30.
The configuration on the motherboard 1 side can be further simplified.

Example 5. The fifth embodiment of the present invention will be described below with reference to the drawings. 10 is a block diagram of an information processing apparatus showing Embodiment 1 of the invention, FIG. 14 is a time chart of each signal line of Embodiment 5, and FIG. 15 is this Embodiment 5.
3 is a circuit block diagram of a buffer for transmitting the state of the device card of FIG. In the above-described first to fourth embodiments, when a failure occurs in the device card, the dedicated information signal line 1 from the buffer 11 is sent to the CPU card.
The signal for interruption was input via 2. In the fifth and subsequent embodiments, the failure of the device card is stored as a status in a buffer or a memory, and the CPU polls the status. The other parts of this device have the same functions as those of the first embodiment, and are therefore given the same reference numerals as in FIG. In FIG. 14, 14 is an address line signal, 15 is a reply signal, and 18 is a reply management generation logic 10.
In the place corresponding to the reply management generation logic for managing and generating the reply signal for the device card 3, the device card 3 makes a determination at the time of no reply. Reference numeral 19 is a device card mounting status signal that conveys the mounting status of the device card on the device card mounting status signal line 9, and reference numeral 20 is a signal generated from the reply signal 17 and the no reply timer signal 18 (for example, "L" at the time of reply). , "H" at no reply.) A signal output to the system bus line 4 or the dedicated information signal line 12, 21 outputs a device card mounting status signal 19, a reply signal 17 or a no reply timer signal 18 as a trigger signal However, like the signal 20, it is a signal output to the system bus line 4 or the dedicated information signal line 12. Also,
In FIG. 15, 25 is a reply signal 17 to the buffer / memory device card 3 which is transmitted to the CPU card 2,
The no reply signal 18 and the device card mounting state signal 19 to the device card 3 are input, and the signal 20,
21 is an enable output signal for enabling the output signal of 21, and this signal is output from the bank memory 6. Then, the buffer memory 28 uses the device card mounting state signal 19 of the device card mounting state signal line 9, the output signal 17 of the reply signal management generation logic of the reply management generation logic 10 to the device card 3 and the no reply timer signal 18 from the device card CP state 3
It is a buffer / memory that transmits to the U card.

Next, the operation of the apparatus according to the fifth embodiment will be described. In FIG. 10, the CPU card 2 operates the bank memory 6 assigned to the input / output area by the bit operation of the data in the input / output address from the input / output area, and the bank memory 6 is the device card 3 to be controlled.
Select a group of mounting slots in which is mounted. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation,
Only in each of the selected mounting slots, the control signal of the address supply control line 8 becomes “permitted”, the address buffer 7 is opened, and the signal on the address line 5 is selected by the address buffer 7 as described above. It becomes possible to supply to the device card 3 attached to the mounting slot. Here, the CPU card 2 sends the address code to which the device card 3 to be controlled is assigned to the address line 5. This address code is supplied only to the group of device cards 3 through the address buffer 7 which is in an open state by the control signal from the bank memory 6, and only the device card 3 to which the address code is assigned is supplied. Can be controlled.

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIG. 14 and FIG. 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. For example, W
In the case of R (write operation), the device card mounting state signal 19 of “L” if the device card 3 is mounted and “H” if not mounted, conveys the mounting state of the device card 3 It is output via the status signal line 9. The reply management generation logic 10 that manages and generates the reply signal for the device card 3 outputs the reply signal to the output signal line 13 of the reply management generation logic that manages and generates the reply signal for the device card 3. That is, the reply signal 17 is used at the time of reply, and the reply management generation logic 10 that manages and generates the reply signal for the device card at the time of no reply.
The no-reply judgment timer detection signal 18 is used therein. As a result, the status of the device card is changed to the CPU card 2
Information is accessed through the buffer 11 (28) as a device card state detecting means which is transmitted to the CPU card 2 at the next timing at each device access to the buffer transmitted to the CPU card. Operate while checking whether it was abnormal or not. As a result, if no reply occurs and the device card is not mounted, the system bus signal of the reply-related information becomes "H" and the system bus signal of the device card mounting-related information becomes "H". And then
By confirming the signals 20 and 21 by the CPU card 2, it becomes possible to determine the normality / abnormality of the device card by the access next to the device card access. In this case, it is not necessary to modify the hardware of each device card 3, and the conventional device card 3 can be used as it is. As described above, in the fifth embodiment, the reply management generating means is provided in the mother board 1, the address buffer 7 is provided in the mother board 1, and the CPU card 2 polls the predetermined area 11a of the buffer 11. The device's device card failure status can be seen. Therefore, the information processing apparatus can be manufactured at low cost, and the cause when a trouble occurs can be determined. Further, since the buffer is provided as a transmission means to the CPU card 2, the information after the device card access can be held until the next device card access, and the trouble can be easily identified.

Example 6. The sixth embodiment of the present invention will be described below with reference to the drawings. FIG. 7 is a block diagram of a memory for transmitting the state of the device card of the information processing apparatus of the sixth embodiment to the CPU card. In FIG. 7, 24-1-2
4-n is the same number of memory selection signals as the type of address of each device card 3, 25-1 to 25-n are buffer / memory transmitted to the CPU card, the reply signal 17 of the device card 3, the device card 3 Is an enable output signal for inputting the no reply timer signal 18 and the device card mounting state signal 19 and enabling the signals 20 and 21. These enable output signals 25
-1 to 25-n are also memory selection signals 24-1 to 24-n
Similarly, two types of signals, that is, the same number of output signals as the device card address types and enable signals are output from the bank memory 6.

Next, the operation of the apparatus according to the sixth embodiment will be described. In FIG. 10, the CPU card 2 operates by bit manipulation of data in the input / output address from the input / output area.
The bank memory 6 assigned to the input / output area is operated, and the bank memory 6 selects a group of mounting slots in which the device card 3 to be controlled is mounted. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and the address buffer 7 is opened only in each of the selected mounting slots, and the signal on the address line 5 passes through the address buffer 7. , Can be supplied to the device card 3 attached to the selected mounting slot.
Here, the CPU card 2 sends the address code to which the device card 3 to be controlled is assigned to the address line 5. This address code is supplied only to the group of device cards 3 via the address buffer 7 which is in an open state by the control signal from the bank memory 6, and only the device card 3 to which the address code is assigned is supplied. Can be controlled.

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, referring to FIGS. 14 and 15, the address 14, data 15 and command 1 from the CPU card 2 are input.
6, the access to the device card is performed. For example, in the case of WR (write operation), “L” if the device card 3 is mounted, and “H” if the device card 3 is not mounted.
The device card mounting status signal 19 of (1) is output through the device card mounting status signal line 9 that conveys the mounting status of the device card. The reply management generation logic 10 that manages and generates the reply signal for the device card 3 outputs the reply signal to the output signal line 13 of the reply management generation logic that manages and generates the reply signal for the device card 3. That is, when replying, the reply signal 1
7 is used, and a no reply determination timer detection signal 18 is used in the reply management generation logic 10 that manages and generates a reply signal for the device card at the time of no reply. As a result, the information is transferred via the memory 11 (29) which transmits the state of the device card to the CPU card 2.
For example, the CPU card 2 accesses the memory transmitted to this CPU card at the next timing at every device access, or the transmission memory 11 (29) to this CPU card is regularly used as a CPU checking program. By performing the polling process, it is possible to operate while checking whether the device access is normal / abnormal. In this case, the transmission memory to the CPU is accessed by the same number of output signal enable signals 24 as the address types of the device card 3. As a result, if no reply and device card non-mounting occur, the system bus signal of reply-related information becomes "H", and the system bus signal of device card mounting-related information becomes "H". After this, the CPU card 2
By checking the signals 20 and 21, it is possible to determine whether the device card is normal or abnormal. In this case, it is not necessary to modify the hardware of each device card 3,
The conventional device card 3 can be used as it is. As described above, in the sixth embodiment, the reply generating means and the address buffer are provided in the motherboard 1, and the C
As a transmission means to the PU card 2, a memory is provided instead of the buffer, and the latest access state is stored in correspondence with the address of the device card 3. For this reason, information on all device cards can be checked when troubleshooting, which is a great advantage.

Example 7. The seventh embodiment of the present invention will be described below with reference to the drawings. 11 is a block diagram of an information processing apparatus showing a seventh embodiment of the present invention. Note that, in FIG. 11, the symbols of the respective parts are the same as those in the first embodiment, and therefore the description thereof will be omitted.

Next, the operation of the apparatus according to the seventh embodiment will be described. In FIG. 10, the CPU card 2 operates by bit manipulation of data in the input / output address from the input / output area.
The bank memory 6 assigned to the input / output area is operated, and the bank memory 6 selects a group of mounting slots in which the device card 3 to be controlled is mounted. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and is supplied to the device card only in each of the selected mounting slots, the address buffer 7 in the device card is opened, and the address line 5 The above signal can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2 sends the address code assigned to the device card 3 to be controlled to the address line 5
Send to. This address code is supplied to the address buffer 7 in the open device card 3 by the control signal from the bank memory 6, and only the device card 3 to which the relevant address code is assigned can be controlled. .

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIGS. 14 and 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. For example, WR
In the case of (write operation), the device card mounting state signal line "L" when the device card 3 is mounted and "H" when the device card 3 is not mounted conveys the mounting state of the device card. It is output through 9.
The reply management generation logic 10 that manages and generates the reply signal for the device card 3 outputs the reply signal to the output signal line 13 of the reply management and generation logic that manages and generates the reply signal for the device card. That is, the reply signal 17 is used at the time of reply, and the no reply determination timer detection signal 18 is used in the reply management generation logic 10 that manages and generates the reply signal for the device card at the time of no reply. As a result, the information is accessed through the buffer 11 (28) for transmitting the state of the device card 3 to the CPU card 2 at the next timing every time the device is accessed through the buffer transmitted by the CPU card 2 to the CPU card 2. It Then, the device is operated while checking whether the device access is normal or abnormal. By this,
If no reply and device card non-mounting occur, the system bus signal of reply related information becomes "H", and the system bus signal of device card mounting related information becomes "H". After that, by checking the signals 20 and 21 by the CPU card 2, the normality / abnormality of the device card can be determined by the access next to the device card access. In this case, each device card 3
Requires a special circuit such as the address buffer 7.
As described above, in the seventh embodiment, the reply management generation means is provided in the mother board 1, the address buffer is provided in the device card, and the buffer is used as the transmission means to the CPU card 2. Therefore, the address matching confirmation can be performed on the device card that is the access target, the failure can be surely checked, and the performance of the failure resolution can be improved.

Example 8. Embodiment 8 of the present invention will be described below with reference to the drawings. In the information processing apparatus of the eighth embodiment, the reply management generating means is provided in the mother board 1, the address buffer 7 is provided in the device card 3, and the memory shown in FIG. 16 is used as a transmitting means (storage means) to the CPU card 2. To use.

Next, the operation of the apparatus of the eighth embodiment will be described. In FIG. 10, the CPU card 2 operates the bank memory 6 allocated to the input / output area by bit operation of the data in the input / output address from the input / output area.
The bank memory 6 selects a group of mounting slots to which the device card 3 to be controlled is mounted. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and is supplied to the device card only in each of the selected mounting slots, the address buffer 7 in the device card is opened, and the address line 5 The above signal can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Where C
The PU card 2 sends the address code, to which the device card 3 to be controlled is assigned, to the address line 5. This address code is supplied to the address buffer 7 in the open device card 3 by the control signal from the bank memory 6, and only the device card 3 to which the relevant address code is assigned can be controlled. .

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIGS. 14 and 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. For example, WR
In the case of (write operation), the device card mounting state signal line "L" when the device card 3 is mounted and "H" when the device card 3 is not mounted conveys the mounting state of the device card. It is output through 9.
Further, the reply management generation logic 10 that manages and generates the reply signal for each device card 3 outputs the reply signal to the output signal line 13 of the reply management generation logic that manages and generates the reply signal for the device card. That is, the reply detection signal 18 is used in the reply management generation logic 10 that manages and generates the reply signal 17 at the time of reply and the reply signal for the device card at the time of no reply. As a result, the information is accessed through the memory 11 (28) that transmits the state of the device card 3 to the CPU card 2, and the information transmitted by the CPU card 2 to this CPU card is accessed at the next timing every device access. . Alternatively, by periodically polling the transmission memory 11 (29) to the CPU card 2 as a checking program of the CPU card 2, it is possible to operate while checking whether the device access is normal / abnormal. . In this case, the same number of output signal enable signals 24 as the number of address types of the device card 3 causes the corresponding CP
Access the transmission memory to the U card. This allows
In the unlikely event that no reply occurs and the device card is not mounted, the system bus signal of reply-related information becomes "H", and the system bus signal of device card mounting-related information becomes "H". After that, the CPU card 2 checks the signals 20 and 21 to determine whether the device card 3 is normal or abnormal. In this case, each device card 3 requires a special circuit such as the address buffer 7. As described above, the eighth embodiment has the same advantages as the fifth and sixth embodiments.

Example 9. The ninth embodiment of the present invention will be described below with reference to the drawings. 12 is a block diagram of an information processing apparatus showing a ninth embodiment of the present invention. Note that, in FIG. 12, the symbols of the respective parts are the same as those in the first embodiment, and therefore the description thereof will be omitted. In FIG. 11, reference numeral 30 denotes a reply / no reply signal generation circuit as reply management generation means having the same function as the reply management generation logic 10.
Reference numeral 6 is a reply / no reply signal output line from each device card. In the information processing apparatus of the ninth embodiment, the reply management generation means is provided in the device card 3, the address buffer 7 is provided in the mother board 1, and the buffer is used as a transmission means (storage means) to the CPU card 2.

Next, the operation of the apparatus according to the ninth embodiment will be described. In FIG. 14, the CPU card 2 uses the bit operation of the data in the input / output address from the input / output area to
The bank memory 6 assigned to the input / output area is operated, and the bank memory 6 selects a group of mounting slots in which the device card 3 to be controlled is mounted. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and the address buffer 7 is opened only in each of the selected mounting slots, and the signal on the address line 5 passes through the address buffer 7. , Can be supplied to the device card 3 attached to the selected mounting slot.
Here, the CPU card 2 sends the address code to which the device card 3 to be controlled is assigned to the address line 5. This address code is supplied only to the group of device cards 3 via the address buffer 7 which is in an open state by the control signal from the bank memory 6, and only the device card 3 to which the address code is assigned is supplied. It becomes controllable.

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIGS. 14 and 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. For example, WR
In the case of (write operation), the device card mounting status signal 19 of “L” if the device card 3 is mounted and “H” if not mounted is the device card mounting status signal that conveys the mounting status of the device card. It is output via line 9. A reply / no reply signal to the device card 3 is directly supplied from the reply / no reply signal output line 26 from the device card 3. That is, the reply signal 17 is used at the time of reply, and the no reply determination timer detection signal 18 within the reply management generation logic for managing and generating the reply signal supported in the device card is used at the time of no reply. As a result, the information is transferred to the CPU 11 via the buffer 11 (28) which transmits the state of the device card 3 to the CPU card 2.
The buffer transmitted by the card 2 to the CPU card is accessed at the following timing every device access.
At this time, the device card 3 is operated while checking whether the access to the device card 3 is normal or abnormal. As a result, in the unlikely event that no reply or device card is not mounted, the system bus signal of reply-related information
For example, "H", the system bus signal of the device card mounting-related information becomes "H", and by checking the signals 20 and 21 by the CPU card thereafter, the normality / abnormality of the device card 3 is checked next to the device card access. It can be judged by access. In this case, each device card 3 requires a special circuit such as a reply / no reply signal generation circuit. As described above, in the ninth embodiment,
Since the reply management generating means is housed in the device card 3, the failure of the device card can be confirmed on the device card, the failure can be surely checked, and the performance of identifying the failure is improved.

Example 10. Hereinafter, Example 10 of the present invention
Will be described with reference to the drawings. In the information processing apparatus of the tenth embodiment, the reply management generation means is provided in the device card, the address buffer is provided in the mother board, and the failure transmission means to the CPU card is the memory (storage means).

Next, the operation of the apparatus according to the tenth embodiment will be described. In FIG. 11, the CPU card 2 operates the bank memory 6 assigned to the input / output area by bit manipulation of the data in the input / output address from the input / output area, and the bank memory 6 is the device card 3 to be controlled.
Select a group of mounting slots in which is mounted. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation,
Only in each of the selected mounting slots, the control signal of the address supply control line 8 becomes “permitted”, the address buffer 7 is opened, and the signal on the address line 5 is selected via the address buffer 7. It becomes possible to supply to the device card 3 attached to the mounting slot. Here, the CPU card 2 sends the address code to which the device card 3 to be controlled is assigned to the address line 5. This address code is supplied only to the group of device cards 3 via the address buffer 7 which is in an open state by the control signal from the bank memory 6, and only the device card 3 to which the address code is assigned is supplied. Can be controlled.

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIGS. 14 and 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. 14 and 1
5, for example, in the case of WR (write operation), the device card mounting state signal 19 of “L” if the device card 3 is mounted and “H” if not mounted, conveys the mounting state of the device card. It is output through the device card mounting state signal line 9. The reply / no reply signal to the device card is directly supplied via the reply / no reply signal output line 26 from each device card. That is, the reply signal 17 at the time of reply and the no reply determination timer detection signal 1 within the reply management generation logic for managing and generating the reply signal supported in the device card at the time of no reply
8 is used. As a result, the state of the device card 3 is changed to C
The information is accessed via the memory 11 (29) transmitted to the PU card 2 at the following timing at every device access to the memory transmitted by the CPU card 2 to this CPU card. Alternatively, as a check program for the CPU card 2, the transmission memory 11 to the CPU card 2
By periodically polling (29), it is operated while checking whether the device access is normal / abnormal. In this case, the transmission memory for the corresponding CPU card is accessed by the same number of output signal enable signals 24 as the address types of the device card 3. As a result, if no reply occurs and the device card is not mounted, the system bus signal of the reply related information becomes "H" and the system bus signal of the device card mounting related information becomes "H". After that, CPU card 2
Thus, by confirming the signals 20 and 21, it is possible to determine the normality / abnormality of the device card at the next access after the device card access. In this case, each device card 3 requires a special circuit such as a reply / no reply signal generation circuit. As described above, the tenth embodiment has the same merits as the above-described sixth and ninth embodiments.

Example 11. Hereinafter, Example 11 of the present invention
Will be described with reference to the drawings. FIG. 13 is a first embodiment of the present invention.
It is a block diagram which shows the information processing apparatus of 1. In the eleventh embodiment, the reply management generating means and the address buffer are housed in the device card, and the buffer shown in FIG. 15 is used as means for transmitting the failure signal to the CPU.

Next, the operation of the apparatus of the eleventh embodiment will be described. In FIG. 12, the CPU card 2 operates the bank memory 6 assigned to the input / output area by bit operation of the data in the input / output address from the input / output area, and the bank memory 6 is attached with the device card 3 to be controlled. Select a group of mounting slots. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and is supplied to the device card only in each of the selected mounting slots, the address buffer 7 in the device card is opened, and the address line 5 The above signal can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2 sends the address code assigned to the device card 3 to be controlled to the address line 5
Send to. This address code is supplied to the address buffer 7 in the open device card 3 by the control signal from the bank memory 6, and only the device card 3 to which the relevant address code is assigned can be controlled. .

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIGS. 14 and 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. 14 and 1
5, for example, in the case of WR (write operation), the device card mounting state signal 19 of “L” if the device card 3 is mounted and “H” if not mounted, conveys the mounting state of the device card. It is output via the device card mounting state signal line 9. The reply / no reply signal to the device card is directly supplied via the reply / no reply signal output line 26 from each device card. That is, the reply signal 17 at the time of reply and the no reply determination timer detection signal 1 within the reply management generation logic for managing and generating the reply signal supported in the device card at the time of no reply
8 is used. As a result, the state of the device card 3
The information is accessed via the buffer 11 (28) which is transmitted to the CPU card 2 at the following timing at every device access to the buffer which the CPU card transmits to this CPU card. Then, the operation is performed while checking whether the device access is normal or abnormal. As a result, if no reply occurs and the device card is not mounted, the system bus signal of the reply-related information becomes "H" and the system bus signal of the device card mounting-related information becomes "H". After that, by checking the signals 20 and 21 by the CPU card 2, the normality / abnormality of the device card can be determined by the access next to the device card access. In this case, each device card 3 requires special circuits such as an address buffer and a reply / no reply signal generation circuit. As described above, in the eleventh embodiment, since the reply management generation means and the address buffer are provided in the device card,
Failure information can be reliably confirmed, and the reliability and performance of failure confirmation of this device are improved.

Example 12. Hereinafter, Example 12 of the present invention
Will be described with reference to FIG. In the information processing apparatus according to the twelfth embodiment, the reply management generating means and the address buffer are housed in the device card, and the CPU
The memory of FIG. 16 was used as a means for transmitting a failure signal to the memory.

Next, the operation of the apparatus of the twelfth embodiment will be described. In FIG. 12, the CPU card 2 operates the bank memory 6 assigned to the input / output area by bit operation of the data in the input / output address from the input / output area, and the bank memory 6 is attached with the device card 3 to be controlled. Select a group of mounting slots. Then, the bank memory 6 generates a control signal for controlling permission / prohibition of the address code supply and sends it to the address supply control line 8. By this operation, the control signal of the address supply control line 8 becomes “permitted” and is supplied to the device card only in each of the selected mounting slots, the address buffer 7 in the device card is opened, and the address line 5 The above signal can be supplied to the device card 3 attached to the selected mounting slot via the address buffer 7. Here, the CPU card 2 sends the address code assigned to the device card 3 to be controlled to the address line 5
Send to. This address code is supplied to the address buffer 7 in the open device card 3 by the control signal from the bank memory 6, and only the device card 3 to which the relevant address code is assigned can be controlled. .

Therefore, in addition to the group of device cards 3,
Even if there is a device card 3 to which the same address code is assigned, the device card 3 for which the control signal from the address supply control line 8 is "prohibited" will not be controllable. It is possible to allocate a plurality of device cards 3 to the same address code. Next, in FIGS. 14 and 15, the device card is accessed by the address line signal 14, the data line signal 15 and the command line signal 16 from the CPU card 2. 14 and 1
5, in the case of WR (write operation), a device card mounting state signal 19 of “L” if the device card is mounted and “H” if not mounted, conveys the mounting state of the device card. It is output via the card mounting state signal line 9. The reply / no reply signal to the device card is directly supplied through the reply / no reply signal output line 26 from each device card. That is, a reply signal 17 at the time of reply and a no reply determination timer detection signal 18 within the reply management generation logic for managing and generating the reply signal supported in the device card at the time of no reply.
Is used. As a result, the state of the device card 3 is changed to C
The information is accessed through the memory 11 (29) transmitted to the PU card 2 at the following timing at every device access to the memory transmitted to the CPU card by the CPU card. Alternatively, by periodically polling the transmission memory 11 (29) to the CPU card as a CPU checking program, it is possible to operate while checking whether the device access is normal / abnormal. In this case, the transmission memory to the corresponding CPU is accessed by the same number of output signal enable signals 24 as the device card address type. As a result, if no reply occurs and the device card is not mounted, the system bus signal of the reply-related information becomes "H" and the system bus signal of the device card mounting-related information becomes "H". After that, by checking the signals 20 and 21 with the CPU card 2, the device card 3
The normality / abnormality of can be determined by the access next to the device card access. In this case, each device card 3
Requires special circuits such as an address buffer and a reply / no reply signal generation circuit.

[0049]

According to the first aspect of the present invention, the various devices described above are received by the reply signal from the reply management generating means for managing and generating the reply signal for the various device cards and the presence / absence detection signal of the various device cards. Since a means for detecting the status of the card and transmitting information about the status of this device card to the central processing unit card as an interrupt signal is provided, the information is normally input by the hardware when various device cards are not mounted and by the hardware. Even when multiple abnormalities overlap, like when it is not possible to output,
This has the effect of facilitating the investigation of the original abnormal location and preventing a significant decrease in the operating rate. According to the second invention, since the address buffer for setting whether or not to send the address code to the device card is housed in each of the device cards, in addition to the effect of the first invention, the configuration of the motherboard is provided. There is an effect that can be simplified. This third
According to the invention, the reply management generating means for managing and generating reply signals for the various device cards is housed in each of the device cards. Therefore, in addition to the effect of the first invention, the configuration of the motherboard can be simplified. effective. According to the fourth invention, an address buffer for setting whether or not to send an address code to the device card, and a reply management generating means for managing and generating reply signals for the various device cards are provided in each of the device cards. Since it is housed inside, in addition to the effect of the first invention, there is an effect that the configuration of the motherboard can be further simplified.

According to the fifth aspect of the invention, the reply management generating means for managing and generating the reply signal for the various device cards, and the reply signal and the presence / absence detection signal of the various device cards are used to perform the various operations. Since the device card state detecting means for detecting the state of the device card, and the storage means for storing the detection result from the device card state detecting means in a predetermined area polled by the central processing unit card, This has the effect of reducing the cost of manufacturing this device. Further, there is an effect that the information on the failure can be surely determined. According to the sixth aspect of the invention, the reply management generating means and the address buffer are housed in the mother board, so that there is an effect of reducing the manufacturing cost of this device. Further, there is an effect that the information on the failure can be surely determined. According to the seventh invention, the reply management generating means is housed in the mother board and the address buffer is housed in the device card. Therefore, in addition to the effect of the fifth invention, There is an effect that the failure can be surely confirmed on the device card to be accessed.
According to the eighth invention, the reply management generating means is housed in the device card and the address buffer is housed in the mother board. Therefore, in addition to the effect of the fifth invention, The presence of the reply signal can be confirmed on the device card to be accessed. According to the ninth aspect of the invention, the reply management generating means and the address buffer are housed in the device card. Therefore, in addition to the effect of the fifth aspect of the invention, the reply signal is transmitted on the device card. There is an effect that it is possible to confirm the presence or absence of a fault and the failure surely.

[Brief description of drawings]

FIG. 1 is a block diagram showing an information processing device according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a specific example of a motherboard according to the first embodiment of the present invention.

FIG. 3 is a circuit block diagram showing a connection part of the motherboard of FIG. 2 with a device card.

FIG. 4 is a block diagram showing an information processing device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an information processing device according to a third embodiment of the present invention.

6 is a circuit block diagram showing a function for generating a reply / no reply signal from the device card of FIG.

FIG. 7 is a block diagram showing an information processing device according to a fourth embodiment of the present invention.

FIG. 8 is a time chart of each signal line according to the embodiment of the present invention.

FIG. 9 is a block diagram of a buffer for transmitting the status of the device card to the CPU card according to the embodiment of the present invention.

FIG. 10 is a block diagram showing an information processing apparatus according to embodiments 5 and 6 of the present invention.

FIG. 11 is a block diagram showing an information processing apparatus according to embodiments 7 and 8 of the present invention.

FIG. 12 is a block diagram showing an information processing apparatus according to embodiments 9 and 10 of the present invention.

FIG. 13 is a block diagram showing an information processing apparatus according to embodiments 11 and 12 of the present invention.

FIG. 14 is a time chart of each signal line according to the embodiment of the present invention.

FIG. 15 is a block diagram of a buffer for transmitting the status of the device card to the CPU card according to the embodiment of the present invention.

FIG. 16 is a block diagram of a memory for transmitting the status of the device card to the CPU card according to the embodiment of the present invention.

FIG. 17 is a block diagram showing a conventional information processing apparatus.

[Explanation of symbols]

 1 Motherboard 2 CPU Card 3 Device Card 4 System Bus 5 Address Line 6 Bank Memory 7 Address Buffer 8 Address Supply Control Line 9 Device Card Mounting Status Signal Line 10 Reply Management Generation Logic 11 Buffer 12 Output Signal Line 14 Address Line Signal 15 Data Line signal 16 Command (control command) line signal 17 Reply signal 18 Device card mounting status signal 22, 23 Interrupt signal 24 Memory selection signal 25 Output signal enable signal 26 Reply / No reply signal output line 28 Buffer memory 30 Reply / No reply signal generation circuit

Claims (9)

[Claims] 1. A central processing unit card mounted in a plurality of mounting slots and various device cards are connected by a system bus, and an address code transmitted by the central processing unit card is opened from an address line of the system bus. In the information processing device having a motherboard that supplies the data to a predetermined device card via the address buffer of the status and controls the device card to which the address code is assigned, manages and generates reply signals for the various device cards. Reply management generation means for detecting the status of the various device cards by the reply signal and the presence / absence detection signal of the various device cards, and interrupts the information about the status of the device card to the central processing unit card. And a means for transmitting as a signal. An information processing device characterized by: 2. The information processing apparatus according to claim 1, wherein the address buffer for setting whether or not to send the address code to the device card is housed in each of the device cards. 3. The information processing apparatus according to claim 1, wherein reply management generating means for managing and generating reply signals for the various device cards is housed in each of the device cards. 4. An address buffer for setting whether or not to send an address code to a device card, and reply management generation means for managing and generating reply signals for the various device cards are housed in each of the device cards. The information processing apparatus according to claim 1, wherein the information processing apparatus comprises: 5. A central processing unit card mounted in a plurality of mounting slots and various device cards are connected by a system bus, and an address code transmitted by the central processing unit card is opened from an address line of the system bus. In the information processing device having a motherboard that supplies the data to a predetermined device card via the address buffer of the status and controls the device card to which the address code is assigned, manages and generates reply signals for the various device cards. Reply management generating means, a device card status detecting means for detecting the status of the various device cards by the reply signal and the presence / absence detection signal of the various device cards, and detection from the device card status detecting means The result shows that the central processing unit card An information processing apparatus, comprising: a storage unit that stores a predetermined area for polling. 6. The information processing apparatus according to claim 5, wherein the reply management generation means and the address buffer are housed in the motherboard. 7. The information processing apparatus according to claim 5, wherein the reply management generating means is housed in the mother board, and the address buffer is housed in the device card. 8. The information processing apparatus according to claim 5, wherein the reply management generation means is housed in the device card and the address buffer is housed in the motherboard. 9. The information processing apparatus according to claim 5, wherein the reply management generation means and the address buffer are housed in the device card.