JPH0628187A - Data loading method and arithmetic processor using the same - Google Patents

Abstract

PURPOSE:To execute parts of a process, which can be made to overlap, in parallel and to obtain a higher throughput by providing a mechanism which restarts instruction execution when return tokens from a necessary number of memories arrive after the execution of respective load instructions generating readout request tokens on condition that there is an instruction to be executed in synchronism with the end of the loading of plural data from the memories. CONSTITUTION:An arithmetic processing part 10 which performs arithmetic processing while referring to and updating a register group 11 under the control of an instruction sequence control part 14. When data are loaded in a register from an external memory, a token is generated and sent to a memory access controller. The execution of the instruction sequence is interrupted according to a sequence end flag in each instruction. A load control part 21 decides on the tokens returned from the outside whether or not a necessary number of tokens required for target load instruction execution are ready and when so, they are put in the arithmetic processing part 10 through a token memory 13 in turn, so that the previous instruction execution is carried on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data loading method in an arithmetic processor which processes a plurality of instruction sequences in parallel and executes the instructions in the execution instruction sequence, and an arithmetic processor using the same.

[0002]

2. Description of the Related Art In a conventional arithmetic processor operating by the Huon-Neumann method, when an instruction to access a memory is issued while executing a sequence of instructions, the instruction is executed and the memory access is executed. Until the processing ends, the processing operation of the arithmetic unit does not proceed to the processing of the next instruction, but waits there. In particular, when the access is a memory read (load) operation, the read value is used in subsequent instructions, and thus such a waiting operation is essential.

With such a control method, if the time taken from the activation of the memory access to its termination is longer than the time required to execute one instruction of the arithmetic processor, the arithmetic processor executes the arithmetic operation. This results in a wasteful cycle without executing the process, which causes a decrease in the processing performance.

In order to solve this, in the invention described in Japanese Patent Application No. 04-108071 filed by the present applicant, the execution instruction sequence is switched at the time of executing a load instruction for accessing the memory, and the memory access and the execution of another instruction sequence are performed in parallel. By doing so, it is possible to maintain high processing performance.

[0005]

In the above-described method, it is possible to maintain high processing performance by switching execution instruction sequences when executing a load instruction for accessing a memory and performing memory access and execution of another instruction sequence in parallel. However, when the instruction cache is used for speeding up, the probability of instruction cache miss increases due to the switching of the instruction sequence, and the execution instruction fetch speed decreases.

Further, particularly when the number of instruction sequences that can be executed in parallel is small, even if the above-mentioned Japanese Patent Application No. 04-10807 is used.
Even if the invention described in 1 is used, if the portion that is continuously executed is short, the number of cycles in which the arithmetic processing unit is idle increases when the token memory is empty.

For example, address calculation for loading data A into a register Loading data A (“load” refers to the operation of fetching data from a local or remote memory and moving it to a specified register of the arithmetic processor) Data Address calculation for loading B into register Load data B Assume that there is a processing flow called an operation using data A and B.

Even if the token memory is empty even with the method proposed above, the time lapse of processing relating to this instruction sequence is shown in FIG.
It can be illustrated as (A) (in the figure, the "load of A" portion includes the time from returning from the memory to arranging in the token memory and exiting from it to enter the arithmetic processing unit).

At this time, the "data A loading operation" and the "address calculation for loading the data B into the register" can be originally executed in parallel, but they are processed in series because of control. , It takes a long time from the beginning to the end of the whole processing of this instruction sequence, especially when there is not enough other instruction sequence that can be executed in parallel.
During the “load of A”, there is a problem that the operation rate of the arithmetic unit may decrease because there is no other process to proceed.

Therefore, the execution of one instruction sequence is continued by increasing the sequence length, which is a portion (partial instruction sequence) that is continuously executed in one instruction sequence without causing an interruption operation. Continuing is preferable for speeding up the processing. In other words, it is more desirable to continue the execution of the same instruction sequence to the point where it can be reached without interrupting the portion of the instruction sequence that does not need to be interrupted, and then perform the interrupting operation where it is absolutely necessary to interrupt. Become.

That is, if the "load of A" and the "address calculation of B" can be executed in parallel as shown in FIG. 6B, this problem can be alleviated. The above problem remains because the "load of A" and the "load of B" cannot be overlapped. That is, it is desirable that the processing as shown in FIG.

An object of the present invention is to solve the above problems and to provide an instruction sequence switching method for realizing higher processing performance and an arithmetic processor using the same.

[0013]

According to the data loading method of the first invention, a plurality of instruction sequences that can be executed in parallel are prepared in advance, and one of them is selected as an execution instruction sequence while switching them. A first instruction sequence including a target instruction to be executed using the two data after the load operation of the first and second two data is completed in an arithmetic processor that sequentially executes the instructions in the execution instruction sequence A data loading method for loading the two pieces of data from a memory into the arithmetic processor during execution of the first data, the first data is used when a first load instruction for loading the first data from the memory is executed. Issuing a first token including the address of the target instruction to the outside to activate a memory access operation and continue execution of the first instruction sequence; At the time of executing a second load instruction that loads the second data from the memory, a second token including the address of the target instruction that uses the second data is externally issued to activate the memory access operation. Together with the execution of the first instruction sequence, after that, immediately before the target instruction, execution of the first instruction sequence is interrupted and execution of another instruction sequence is performed, and the memory access operation is terminated and the The number of input tokens input to the arithmetic processor having the data necessary for the target instruction is counted, and when the result of the counting is 2, the first
The execution of the instruction sequence is restarted from the target instruction according to the address of the target instruction included in the input token.

In the arithmetic processor of the second invention, a plurality of instruction sequences that can be executed in parallel are prepared in advance, one of them is selected as an execution instruction sequence while switching them, and the instructions in the execution instruction sequence are selected. In an arithmetic processor that executes sequentially, an arithmetic processing unit that sequentially executes instructions in one instruction sequence, a token memory that holds a token input from the outside and supplies the token to the arithmetic processing unit, and an arithmetic processing unit that is accessed from the arithmetic processing unit. I / O information of the token including a register group for holding data, a description of an operation performed externally, and a restart instruction address to be resumed after interrupting the instruction sequence execution described in the instruction code being executed at that time. Before managing and counting the number of inputs and holding the token returned from the outside to the arithmetic processor in the token memory A load control unit that writes the memory read data in the token to register in the register group,
Each load instruction has the restart instruction address and the required number of firings, which is the number of arrival tokens required for restart, and for each instruction, an instruction group having a flag indicating whether or not the instruction immediately after the instruction is executed is continued. And a command sequence control unit for controlling the operation of each unit while storing a program including the program and supplying a command sequence to the arithmetic processing unit.

The method of the third invention is, in addition to the method of the first invention, a target instruction to be executed by using the n data after completion of a load operation of n data in the first instruction sequence. When the load instruction for loading each of the n pieces of data is executed, a token including the address of the target instruction is issued to the outside to activate the memory access operation, and Execution is continued, and then, immediately before the target instruction, the execution of the first instruction sequence is interrupted to move to another instruction sequence execution, the memory access operation is terminated, and the target instruction has data. The number of input tokens is counted, and when the result of the counting is n, the execution of the first instruction sequence is executed according to the address of the target instruction included in the input token. It is characterized by resuming from the target instruction.

In addition to the third aspect of the invention, the method of the fourth aspect of the present invention, when executing a load instruction, replaces the target instruction with any one of the instructions between the load instruction and the target instruction (this is called a restart instruction). The token including the address is issued to the outside to activate the memory access operation, and then the execution of the instruction sequence is interrupted immediately before the restart instruction, and the token having the address of the restart instruction is input a predetermined number of times. It is characterized in that it is possible to restart from the restart instruction by an address contained in the token.

According to the method of the fifth invention, in addition to the fourth invention, a plurality of load instructions and respective target instructions are included in an instruction sequence for an instruction that requires two data for instruction execution. If present, for all load instructions,
During execution of the first load instruction, the first load instruction resumes the first target instruction when there is no other load instruction between the first load instruction and the target first target instruction. When the other load instruction exists and the load instruction closest to the first load instruction is a second load instruction having another second target instruction, the first load instruction is the second load instruction. Load instruction is a restart instruction, and when there is another load instruction and the load instruction closest to the first load instruction is the third load instruction having the same first target instruction, the first load instruction For the instruction, the same instruction as the restart instruction of the third load instruction is used as the restart instruction, and when all the instructions are the restart instructions of any load instruction, Immediately before that, execution of the instruction sequence to which the certain instruction belongs is interrupted, and when there are two load instructions that use the certain instruction as the restart instruction, when two tokens having the restart instruction arrive, The feature is that the instruction sequence to which it belongs can be restarted.

[0018]

In the first and second inventions, the address of the target instruction corresponding to the load instruction is checked in advance, and after issuing two tokens having the address of the target instruction, the execution of the instruction sequence is suspended immediately before the target instruction. ,
The instruction sequence execution is restarted by discovering that two tokens have been input.

According to the third aspect of the invention, even when the data required for executing the target instruction is more than two, the same operation is performed by counting the necessary number at the time of restart.

In the fourth invention, even if there is an instruction which is an obstacle in implementing the method of the third invention between the load instruction and the target instruction, this is statically detected at compile time, and the instruction is detected. The same operation is performed by setting the address of 1 as the restart address.

According to the fifth aspect of the invention, even if a set of two or more load instructions and a target instruction interfere with each other, the restart address after interruption is set so as to resolve the interference, and the same operation is performed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the apparatus of the second invention using the method of the first invention will be described with reference to the drawings.

FIG. 1 is a basic configuration diagram of an embodiment of an arithmetic processor of the second invention, FIG. 2 is a format diagram showing a format of a token used in this arithmetic processor, and FIG. 3 is used in this arithmetic processor. It is a format diagram which shows the format of an instruction.

The arithmetic processor 1 of FIG. 1 performs arithmetic processing in accordance with an instruction in the instruction sequence referred to by incrementing the value of the internal program counter by one when the instruction sequence is given. Unit 10 and arithmetic processing unit 1
A token is generated from a register group 11 which is a set of a plurality of registers referenced and updated from 0, an instruction in the arithmetic processing unit 10 and a value of a program counter, and is issued to a memory access controller (not shown). And the token input from the memory access controller via the load control unit 21 to the FIFO.
An instruction sequence control that controls the operations of the token memory 13 that sequentially holds the O, the load control unit 21, the token memory 13, the arithmetic processing unit 10, and the token generation unit 12 and that has a program memory that internally holds a program And part 14. The register group 11 is divided into a global register frame and R local register frames. R is an integer of 2 or more, for example, 16.

FIG. 4 shows the configuration of the load control unit 21 including the input token table 20 and the input management unit 25. The input token table 20 consists of R rows, and each row has a field of the required number of firing 22 and the number of already arrived 23. Number of arrivals 2
3 is initialized to "0".

When performing arithmetic processing using such arithmetic processor 1, the procedure is as follows.

First, from the outside, a program describing the entire operation is given to the instruction sequence control unit 14 via the signal line 90, and then some tokens each having an execution start address are given.

The upper limit of the number of tokens which are given at the same time and can exist inside and outside the arithmetic processor 1 is the number R of local register frames in the register group 11. At the time of initial startup, the number of tokens is adjusted by the compiler when creating the program code so that it does not exceed this number. As a result, the number of executable instruction sequences existing in the system at the same time becomes R or less. When R or less tokens are given from the outside when the program is started, the instruction sequence control unit 14 gives different frame identifiers to the respective tokens. The frame identifier identifies which of the R local register frames the instruction string represented by the token exclusively uses.

The program in the instruction sequence controller 14 is a series of a series of instructions, and the execution start address is one of them. Hereinafter, a subsequence from the execution start address to a certain end point in the program is called an instruction sequence.

All tokens are stored in the token memory 13. The token in token memory 13 is shown in format 50 of FIG. 2 and has a field 51 of execution start addresses. At this time, the field 60 is not used, and the value of the flag 52 is "0". The aforementioned frame identifier is written in the field 63. Further, the number of tokens given from the outside to the token memory 13 is set in the token number counter in the instruction sequence control unit 14.

When a processing start signal is given to the instruction sequence control unit 14 from the outside, the first token in the token memory 13 is sent to the arithmetic processing unit 10, and the value of the flag 52 of the token is "0". Therefore, in the arithmetic processing unit 10, the value of the execution start address 51 in the token is set in the program counter. At the same time, the frame identifier 6
The value of 3 is set in the frame register in the arithmetic processing unit 10. This is hereinafter referred to as an instruction string fetch operation. Then, the execution of the instruction sequence is started.

In the arithmetic processing of the arithmetic processing unit 10, first, the value of the program counter is sent to the instruction sequence control unit 14, and the instruction in the program memory in the instruction sequence control unit 14 indicated by it is used as an address. To be fucked. This is called an instruction fetch operation.

Next, in the arithmetic processing unit 10, after executing the instruction described in the fetched instruction, if the sequence end flag of the instruction (reference numeral 65 of the instruction format in FIG. 3 described later) is "0". If the value of the program counter is 1
Increments by one and proceeds to execution of the next instruction. If the sequence end flag of the instruction is "1", the execution of the instruction sequence is terminated and another instruction sequence fetch operation is performed, as in the case where the instruction sequence end instruction described later is executed. The above is the basic operation of instruction execution.

As the types of instructions obtained by the instruction fetch, an ALU operation instruction for writing an operation result such as addition, subtraction, multiplication, division, etc. to a designated register by referring to a maximum of two register values in the register group 11 and an external memory A load instruction that reads the above data by specifying its address and loads it into a register, a store instruction that writes the data in the register to a specified location in external memory, and changes the value of the program counter by the value specified by the instruction There are a jump instruction and a branch instruction to be performed, and an instruction sequence end instruction to terminate the instruction sequence execution at the end of the instruction sequence.

When executing ALU operation instructions, load instructions, and store instructions, the instructions use the format of reference numerals 80, 70 and 75 in FIG. 3, but the register identifiers therein directly identify the registers. Instead, it is used for identification within the frame assigned to the instruction sequence. The register identifier first indicates whether it points to a global frame register or a local frame register, and if the former, the rest address one of them. In the latter case, one frame is determined by the frame identifier held in the frame register in the arithmetic processing unit 10, and one register is addressed by the register identifier in the instruction.

When the instruction obtained by the instruction fetch is an ALU operation instruction, the above basic operation is performed. The format of the ALU operation instruction is shown by reference numeral 80 in FIG. The register containing the data used by the read register identifier A83 and the read register identifier B84 for the calculation is designated as the write register identifier 82.
Indicates the register in which the result should be stored.

When the instruction obtained by the instruction fetch is a load instruction, the instruction sequence control unit 14 to the token generation unit 12
2 is generated, the token generation unit 12 generates the read request token shown in the format 55 of FIG.

The format of the load instruction is shown at reference numeral 70 in FIG. The format 70 of the load instruction is an instruction code 71 indicating the load instruction, a read address 73 for reading the memory, an identifier 72 of a register for writing the read data, and an instruction for restarting after interrupting the instruction sequence execution by executing the load instruction. It has an address 66 in the program memory of a certain target instruction and a required firing number 67 for holding the number of input tokens required to restart the instruction sequence execution from the target instruction address. This required firing number 67
In the arithmetic processor for realizing the method of the first invention, "1" or "2" is inserted, and in the arithmetic processor for realizing the method of the third invention or later, the number n determined by the program is entered.

In the read request token format 55, the value of the target instruction address 66 in the load instruction 70 at that time is used as the execution start address 58, and the read address 73 of the external memory in the load instruction 70 to be accessed is used as the access address 57. The register identifier 72 in the load instruction 70 is used as the register identifier 61, and the operation code 56 has a code for instructing memory read as an operation performed by the memory access controller. Further, the frame identifier held in the arithmetic processing unit 10 is written in the field 64. At this time, the field 59 is not used.

When the load instruction is executed, this read request token is sent to the memory access controller via the signal line 91 after generation. At the same time, the command controller 14 sends the signal line 9
The operation processing unit 1 of the input token table 20 (see FIG. 4) in the load control unit 21 at that time via 3, 94.
The load instruction 70 (see FIG. 3) is loaded into the field 22 of the required number of firing of the row addressed by the frame identifier held in 0.
The field value of the required number of firings 67 in (see) is written.

When the instruction obtained by the instruction fetch is the store instruction for writing the data in the register to the specified location in the external memory, the instruction sequence control unit 14 instructs the token generation unit 12 to execute the instruction. , Token generator 1
At 2, the write request token shown in format 55 of FIG. 2 is generated.

The format of the store instruction is shown by reference numeral 75 in FIG. The format 75 is an instruction code 76 indicating a store instruction,
It has a write address 77 for writing to the memory and a register identifier 78 for reading the data to be written.

The format 55 of the write request token is such that the write address 77 of the external memory in the store instruction 75 is the access address 57, the code for instructing the memory write as the operation performed by the memory access controller is the operation code 56, and the field of the store instruction is the field. 78
The field 59 has the data to be written, which is read from the register designated by. Field 58,
61 and 64 are not used. This write request token is sent to the memory access controller via the signal line 91 after generation.

If the instruction obtained by the instruction fetch is a jump instruction that changes the value of the program counter by the value indicated by the instruction, the value specified in the instruction is added to the program counter and its address is added. The process continues from. Also, for a branch instruction similar to this, it is determined whether to jump or to proceed directly to the execution of the instruction immediately after, depending on the immediately preceding calculation result.

When the instruction obtained by the instruction fetch is the instruction sequence end instruction which terminates the instruction sequence execution at the end of the instruction sequence, and the sequence end flag 65 in another instruction.
If is "1", the following operation is performed.

The value of the token number counter in the instruction string control unit 14 is decremented by one. After decrement this is 0
Then, the end of the program execution is notified to the outside through the signal line 90, and the arithmetic processor 1 stops. If it is not 0, then the instruction sequence control unit 14 controls the instruction sequence fetch operation to start the execution of the fetched instruction sequence. If no token exists in the token memory 13, the arithmetic processing unit 10 continues to wait until a token is obtained.

When the memory access controller receives the read request token (format 55), it reads data from the address indicated by the access address 57 according to the operation code 56, generates the token of format 50 in FIG. Send to. At this time, the value of the field 58 of the format 55 for the field 51,
For field 60, the value of field 61 of format 55,
The value read from the memory is stored in the data 53 as the flag 52.
"1" is given to. Further, the value of the frame identifier 64 of the received token is directly embedded in the corresponding field 63 of the return token.

When the memory access controller receives the write request token (format 55), it writes the data 59 in the address indicated by the access address 57 according to the operation code 56.

A token from the memory access controller whose format 52 of FIG. 2 has a field 52 flag of "1" is sent via the signal line 92 to the processor 1.
When it is input to, the load controller 21 performs the following operation.

First, the data 53 is written into the register designated by the field 60 in the frame designated by the field 63 of the token format 50 of FIG. In the cycle in which the arithmetic processing unit 10 is writing to the register, the load control unit 21 cannot write data at the same time.
The write request is held in the FO, and the write is performed when the write becomes possible for the first time. Further, when the instruction sequence is switched in the arithmetic processing unit 10, the start of execution of a new instruction sequence is delayed if necessary to complete all write requests in the FIFO.

When the writing is completed, then one row of the input token table 20 is addressed based on the frame identifier 63 in the token format 50, the field 23 of the number of already arrived of that row is incremented, and the value after the increment is the row. Is compared with the value of the required number of fires field 22.

If they are not equal to each other, the tokens necessary for restarting the instruction sequence have not arrived at all, and the tokens disappear there. If they are equal, it can be seen that the number of tokens necessary for restarting the instruction sequence has been input. Therefore, the number of arrived tokens 23 is reset to "0" and the arrival token is set after the flag 52 of the token format 50 is set to "0". It is added to the end of the FIFO of the token memory 13. F
In the IFO, every time the first token is fetched from the arithmetic processing unit 10, it is removed and the second token up to that point becomes the first token, and the order is incremented in the following order.

In the instruction sequence fetch operation in the arithmetic processing unit 10, the value of the execution start address 51 in the fetched token is set in the program counter. At the same time, the value of the frame identifier 63 is set in the frame register in the arithmetic processing unit 10. Then, the arithmetic processing of the instruction sequence is restarted from the instruction designated by the program counter.

The operation of the apparatus having the above-described structure that enables the achievement of the object of the present invention will be described. First, the realization of the method of the first invention will be described.

Memory address ad with load instructions La and Lb
It is assumed that the instruction Tab first needs the data to be fetched from dr1 and addr2 and loaded into the registers r1 and r2. In other words, the instruction sequence is Suppose At this time, Tab is a "target instruction" for the load instructions La and Lb.

On the other hand, when the instruction string is given, it is possible to find the corresponding target instruction for all load instructions and obtain the value of the code address thereof at the time of compilation, so that the read request tokens at La and Lb can be obtained. If the address of Tab is given as the execution start address, the execution can be restarted from that time.

In order to realize this method, at the time of compilation, 1. 1. Obtain the address of the target instruction for all load instructions as described above, 2. Embed it at each load instruction in program memory (field 66 in Figure 3); When the target instruction requires n pieces of data to restart the execution of the instruction sequence, "n" is embedded in the field 67 of the instruction. 3. In the method of the first invention, this is "2" or "1". For each target instruction, set the sequence end flag 65 of the instruction immediately before it.
1 ″ 5. For other instructions, instruction sequence end flag 6
Pre-processing of setting 5 to "0" is performed.

According to this at the time of execution, as described in the explanation of the operation, 1. If there is a load instruction La in a certain instruction sequence, a token with the address of the target instruction Tab as the execution start address is issued there, and at the same time, the data necessary for restart that was written in the field 67 of the load instruction format 70 in advance. 1. Write the number into the required firing field 22 of the input token table 20. Therefore, the instruction sequence is continued without interruption. The sequence end flag 65 of the executed instruction is "1".
If so, then simply stop executing the sequence of instructions (simply “disappear”). 4. Read the next instruction sequence from the token memory 13. Whenever the token returns from the memory access, the data in the token is written in the register and the number of fields 2 of the arrival of the input token table 20 has already arrived.
The number of arrivals is counted using 3 as a counter, and the number of required firings is 2
5. When equal to 2, token is sent to token memory 13. When the tokens are fetched from the token memory 13 and the order is calculated, 7. The process proceeds in the procedure of continuing the process from the Tab command.

This state can be illustrated as shown in FIG. Here, the thin broken arrow below indicates the data dependency from the load instruction to its target instruction, the vertical bar indicates that the instruction sequence is cut immediately before the target instruction and the instruction sequence execution is interrupted, and the thick bold arrow above. The dashed arrow indicates that the read request token having the address of the target instruction Tab as the execution start address is issued and the instruction sequence execution is restarted from the target instruction.

For example, in the above program example, La, L
At the time of execution of b, with Tab as the execution start address, the processing is continued after the token whose required number of firings is "2" is issued, and the instruction sequence execution is interrupted immediately before Tab. After that, when counting the return of two tokens, the instruction sequence becomes executable, and when the turn comes in the token memory 13, the execution is restarted from the instruction Tab.

The method for loading the target instruction when the number of data required by the target instruction is at most 2 and restarting from the target instruction has been described above.

Generally, when it is necessary to restart the instruction sequence execution when n pieces of data arrive for the number n of 3 or more, the method of the third invention is used. In this case, "n" is set to the required firing number 67 of the load instruction format 70 of FIG. 3 at the time of compilation, and "n" is set to the required firing number field 22 in the input token table 20 of FIG. 4 at the time of execution.
Is set. The number of already arrived fields 23 is counted from the initial value "0", and the token is sent to the token memory 13 when it becomes equal to "n".

The method of interrupting all the load instructions for the target instruction requiring the binary data immediately before the target instruction and restarting from the target instruction when all the data tokens have arrived has been described above.

However, when there is a jump instruction between these two instructions and the instruction jumps in the direction opposite to the instruction sequence (the direction in which the program counter decreases), it is difficult to find the target of the load instruction in the analysis during compilation. Sometimes. In this case, it is difficult to find the target with one pass, or table management becomes complicated.

In such a case, according to the method of the fourth invention, this jump instruction is regarded as the target instruction in the first and third inventions, interrupted before it, and the address in the program is restarted. It is given as the target instruction address.

Further, in a branch instruction that branches conditionally according to the operation result, there is a case where one of the branches uses a register and therefore has a target, but the other cannot find the target. In this case, the branch instruction is dealt with similarly as the target instruction.

As described above, according to the fourth invention, even in the case where an instruction which hinders the implementation of the method of the first invention exists between the load instruction and the target instruction, this is statically compiled at the time of compilation. Controls can be embedded to detect and discover and use suitable targets.

As described above, when all data tokens arrive by interrupting immediately before the target instruction or at an instruction point between the load instruction and the target instruction for all the load instructions for the target instruction requiring the binary data I explained how to restart from the target instruction.

However, when a plurality of sections from the load instruction to the target instruction are overlapped, a token having a different target address is issued from the arithmetic processor 1 at the same time, and then a token for the target instruction located later is first input. There is a problem in that correct operation is not guaranteed, such as performing an erroneous operation.

The fifth invention solves this problem as follows. Load instructions La and Lb and their target instructions T
It is assumed that ab are arranged in this order, and in addition, the load instruction Lc and its target instruction Tc are in the same instruction sequence.

At the time of compilation, the order of a plurality of load instructions and respective target instructions is analyzed. When there is no other load instruction between the load instruction La and its target instruction Tab, (a) the target instruction is changed to load instructions La and Lb as in the method of the first invention.
1. In the restart command, the required number of firings is set to "2", and (b) the sequence end flag is set so as to be interrupted immediately before the target command. When another load instruction is sandwiched between the load instructions La and Lb, (a) the address of the sandwiched load instruction Lc is used as a restart instruction for execution of the load instruction La,
The required number of firings is set to "1", (b) the load instruction Lc is interrupted immediately before execution, (c) the restart instruction of Lc is set to Lb, the required number of firings is set to "1", and (d) Lb is restarted. Set the command to Tab and the required number of firings to "1". When another load instruction is sandwiched between the load instruction Lb and the target instruction Tab, the address of the sandwiched load instruction Lc is set in (a).
b Resumption of execution, set the required number of firing to "2",
(B) The load instruction Lc is interrupted immediately before it is executed. (C) The restart instruction of Lc is set to Tc, and the required number of firings is set to "
Using the program memory obtained as a result of this compilation which is set to 1 ″, the arithmetic processor operates as follows at the time of execution.

1. When there is no other load instruction between the load instruction La and its target instruction Tab, the operation is similar to that of the first invention. When the load instruction Lc is sandwiched between the load instructions La and Lb (see FIG. 7A), (a) when the load instruction La is executed, the sandwiched load instruction Lc is started to be executed. Issue a token as an address to continue the sequence, (b) interrupt the instruction sequence processing immediately before the execution of the load instruction Lc,
The arithmetic processing unit 10 etches another instruction sequence. (C) The instruction sequence is restarted from Lc by the returned token. (D) At Lc, the load instruction whose target instruction is Lb is executed and then the sequence processing is continued. (E) After that, the instruction sequence is restarted from Lb by the returned token. (F) In Lb, the target instruction is Tab, and the load instruction that sets the required number of firings to "1" is executed, and then the sequence processing is continued. g) At this time, it is guaranteed that the data required by Tc has been loaded, so Tc can be executed as it is. (h) Instruction sequence processing is interrupted immediately before Tab and arithmetic processing is performed. Part 1
0 fetches another instruction sequence (i) The instruction sequence is restarted from Tab by the returned token. When the load instruction Lc is sandwiched between the load instruction Lb and the target instruction Tab (see FIG. 7B), (a) When the load instruction La is executed, Lc is used as the execution start address and the firing is required. Continue the sequence by issuing a token with the number "2" (b) When executing the load instruction Lb, issue the token with the execution start address Lc and the number "2" required to fire and continue the sequence (c) Immediately before executing the load instruction Lc, the instruction sequence processing is suspended,
The arithmetic processing unit 10 etches another instruction sequence. (D) After that, the instruction sequence is restarted from Lc after returning two tokens. (E) In Lc, after executing a load instruction whose target instruction is Tc, the sequence of Continue processing. (F) At this time, it is guaranteed that the data required by Tab has been loaded, so Tab can be executed as it is. (G) Instruction sequence processing is suspended immediately before Tc. The arithmetic processing unit 1
0 fetches another instruction sequence (h) The instruction sequence is restarted from Tc by the token returned from Lc Generally, when there are multiple load instructions having other target instructions between the load instruction and its target instruction. However, as described above, when another load instruction is closer than the target instruction of each load instruction Lx, the next load instruction Ly can be used as a restart instruction to perform a correct operation.

[0073]

According to the first and second aspects of the present invention, the addresses of the target instruction that requires two data and the address of the load instruction are checked in advance, and two tokens are issued before the instruction sequence execution is interrupted. By delaying immediately before the instruction, even when the number of instruction sequences that can be executed in parallel is small, the number of cycles in which the arithmetic processing unit is idle can be reduced, and higher processing performance can be realized. Also, the two memory accesses can be overlapped to speed up the processing. In this state, in FIG. 6, the time elapse for execution of one instruction sequence is (A) in the conventional method and (B) in the method that is not yet known, but the processing time is as shown in (C). It means that it can be shortened.

In the third invention, the above invention is generalized,
Even when there is a target instruction that requires n data, it is possible to determine the arrival of n data tokens and start the instruction sequence execution. This method enables not only data loading but also high-speed realization of barrier synchronization that starts a certain operation after arrival of event completion information in n processes in parallel processing.

In the fourth invention, in addition to the operation described above, the above invention is generalized, and there is an instruction between the load instruction and the target instruction which is an obstacle to the implementation of the method of the first invention. Even then, it is possible to embed control that statically detects this at compile time to find and use an appropriate restart instruction, thereby enabling a similar effect to be realized.

In the fifth invention, in addition to the operation described above, even if two or more load instructions and target instructions interfere with each other, the restart address after interruption can be set so as to resolve the interference. To

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic processor that is an embodiment of the present invention.

FIG. 2 is a format diagram showing a format of a token used in this embodiment.

FIG. 3 is a format diagram showing the format of an instruction used in this embodiment.

FIG. 4 is a block diagram showing a configuration of a load control unit used in this embodiment.

FIG. 5 is a diagram showing the method of the first invention.

FIG. 6 is a time chart comparing execution states of the conventional method and the method of the present invention.

FIG. 7 is a diagram showing a method of the fifth invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 arithmetic processor 10 arithmetic processing unit 11 register unit 12 token generation unit 13 token memory 14 instruction sequence control unit 21 load control unit

Claims (5)

[Claims] 1. An arithmetic processor that prepares a plurality of instruction sequences that can be executed in parallel in advance, selects one of them as an execution instruction sequence while switching them, and sequentially executes the instructions in the execution instruction sequence. The operation of the two pieces of data from the memory while executing the first instruction sequence including the target instruction to be executed using the two pieces of data after completion of the load operation of the first and second pieces of data In a data loading method of loading into a processor, a first token including an address of the target instruction that uses the first data is externally executed when a first load instruction that loads the first data from the memory is executed. Issuing and activating a memory access operation, continuing execution of the first sequence of instructions, and then loading the second data from the memory; When the second load instruction is executed, the second
Issue a second token including the address of the target instruction using the data of the above to activate the memory access operation and continue the execution of the first instruction sequence, and then immediately before the target instruction. Execution of the first instruction sequence is interrupted, execution of another instruction sequence is executed, the memory access operation is terminated, and the number of input tokens input to the arithmetic processor having data necessary for the target instruction is counted, The data loading method, wherein when the result of the counting becomes 2, execution of the first instruction sequence is restarted from the target instruction by the address of the target instruction included in the input token. 2. An arithmetic processor that prepares a plurality of instruction sequences that can be executed in parallel in advance, selects one of the instruction sequences as an execution instruction sequence while switching them, and sequentially executes the instructions in the execution instruction sequence, An arithmetic processing unit that sequentially executes instructions in one instruction sequence, a token memory that holds a token input from the outside and supplies the token to the arithmetic processing unit, and a register group that holds data accessed from the arithmetic processing unit. And the input / output information of the token including the description of the operation performed externally and the restart instruction address to be restarted after interrupting the execution of the instruction sequence described in the instruction code being executed at that time The memory read data in the token is counted before holding the token that has been counted and returned to the arithmetic processor from the outside in the token memory. Load controller for writing data to a register in a register group, each load instruction has the restart instruction address and the required number of firings, which is the number of arrival tokens required for restart, and for each instruction, the instruction immediately after execution of that instruction And a command sequence control unit that stores a program including a command group having a flag indicating whether or not to continue execution, supplies a command sequence to the arithmetic processing unit, and controls the operation of each unit. Arithmetic processor. 3. When the first instruction sequence includes a target instruction to be executed using the n data after the end of the load operation of the n data, each of the n data is When the load instruction to be loaded is executed, a token including the address of the target instruction is issued to the outside to activate the memory access operation, and the execution of the first instruction sequence is continued, and then immediately before the target instruction. Execution of the first instruction sequence is interrupted, execution of another instruction sequence is executed, the memory access operation is terminated, and the number of input tokens having data necessary for the target instruction is counted. When it becomes, the execution of the first instruction sequence is restarted from the target instruction by the address of the target instruction included in the input token. The method for loading data according to claim 1, wherein 4. When a load instruction is executed, a token including the address of an instruction (which is called a restart instruction) between the load instruction and the target instruction instead of the target instruction is issued to the outside to perform a memory access operation. When the token having the address of the restart instruction is input for a predetermined number of times, the start of the instruction sequence is suspended immediately before the restart instruction The data loading method according to claim 3, wherein the data loading method is resumable. 5. When a plurality of load instructions and respective target instructions exist for an instruction that requires two data for instruction execution in the instruction sequence, the first instruction for all load instructions is set. When there is no other load instruction between the first load instruction and the target first target instruction at the time of executing the load instruction, the first load instruction sets the first target instruction as a restart instruction, A second load instruction having another load instruction and a load instruction closest to the first load instruction having another second target instruction;
When the first load instruction is a second load instruction, the first load instruction is the second load instruction as a restart instruction, another load instruction exists, and the load instruction closest to the first load instruction is the same as the first target. When it is a third load instruction having an instruction, the first load instruction uses the same instruction as the restart instruction of the third load instruction as its restart instruction, and for all the instructions, a certain instruction is one of the load instructions. Immediately before the restart instruction, the execution of the instruction sequence to which the certain instruction belongs is interrupted, and when there are two load instructions that use the certain instruction as the restart instruction, two tokens having the restart instruction arrive. The data loading method according to claim 4, wherein the instruction sequence to which the instruction belongs can be restarted from the certain instruction at the time of performing.