JPH06276104A - Huffman decoding circuit - Google Patents

Abstract

PURPOSE:To obtain the Huffman decoding circuit of a small circuit scale, which can operate at high speed. CONSTITUTION:The Huffman decoding circuit includes plural Huffman code registers 21, 22,..., 2n, plural code filter circuits 31, 32,..., 3n and plural coincidence detecting circuits 41, 42,..., 4n in correspondence to plural Huffman codes. The Huffman decoding circuits furthermore includes a Huffman table 10 storing plural pieces of decoding data corresponding to the plural Huffman codes. The respective Huffman coding registers store the corresponding Huffman codes. The respective code filter circuits allow to pass only the part corresponding to the code length of the corresponding Huffman code in given compressed data. The respective coincidence detecting circuits compare output data of the corresponding code filter circuit and that of the corresponding Huffman code register, generate an output signal at the time of coincidence and give the output signal to the Huffman table 10 as an address signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Huffman decoding circuit for decoding a Huffman code encoded by the Huffman coding method.

[0002]

2. Description of the Related Art Image data contains a very large amount of information. Therefore, it is not practical to process the image data as it is in terms of memory capacity and communication speed. Therefore, image data compression technology is important.

J is one of the international standards for image data compression.
PEG (Joint Photographic Ex)
pert Group). DCT (discrete cosine transform) method for lossy coding and DP in two-dimensional space
A reversible coding method for performing CM (Differential PCM) is adopted. The DCT method image data compression will be described below.

FIG. 4 is a block diagram showing the basic configuration of a system for executing the DCT method.

On the encoding side, the DCT device 100 performs DCT conversion on the input original image data and outputs DCT coefficients. The quantizer 200 has a quantization table 400.
, The DCT coefficient is quantized and a quantized DCT coefficient (hereinafter referred to as a quantized DCT coefficient) is output. The entropy encoder 300 refers to the encoding table 500, performs entropy encoding processing on the quantized DCT coefficient, and outputs compressed data. The Huffman coding method is used as the entropy coding method.

On the decoding side, the entropy decoder 600
Performs entropy decoding processing on the compressed data with reference to the encoding table 500, and outputs the quantized DCT coefficient. The inverse quantizer 700 refers to the quantization table 400 to perform inverse quantization processing on the quantized DCT coefficient,
Output the T coefficient. The inverse DCT device 800 performs inverse DCT conversion on the DCT coefficient and outputs reproduced image data.

As shown in FIG. 5, each compressed data (code data) is composed of a variable-length Huffman code and a variable-length additional bit. The code length of the Huffman code and the code length of the additional bits differ depending on each compressed data.

FIG. 6 is a block diagram showing the configuration of the main part of a conventional Huffman decoding circuit. Huffman table 1
Consists of a memory circuit having a storage capacity of 2 ^m words. Here, m represents the maximum code length of the Huffman code. A static random access memory (SRAM), a dynamic random access memory (DRAM), or the like is used as the memory circuit.

Address input terminal A of Huffman table 1
The leading m bits of the compressed data are given to D as an address signal. At each address in the Huffman table 1, decoded data corresponding to the Huffman code represented by the address is stored.

For example, assuming that the maximum code length m of the Huffman code is 16, the Huffman code "1111" having a 16-bit length.
The decoded data corresponding to "111111110101" is
It is stored at the address “11111111111110101”. 15-bit Huffman code “1111111”
The decoded data corresponding to 11000010 "is stored in two addresses" 111111111000010X ", where X represents 0 and 1. Further, the decoded data corresponding to the 2-bit Huffman code" 01 "is 2
¹⁴ addresses "01XXXXXXXXXXXXXXXX"
Stored in.

As described above, since the Huffman table 1 is provided with 16-bit compressed data corresponding to the maximum code length as an address signal, the decoded data corresponding to the Huffman code shorter than the maximum code length has a plurality of addresses. Must be stored in.

For example, when the compressed data includes a 2-bit Huffman code "01", 16-bit compressed data "01 ..." Is given to the Huffman table 1 as an address signal. As a result, the decoded data stored at the address “01 ...” Is read, and the data output terminal D
It is output from O. In this way, the Huffman code included in the compressed data is decoded.

[0013]

As described above, in the conventional Huffman decoding circuit, the maximum code length m of the Huffman code is m.
Since the compressed data having the number of bits corresponding to is given to the Huffman table 1 as an address signal, the memory capacity of the memory circuit forming the Huffman table 1 requires 2 ^m words. In this case, the decoded data corresponding to the Huffman code shorter than the maximum code length m is stored at a plurality of addresses. When the number of Huffman codes is n, the utilization efficiency of the memory circuit is n / 2 ^m .

As described above, in the conventional Huffman decoding circuit, it is necessary to write extra decoded data in a number of addresses much larger than the number of Huffman codes, and the utilization efficiency of the memory circuit is very low. As a result, the circuit scale of the Huffman decoding circuit becomes large, and it becomes difficult to increase the processing speed.

An object of the present invention is to provide a Huffman decoding circuit capable of performing Huffman decoding processing at high speed with a small circuit scale.

[0016]

(1) First invention A Huffman decoding circuit according to the first invention is a Huffman decoding circuit for decoding a plurality of Huffman codes each having an arbitrary code length. And includes a decoded data storage means, a plurality of Huffman code storage means, a plurality of filter means, a plurality of match detection means, and a selection means.

The decoded data storage means stores a plurality of decoded data respectively corresponding to a plurality of Huffman codes. The plurality of Huffman code storage means are provided corresponding to the plurality of Huffman codes, and store the corresponding Huffman codes.

A plurality of filter means are provided corresponding to a plurality of Huffman codes, each receives code data including a Huffman code to be decoded, and a portion of the code data corresponding to the code length of the corresponding Huffman code. Pass through.

The plurality of coincidence detecting means are provided corresponding to the plurality of Huffman codes, and detect the coincidence between the Huffman code stored in the corresponding Huffman code storage means and the output data of the corresponding filter means. The selecting means selects any of the plurality of decoded data stored in the decoded data storage means in response to the output signals of the plurality of match detecting means.

(2) Second Invention In the Huffman decoding circuit according to the second invention, each of the plurality of filter means includes a filter data storage means and a logic gate means.

The filter data storage means stores filter data having a bit length corresponding to the code length of the corresponding Huffman code. The logic gate means receives the code data and the filter data output from the corresponding filter data storage means, and outputs a portion of the code data corresponding to the filter data.

(3) Third Invention In the Huffman decoding circuit according to the third invention, the Huffman code storage means includes a plurality of registers corresponding to a plurality of Huffman codes.

[0023]

In the Huffman decoding circuit according to the first to third inventions, the code data including the Huffman code to be decoded is given to the plurality of filter means. Each filter means passes a portion of the code data corresponding to the code length of the corresponding Huffman code. The match detection means is
The output data of the corresponding filter means is compared with the Huffman code stored in the corresponding Huffman code storage means to detect whether or not they match. The selecting means selects any one of the plurality of pieces of decoded data stored in the decoded data storage means based on the comparison result of the plurality of match detecting means.

In this Huffman decoding circuit, the decoded data storage means needs to store the same number of decoded data as the number of Huffman codes, so that the storage capacity of the decoded data storage means becomes small. Therefore, it becomes possible to configure the decoded data storage means by a register. as a result,
The processing speed is increased.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A Huffman decoding circuit according to an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the Huffman decoding circuit of this embodiment. This Huffman decoding circuit is used for decoding a DC Huffman code, for example. In this embodiment, the number of Huffman codes is n,
The maximum code length of the Huffman code is m.

The Huffman decoding circuit of FIG. 1 includes a Huffman table 10 composed of a memory circuit, n Huffman code registers 21, ..., 2n, and n filter circuits 31, 3.
2, ..., 3n and n match detection circuits 41, 42,
..., including 4n.

Huffman code registers 21, 22, ..., 2
n is provided corresponding to each of the n Huffman codes. A corresponding Huffman code is stored in each Huffman code register.

N filter circuits 31, 32, ..., 3n
Are provided respectively corresponding to n Huffman codes.
The filter circuit 31 includes a sign filter register 51 and A
It includes an ND gate 61. The filter circuit 32 includes a sign filter register 52 and an AND gate 62. Similarly, the filter circuit 3n includes a sign filter register 5n and an AND gate 6n.

Each code filter register stores filter data having a bit length corresponding to the code length of the corresponding Huffman code. One input terminal of the AND gate 61 is supplied with m-bit compressed data (code data), and the other input terminal is supplied with output data of the code filter register 51. One input terminal of the AND gate 62 is supplied with m-bit compressed data, and the other input terminal is supplied with output data of the sign filter register 52. Similarly, one input terminal of the AND gate 6n has m
Bit-compressed data is given, and the output data of the sign filter register 5n is given to the other input terminal.

The AND gate 61 outputs a portion of the m-bit compressed data corresponding to the filter data stored in the sign filter register 51. AND gate 62
Outputs a portion of the m-bit compressed data corresponding to the filter data stored in the sign filter register 52. Similarly, the AND gate 6n outputs a part of the m-bit compressed data corresponding to the filter data stored in the sign filter register 5n.

N match detection circuits 41, 42, ..., 4n
Are provided corresponding to n Huffman codes. The coincidence detection circuit 41 compares the output data of the AND gate 61 with the output data of the Huffman code register 21, and generates an output signal A1 when they coincide with each other. Match detection circuit 4
2 compares the output data of the AND gate 62 with the output data of the Huffman code register 22, and generates an output signal A2 when they match. Similarly, the match detection circuit 4n compares the output data of the AND gate 6n with the output data of the Huffman code register 2n, and when they match, generates an output signal An.

The output signals of the coincidence detection circuits 41, 42, ..., 4n are applied as address signals to the address input terminal AD of the Huffman table 10. Huffman table 10
Stores n pieces of decoded data respectively corresponding to n pieces of Huffman code. Output signal A of the coincidence detection circuit 41
At the address designated by 1, the decoded data corresponding to the Huffman code stored in the Huffman code register 21 is stored. Decoded data corresponding to the Huffman code stored in the Huffman code register 22 is stored at the address designated by the output signal A2 of the match detection circuit 42. Similarly, decoded data corresponding to the Huffman code stored in the Huffman code register 2n is stored at the address designated by the output signal An of the match detection circuit 4n.

When any of the output signals A1, A2, ..., An is given to the address input terminal AD of the Huffman table 10, the decoded data is read from the address designated by the output signal and is output from the data output terminal DO. Is output.

Next, an example of the operation of the Huffman decoding circuit shown in FIG. 1 will be described with reference to FIG. In FIG. 2, the Huffman code register 2i, code filter register 5i, AN
D-gate 6i and match detection circuit 4i are shown. Here, i represents any one of 1 to n. Further, in the example of FIG. 2, the maximum code length m of the Huffman code is 16.

In this case, the Huffman code register 2i is 1
It has a 6-bit length, and the code filter register 5i also has a 16-bit length. As shown in FIG. 2, a Huffman code “11011” having a 5-bit length is stored in the Huffman code register 2i. 0 is stored in the remaining 11 bits of the Huffman code register 2i. The code filter register 5i stores 5-bit length filter data "11111". 0 is stored in the remaining 11 bits of the sign filter register 5i.

One of the input terminals of the AND gate 6i has 5
When 16-bit compressed data including the bit length Huffman code "11011" is given, the output data of the AND gate 6i becomes "1101100000000". The match detection circuit 4i outputs the output data “1101100000000000000” of the AND gate 6i and the output data “11011000000” of the Huffman code register 2i.
Compare with 00000 ".

In this case, since the two coincide with each other, the coincidence detection circuit 4i generates the output signal Ai. The output signal Ai is
It is applied to the address input terminal AD of the Huffman table 10 shown in FIG. As a result, Huffman table 10
At, the decoded data is read from the address designated by the output signal Ai.

FIG. 3 is a block diagram showing an example of the configuration of the Huffman table 10. This Huffman table 10
Is n registers 10 corresponding to n Huffman codes.
, 10n and a combination circuit 110.

The register 101 stores the decoded data corresponding to the Huffman code stored in the Huffman code register 21 of FIG. The register 102 stores the decoded data corresponding to the Huffman code stored in the Huffman code register 22 of FIG. Similarly, register 10n
Stores the decoded data corresponding to the Huffman code stored in the Huffman code register 2n of FIG.

In the combinational circuit 110, the coincidence detection circuits 41, 42, ..., 4n of FIG.
Output signal is given. The combinational circuit 110 is responsive to the applied output signal to register 101, 102,
, 10n is selected. Thereby, the decoded data is output from the selected register.

For example, combinational circuit 110 selects register 101 in response to output signal A1 of FIG. Further, the register 102 is selected in response to the output signal A2 of FIG. Similarly, in response to the output signal An of FIG.
Select 0n.

In the embodiment of FIG. 1, it is sufficient to store n pieces of decoded data corresponding to n pieces of Huffman code in the Huffman table 10, so that the storage capacity of the Huffman table 10 becomes small. Further, the utilization efficiency of the Huffman table 10 is improved to 100%. As a result, the hardware configuration required for the Huffman table 10 is simplified,
The circuit scale is also greatly reduced.

Further, as shown in FIG. 3, the Huffman table 10 is integrated into an IC by a plurality of registers and combination circuits.
Can be configured on. As a result, the processing speed can be easily increased.

In the above embodiment, each filter circuit is composed of the code filter register and the AND gate, but each filter circuit corresponds to the code length of the corresponding Huffman code in the given m-bit compressed data. Other circuit configurations may be used as long as they have a function of passing only the bit to be passed.

Further, in the above embodiment, the Huffman table is composed of the register and the combinational circuit, but the Huffman table may be composed of the memory including the memory cell selection circuit.

[0047]

As described above, according to the present invention, since it is sufficient to store the same number of decoded data as the number of Huffman codes in the decoded data storage means, the storage capacity and the circuit scale of the decoded data storage means can be increased. Get smaller.

Further, since the storage capacity of the decoded data storage means may be small, the decoded data storage means can be constituted by a register. Thereby, the processing speed is increased.

As a result, a Huffman decoding circuit that can operate at high speed and has a small circuit scale can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a Huffman decoding circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an example of the operation of the Huffman decoding circuit in FIG.

3 is a block diagram showing an example of a configuration of a Huffman table included in the Huffman decoding circuit of FIG.

FIG. 4 is a block diagram showing a basic configuration of a DCT image data compression system.

FIG. 5 is a diagram showing a structure of compressed data.

FIG. 6 is a block diagram showing a configuration of a main part of a conventional Huffman decoding circuit.

[Explanation of symbols]

 10 Huffman Table 21, 22, 2n Huffman Code Register 31, 32, 3n Filter Circuit 41, 42, 4n Match Detection Circuit 51, 52, 5n Code Filter Register 61, 62, 6n AND Gate 101, 102, 10n Register 110 Combination Circuit A1, A2, An output signal AD address input terminal DO data output terminal In the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (3)

[Claims] 1. A Huffman decoding circuit for decoding a plurality of Huffman codes each having an arbitrary code length, the decoded data storage storing a plurality of decoded data respectively corresponding to the plurality of Huffman codes. Means, a plurality of Huffman code storage means provided corresponding to the plurality of Huffman codes, each storing a corresponding Huffman code, and provided corresponding to the plurality of Huffman codes, each should be decoded A plurality of filter means for receiving code data including a Huffman code and passing a portion of the code data corresponding to the code length of the corresponding Huffman code, and provided corresponding to the plurality of Huffman codes, each corresponding A plurality of match detections for detecting a match between the Huffman code stored in the Huffman code storage means and the output data of the corresponding filter means. Comprising means, and selection means for selecting one of the plurality of decoded data stored in the decoded data storage means in response to an output signal of said plurality of coincidence detecting means, Huffman decoding circuit. 2. Each of the plurality of filter means includes a filter data storage means for storing filter data having a bit length corresponding to the code length of a corresponding Huffman code, and the code data and the corresponding filter data storage means. The Huffman decoding circuit according to claim 1, further comprising a logic gate unit that receives the output filter data and outputs a portion of the code data corresponding to the filter data. 3. The Huffman decoding circuit according to claim 1, wherein the Huffman code storage unit includes a plurality of registers corresponding to the plurality of Huffman codes.