JPH06275648A - Method of forming thin film transistor - Google Patents

Abstract

PURPOSE:To improve the TFT characteristics in a CTFT circuit, by covering an N-channel TFT with an insulative mask in the case of current cure of a P-channel TFT, and preventing an effective voltage from being applied to the gate insulating film of the N-channel TFT. CONSTITUTION:After gate electrodes 15p, 15n are formed by using material capable of anodic oxidation, the surfaces of the electrodes are subjected to anodic oxidation in electrolytic solution, and anodic oxidation material layers 16p, 16n are grown. Impurities are implanted in silicon regions 13n, 13p, by using the gate electrodes 15p, 15n, and anodic oxidation material around the electrodes as masks. Thus an N-type impurity region 17 is formed. Only the region 13n of the N-channel TFT is covered with insulative mask material 18, and the whole part is again dipped in the electrolytic solution. A negative voltage is applied to the gate electrodes 15p, 15n, and current cure is performed. In this case, an effective voltage is not applied to the gate insulating film of the N-channel TFT, and current cure is not performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT) having a non-single crystal semiconductor thin film. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are distinguished as an amorphous silicon TFT or a crystalline silicon TFT depending on the material / crystal state of the semiconductor used.

A crystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. Also, with crystalline silicon, not only NMOS TFTs but also PMOS TFTs can be obtained in the same way, so CMO
It is possible to form S circuits. Therefore, particularly recently, TFTs using crystalline silicon have been actively researched.

[0004]

In producing such a gate insulation type element from the past results, it is the gate insulation film which is the thermal oxide film of silicon that has the best characteristics. However, to obtain a thermal oxide film, 1000
It was necessary to treat at a temperature of about ° C. Since the substrate material to be used is limited at such a temperature, an insulating film produced by sputtering or various chemical vapor deposition (CVD) methods has been used for producing such a TFT.

Since the production of these insulating films does not require a high temperature, the restriction on the substrate has been resolved. On the other hand, the insulating film produced by such a vapor phase growth method has a problem that the interface state density is high and many defects such as pinholes are present. And
Regarding the repair (repair) of such defects and the improvement of the characteristics, no treatment can be performed after the film formation, and the current situation is that the film formation conditions are exclusively optimized.

In the research conducted by the present inventor, it was found that the characteristics of the TFT are remarkably improved when a positive or negative voltage is applied between the gate electrode and the semiconductor layer across the gate insulating film. This effect will be referred to as current curing or current annealing. Regarding the applied voltage, the current cure effect does not occur in any case. For example, in the case of an N-channel TFT (source and drain are N-type), it is necessary to apply a positive voltage to the gate electrode. On the contrary, the characteristics could not be remarkably improved. Also in the case of a P-channel TFT (P-type source and drain), it is preferable to apply a negative voltage to the gate electrode in the same manner.

Such current curing effect is caused, in part, by filling the pinholes in the oxide film due to the electrochemical effect. That is, when the thickness of the gate insulating film is non-uniform, ions (mainly oxygen ions) move by the applied voltage so as to smooth the non-uniform portion. As a result, the gate insulating film TFT
The homogeneity within is improved.

The other is that the heat generated by the electric current brings about the same effect as the annealing treatment at a substantially high temperature. That is, fixed charges are swept away, and appropriate ions and unpaired bonds of silicon are bonded to the unpaired bonds to reduce the interface state density. Although a high temperature of about 1000 ° C. is required to perform such a process over the entire substrate, current cure is performed at room temperature or in a liquid under cooling for the entire substrate. However, micro processing is performed with energy (about 0.1 eV) corresponding to 1000 ° C. in a very small area of the gate insulating film, which is a particular problem.

For example, FIG. 2 shows a state in which the source and drain of the TFT have the same potential and a voltage is applied between this and the gate electrode. (FIGS. 2A to 2D)
1A and 1C are energy band diagrams in the AA 'cross section in FIG. In addition, FIG.
FIG. 1D shows an energy band diagram of a BB ′ cross section in FIG. Here, it is assumed that the source and drain are not doped, and that they are as intrinsic as the active region under the gate electrode. 2 (A) and (B)
Is a positive voltage applied to the gate electrode, and FIGS. 2C and 2D are negative voltage applied to the gate electrode. In both cases, the band is sharply bent in the vicinity of the gate electrode and the gate insulating film under the influence of the applied voltage, and deep inversion is formed in the vicinity of silicon at the silicon oxide-silicon interface. Then, the electrons and holes are accelerated in the steep part of the energy band as shown in FIGS. 2 (A) and 2 (C),
Recombines with each other via recombination centers. Then, this recombination loses kinetic energy, heat energy is locally generated, and unpaired bonds are recombined and neutralized. Further, as shown in FIGS. 2B and 2D, electrons or holes rush from the inside of the semiconductor into the gate insulating film with high energy through the interface. Then, the electrons and holes collide with the lattice, and a large amount of heat is locally generated.

[0010]

Although the above effects can be clearly confirmed experimentally, it was very difficult to carry out the method in mass production. One problem was how to apply a voltage to the semiconductor region and the gate electrode.

Although it is experimentally possible to connect the gate electrode and the semiconductor region with an electric wire, such a method is not practical for mass production. With regard to this problem, the inventor has come up with using an electrolytic solution at room temperature or cooled. This solution has the function of a cool sink (cooling medium) that prevents local heating from occurring too much and causing permanent destruction.
When the operation is outlined, for example, a TFT as shown in FIG.
Consider the element. The TFT is formed on the substrate 1 and the base insulating film 2, and has an island-shaped semiconductor region (three regions 3a, 3b, 3c).
The gate insulating film 4 and the gate electrode 5 are formed.
An insulating film 6 is formed around the gate electrode 5. This insulating film 6 is extremely important when an electrolytic solution is used. As the insulating film 6, it is usually preferable to use an oxide film obtained by anodizing the gate electrode.

Although only one TFT is shown in the figure, it is assumed that several TFTs exist independently on the same substrate. Then, by applying a voltage to the gate electrode, a potential difference is generated above and below the gate insulating film,
Current cure can be performed.

An equivalent circuit of such a TFT is shown in FIG.
Shown in. That is, the potential of the gate electrode is V _G. When viewed from the gate electrode, the insulating film 6 (resistor R
₁ ) to the electrolytic solution, the route to reach the electrolytic solution through the gate insulating film 4 (resistor R ₂ ) below the gate electrode, the semiconductor region 3 (resistor R ₄ ) and again the gate insulating film 4 (resistor R ₃ ). There are two types. It will be apparent that the value of the voltage V _CG applied to the gate insulating film below the gate electrode changes depending on the size of the resistors R ₁ , R ₂ , R ₃ and R ₄ .

[0014] For example, given the anodic oxidation process, according to the insulating film 6 is grown, R ₁ becomes larger to some extent above, R ₁ becomes large, equal sized and R _2, R _3, R ₄ Then, V _CG rapidly increases.

As a result, current curing is performed even during anodic oxidation. In particular, this current cure has favorable results for N-channel TFTs because a positive voltage is applied to the gate electrode. However, in the CMOS circuit (or CTFT circuit), there is also a P-channel TFT. In this anodic oxidation process, an unfavorable voltage is applied to the P-channel TFT, so it is necessary to cure the current with a negative voltage only in the P-channel TFT after the anodic oxidation process. However, at this time, it is not preferable to apply a negative voltage to the N-channel TFT.

To avoid this difficulty, the P channel T
It is general that the gate electrodes of the FT and the N-channel TFT are separately provided so that the voltages are independently applied to the gate electrodes. However, in the CTFT circuit, the gate electrodes of the N-channel TFT and the P-channel TFT are often connected to each other. Therefore, if a voltage of another system is supplied in this way, a pattern for connecting them later is required. Become.

The present invention provides an answer to such a difficulty, and its technical idea is to cover the N-channel TFT with an insulating mask during the current cure of the P-channel TFT so that an effective voltage can be obtained. Is not applied to the gate insulating film of the N-channel TFT. In particular, as this mask, a special mask is not prepared, but a doping mask of a P-channel TFT is used, which can be performed without increasing the number of manufacturing steps.

Therefore, the P-type impurity may be doped before and after the current curing. Several variations of the present invention are conceivable from the above idea. The basic process consists of five basic steps: anodic oxidation of all gate electrodes (current cure of N-channel TFT) N-type impurity doping (overall doping) P-channel TFT mask formation P-channel TFT current cure P-type impurity doping It is a combination of steps. Here, the first step is, and the subsequent steps may be considered.
The following four patterns are conceivable and any of them can be executed. (A)->->->->(B)->->->->(C)->->->->(D)->->->->

The gate electrode may be made of aluminum, tantalum, silicon, titanium, tungsten, chromium or the like, which can form an insulating film by anodic oxidation. Further, it is desirable that such an electrolytic solution is kept at a constant temperature so that the reaction can be carried out uniformly. The present invention is characterized by using an electrolytic solution. However, since the electrolytic solution can be easily cooled (= thermal diffusion), it is possible to prevent destruction due to local excessive heat generation.

FIG. 4 shows an outline of an apparatus for performing current curing or anodic oxidation according to the present invention. The electrolytic bath 7 is filled with an electrolytic solution 8, and an electrode 10 having excellent oxidation resistance such as platinum and palladium and a substrate 9 are immersed in the electrolytic solution 8. Regarding the immersion of the substrate, a method of directly immersing in the solution as shown in FIG.
As shown in FIG. 4 (B), there are two possible methods of fixing the substrate 9 on the supporting plate 9A of the substrate and immersing it. A positive or negative voltage is applied to these electrodes and terminals A and B taken out from the substrate. Examples will be shown below to describe specific methods for carrying out the present invention.

[0021]

【Example】

Example 1 FIG. 3 shows a cross-sectional view of the manufacturing process of this example. This embodiment is an example of manufacturing a complementary TFT (CTFT) in which an N-channel TFT and a P-channel TFT are formed on the same substrate. First, a base film 12 of silicon oxide having a thickness of 2000Å was formed on a substrate (Corning 7059) 11 by a sputtering method. Further, an intrinsic (I-type) amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method, and a silicon oxide film having a thickness of 200 Å was further deposited thereon by the sputtering method. Then, this amorphous silicon film was annealed in a nitrogen atmosphere at 600 ° C. for 48 hours to be crystallized.

After the crystallization process, the silicon film is patterned to form island-shaped silicon regions 13p (for P-channel TFT).
And 13n (for N-channel TFT) are formed, and
A 1000 Å thick silicon oxide film 14 was deposited as a gate insulating film by the sputtering method. For sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is 200 to 400 ° C., for example 250 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example 0.1 or less. did.

Subsequently, by the sputtering method,
An aluminum film containing 0.5 to 3%, for example, 2% of silicon was deposited to a thickness of 1000 to 10000Å, for example 5000Å. In addition, it is desirable that the steps of forming the silicon oxide film and the aluminum film are continuously performed. Then, the aluminum film is etched with a mixed acid containing phosphoric acid as a main component to form the same film as the gate electrode 15p (for P-channel TFT).
n (for N-channel TFT) was formed.

Then, the substrate is immersed in an ethylene glycol solution of tartaric acid (1 to 5%, neutralized with ammonia), a positive voltage is applied to the gate electrode to pass an electric current, and the surface of the gate electrode is anodized. Oxide (aluminum oxide) layers 16p and 16n were grown. The potential of the gate electrode is initially 2 to 5 V / min, for example 4 V / min to 200 to 3 V / min.
The voltage was raised to 00 V, for example 250 V, and kept constant for 2 hours. The thickness of the anodic oxide obtained was determined by the magnitude of the applied voltage. Thickness of anodic oxide is 1
000-5000Å, especially 2000-3000Å was preferred. Here, it is set to 2500Å. (Fig. 3 (A))

Then, by the plasma doping method,
Impurities (phosphorus) were implanted into the silicon regions 33n and 33p using the gate electrode and the surrounding anodic oxide as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount was set to 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, the N-type impurity region 17 was formed. As is clear from the figure, the impurity region 17 and the gate electrode are in an offset state where they do not geometrically overlap. (Fig. 3 (B))

Next, a mask 18 is formed by photoresist.
Was formed to expose only the semiconductor region 33p of the P-channel TFT. Then, again, the substrate was immersed in an ethylene glycol solution of tartaric acid (1 to 5%, neutralized with ammonia), and a negative voltage was applied to the gate electrode to perform current curing. Then, since the gate electrode was positive, a current flowed as indicated by an arrow, and the current could be cured. The potential of the gate electrode is -30V at -4V / min at first
Raise to -80V, for example -60V, then 1
Kept constant for a time.

At this time, in the N-channel TFT as well, a negative voltage is applied to the gate electrode, but since the whole is covered with an insulating material, the insulation under the gate electrode is prevented. No specific voltage was applied to the membrane. Therefore, current curing is not performed for the N-channel type in this step. This is N channel T
This is convenient for the FT. That is, in the N-channel TFT, characteristics are deteriorated when a negative voltage is applied to the gate insulating film. (Fig. 3
(C))

Then, by the plasma doping method,
Impurities (boron) were implanted into the silicon region 13p of the P-channel TFT by using the mask 18, the gate electrode 15p and the surrounding anodic oxide 16p as a mask. Diborane (B ₂ H ₆ ) was used as the doping gas, and the acceleration voltage was 4
It was set to 0 to 80 kV, for example, 65 kV. 1x dose
10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁵ cm ^−2, which is larger than that of the previously doped phosphorus. As a result,
P-type impurity region 19p is formed. On the other hand, mask 1
The N-type impurity region 19 is formed in the N-channel region covered with
n were formed. (Fig. 3 (D))

Then, laser light was irradiated to perform laser annealing. KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
However, other lasers such as XeF excimer laser (wavelength 353 nm), XeCl excimer laser (wavelength 308 nm), ArF excimer laser (wavelength 193 nm) and the like may be used. The energy density of the laser was 200 to 500 mJ / cm ² , for example 250 mJ / cm ^2, and the irradiation was performed for 2 to 10 shots, for example, 2 shots, per location. At the time of laser irradiation, the substrate was heated to 100 to 450 ° C, for example 250 ° C. In this way, the impurities were activated. (Fig. 3 (E))

Then, a silicon oxide film 20 having a thickness of 6000Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
Source / drain region electrodes / wirings 21a, 21
b, 21c and 21d were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The thin film transistor was completed through the above steps. (Fig. 3
(F))

The field effect mobility of the manufactured thin film transistor is 70 to 100 cm ² / Vs at a gate voltage of 10V.
(N channel TFT), 50 to 90 cm ² / Vs (P channel TFT), threshold value is 2.0 to 3.5 V (N channel TFT), -2.5 to 4.0 V (P channel TF)
T). In addition, a shift register was formed using the manufactured thin film transistor. It was confirmed that the drain voltage was 15 V, the operation was 11 MHz, and the drain voltage was 18 V, the operation was 20 MHz.

[Embodiment 2] FIG. 4 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 3
An underlayer film 32 of silicon oxide having a thickness of 2000 Å was formed on the substrate 1 by sputtering. Furthermore, plasma CVD
Depending on the method, the thickness is 500-1500Å, for example 500Å
An intrinsic (I-type) amorphous silicon film is deposited and patterned to form an island-shaped silicon region 33p (P channel T
33n (for N channel TFT) and 33n (for FT) were formed.

Further, the silicon region was crystallized by laser annealing. A KrF excimer laser (wavelength 248 nm) as the laser, the energy density of the laser, 200~500mJ / cm ^2, for example, a 350 mJ / cm ^2, 2 to 10 shots per location, for example 2 shots irradiated. At the time of laser irradiation, the substrate was heated to 100 to 450 ° C, for example 350 ° C.

Further, tetra ethoxy silane (Si
Using (OC ₂ H ₅ ) ₄ , TEOS) and oxygen as raw materials, a 1000 Å-thick silicon oxide 34 was formed as a gate insulating film of a crystalline silicon TFT by a plasma CVD method. As the raw material, trichlorethylene (C ₂ HCl ₃ ) was used in addition to the above gas. Oxygen 400SCCM flow into the chamber before film formation, substrate temperature 300 ° C, total pressure 5P
a, plasma was generated with an RF power of 150 W, and this state was maintained for 10 minutes. After that, 300S oxygen is added to the chamber.
A silicon oxide film was formed by introducing 15 SCCM of CCM and TEOS and 2 SCCM of trichloroethylene. The substrate temperature, RF power, and total pressure are each 300
C., 75 W, 5 Pa. After the film formation was completed, 100 Torr of hydrogen was introduced into the chamber, and hydrogen annealing was performed at 350 ° C. for 35 minutes.

Subsequently, by the sputtering method,
An aluminum film containing 0.5 to 3%, for example, 2% of silicon was deposited to a thickness of 1000 to 10000Å, for example 5000Å. Then, the aluminum film was etched to form gate electrodes 35p (for P-channel TFT) and 35n (for N-channel TFT).

Then, the substrate was immersed in a solution of tartaric acid in ethylene glycol (1 to 5%, neutralized with ammonia), a positive voltage was applied to the gate electrode to pass an electric current, and an anode was formed on the surface of the gate electrode. Oxide (aluminum oxide) layers 36p and 36n were grown. The potential of the gate electrode is initially 2 to 5 V / min, for example 4 V / min to 200 to 3 V / min.
The voltage was raised to 00 V, for example 250 V, and kept constant for 2 hours. The thickness of the anodic oxide obtained was determined by the magnitude of the applied voltage. Thickness of anodic oxide is 1
000-5000Å, especially 2000-3000Å was preferred. Here, it is set to 2500Å. (Figure 5 (A))

Then, by the plasma doping method,
Impurities (phosphorus) were implanted into the silicon regions 33n and 33p using the gate electrode and the surrounding anodic oxide as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount was set to 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, the N-type impurity region 37 was formed. (Fig. 5 (B))

Next, a mask 38 is formed by photoresist.
Was formed to expose only the semiconductor region 33p of the P-channel TFT. Then, by the plasma doping method,
Impurities (boron) are implanted into the silicon region 33p of the P-channel TFT by using the mask 38, the gate electrode 35p and the surrounding anodic oxide 36p as a mask. Diborane (B ₂ H ₆ ) was used as the doping gas, and the acceleration voltage was 4
It was set to 0 to 80 kV, for example, 65 kV. 1x dose
10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁵ cm ^−2, which is larger than that of the previously doped phosphorus. As a result,
A P-type impurity region 39p is formed. On the other hand, mask 3
In the N channel region covered with
n were formed. (Fig. 5 (C))

Then, again, the substrate was immersed in an ethylene glycol solution of tartaric acid (1 to 5%, neutralized with ammonia), and a negative voltage was applied to the gate electrode to perform current curing. Then, by passing a current through the silicon film, particularly in the channel formation region (active region),
As shown in FIGS. 2A and 2B, a current cure process is performed. Thus, the recombination center at the insulating film-silicon interface in the channel forming region, particularly in the portion where pinch-off will occur in the future, could be neutralized and eliminated. The potential of the gate electrode is initially -4 V / min at -30 to -80 V, for example -6
The voltage was raised to 0 V and kept constant for 1 hour. (Figure 5 (D))

Then, laser light was irradiated to perform laser annealing. KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
And the energy density of the laser is 200 to 500
mJ / cm ^2, for example, a 250 mJ / cm ^2, 2 to 10 shots per location, for example 2 shots irradiated.
During laser irradiation, the substrate is heated to 100 to 450 ° C., for example, 2
Heated to 50 ° C. In this way, the impurities were activated. (Fig. 5 (E))

Subsequently, a silicon oxide film 40 having a thickness of 6000Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
41a, 41 of electrodes and wirings in the source region and the drain region of
b, 41c and 41d were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The thin film transistor was completed through the above steps. (Fig. 5
(F))

[Embodiment 3] FIG. 6 shows a cross-sectional view of a manufacturing process of this embodiment. A base film 52 of silicon oxide having a thickness of 2000 Å was formed on a substrate (Corning 7059) 51 by a sputtering method. Further, an intrinsic (I-type) amorphous silicon film having a thickness of 500 to 1500 Å, for example 1500 Å, was deposited by the plasma CVD method, and a silicon oxide film having a thickness of 200 Å was further deposited thereon by the sputtering method. Then, this amorphous silicon film was annealed in a nitrogen atmosphere at 600 ° C. for 48 hours to be crystallized.

After the crystallization process, the silicon film is patterned to form island-shaped silicon regions 53p (for P-channel TFT).
53n (for N-channel TFT) is formed, and
A 1000 Å thick silicon oxide film 54 was deposited as a gate insulating film by a sputtering method. For sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is 200 to 400 ° C., for example 250 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example 0.1 or less. did.

Subsequently, by the sputtering method,
An aluminum film containing 0.5 to 3%, for example, 2% of silicon was deposited to a thickness of 1000 to 10000Å, for example 5000Å. Then, the aluminum film was etched to form gate electrodes 55p (for P-channel TFT) and 55n (for N-channel TFT).

Then, the substrate was immersed in a solution of tartaric acid in ethylene glycol (1 to 5%, neutralized with ammonia), a positive voltage was applied to the gate electrode to pass an electric current, and an anode was formed on the surface of the gate electrode. Oxide (aluminum oxide) layers 56p and 56n were grown. The potential of the gate electrode is initially 2 to 5 V / min, for example 4 V / min to 200 to 3 V / min.
The voltage was raised to 00 V, for example 250 V, and kept constant for 2 hours. The thickness of the anodic oxide obtained was determined by the magnitude of the applied voltage. Thickness of anodic oxide is 1
000-5000Å, especially 2000-3000Å was preferred. Here, it is set to 2500Å. (Fig. 6 (A))

Next, a mask 57 is formed by photoresist.
Was formed to expose only the semiconductor region 53p of the P-channel TFT. Then, again, the substrate was immersed in an ethylene glycol solution of tartaric acid (1 to 5%, neutralized with ammonia), and a negative voltage was applied to the gate electrode to perform current curing. The potential of the gate electrode is initially -4
The voltage was increased from −70 to −200 V, for example −120 V at V / min, and kept constant for 1 hour. In this embodiment,
Since the regions corresponding to the source and drain of the P-channel TFT are not doped, the resistance is high. That is,
The resistance R ₄ in FIG. 1 is large, and the voltage effect in that portion is large. That is, the voltage V _G applied to the gate electrode
Among them, the ratio of the voltage applied to the gate insulating film is reduced, so that compared with the cases of Examples 1 and 2 (in these cases, the source and drain regions of the P channel TFT are doped) Then, it was necessary to apply a high voltage (FIG. 6 (B)).

Then, by the plasma doping method,
Impurities (boron) are implanted into the silicon region 53p of the P-channel TFT using the mask 57, the gate electrode 55p and the surrounding anodic oxide 56p as a mask. Diborane (B ₂ H ₆ ) was used as the doping gas, and the acceleration voltage was 4
It was set to 0 to 80 kV, for example, 65 kV. 1x dose
10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 5 × 10 ¹⁵ cm ^-2
And As a result, a P-type impurity region 58p is formed. (Fig. 6 (C))

Next, the mask 57 is removed, and impurities (phosphorus) are implanted into the silicon regions 53n and 53p by plasma doping using the gate electrode and the surrounding anodic oxide as a mask. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. Dose amount is 1 × 10 ¹⁵ to 8 × 10
¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ c, which is less than the previous boron
m ^-2 . As a result, an N-type impurity region 58n was formed. On the other hand, a P-channel TFT in which boron is implanted first
In the region, the concentration of boron was higher than the concentration of phosphorus, so that it remained P-type. (Figure 6 (D))

After that, laser annealing was performed by irradiating laser light. KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
Was used. The energy density of the laser is 200-50
The irradiation was performed at 0 mJ / cm ² , for example, 250 mJ / cm ^2, and the irradiation was performed for 2 to 10 shots, for example, 2 shots at one location. At the time of laser irradiation, the substrate was heated to 100 to 450 ° C, for example 250 ° C. In this way, the impurities were activated. (Fig. 6 (E))

Then, a silicon oxide film 59 having a thickness of 6000Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
Source / drain region electrodes / wirings 60a, 60
b, 60c and 60d were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. The thin film transistor was completed through the above steps. (Fig. 6
(F))

[0051]

According to the present invention, it has become possible to mass-produce current cure for a large number of TFTs. Of the possible process combinations pointed out herein, only (A), (B) and (D) are shown in the examples, but it will be clear that (C) can be implemented as well. . As described above, the characteristics of the TFT are improved by the current curing, but it is the CTF.
The economic impact of being industrially applicable to the substrate of the T circuit is great. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows a conceptual diagram of the present invention.

FIG. 2 is a band diagram showing a state of current cure.

3A to 3D are cross-sectional views of the manufacturing process of the first embodiment.

FIG. 4 shows an example of a device for performing current curing.

5A to 5C show sectional views of a manufacturing process of the second embodiment.

6A to 6C are sectional views showing a manufacturing process of the third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Base insulating film 3a, 3b, 3c ... Island silicon region 4 ... Gate insulating film 5 ... Gate electrode 6 ... Insulating film (anodic oxide)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroki Adachi, 398 Hase, Atsugi City, Kanagawa Prefecture, Semi Conductor Energy Laboratory Co., Ltd. (72) Inventor, Yasuhiko Takemura, 398, Hase, Atsugi City, Kanagawa Prefecture, Semiconductor Energy Laboratory Co., Ltd.

Claims (6)

[Claims] 1. Forming at least one first island-shaped non-single-crystal semiconductor region for N-channel thin film transistors and at least one second island-shaped non-single-crystal semiconductor region for P-channel thin film transistors on a substrate. 1), an insulating film covering both the non-single-crystal semiconductor regions, and a gate electrode formed on the insulating film by a material capable of anodizing across the first and second semiconductor regions, respectively. A second step of forming the substrate, a third step of immersing the substrate in an electrolytic solution, and applying an electric current using the gate electrode as a positive electrode to form an anodic oxide on the surface of the gate electrode; A fourth step of doping the semiconductor region with an impurity exhibiting N-type conductivity, and a fifth step of forming a mask of an insulating material on the entire surface of the first semiconductor region, A method for manufacturing a thin film transistor and having a sixth step of immersing the plate in an electrolytic solution, a negative voltage is applied to the gate electrode. 2. The method according to claim 1, further comprising a step of doping an impurity having a P-type conductivity type into the second region after the fifth step and before the sixth step. Method for manufacturing thin film transistor. 3. The method for manufacturing a thin film transistor according to claim 1, further comprising a step of doping an impurity having a P-type conductivity into the second region after the sixth step. 4. Forming at least one first island-shaped non-single-crystal semiconductor region for N-channel thin film transistors and at least one second island-shaped non-single-crystal semiconductor region for P-channel thin film transistors on a substrate. 1), an insulating film covering both the non-single-crystal semiconductor regions, and a gate electrode formed on the insulating film by a material capable of anodizing across the first and second semiconductor regions, respectively. A second step of forming, a third step of immersing the substrate in an electrolytic solution, and applying an electric current with the gate electrode as a positive electrode to form an anodic oxide on the surface of the gate electrode; A fourth step of forming a mask on the entire surface of the first semiconductor region with an insulating material; and a fifth step of immersing the substrate in an electrolytic solution and applying a negative voltage to the gate electrode. A method for manufacturing a thin film transistor and having a, a sixth step of doping an impurity showing N-type conductivity in the two semiconductor regions. 5. The method according to claim 1, further comprising a step of doping an impurity having a P-type conductivity type into the second region after the fourth step and before the fifth step. Method for manufacturing thin film transistor. 6. The thin film transistor according to claim 1, further comprising a step of doping an impurity having a P-type conductivity type into the second region after the fifth step and before the sixth step. Of manufacturing.