JPH06274412A - Memory controller - Google Patents

Abstract

PURPOSE:To constitute the memory controller so that the capacity can be recog nized without increasing the number of signal lines, even if the number of capac ity information increases. CONSTITUTION:This memory controller is provided with a capacity information interface control means 10 for controlling read-out of capacity information, and A capacity information holding means 12 for holding the read-out capacity information. Each memory card 2-4 is connected to a common signal line 20 for reading out each capacity information, and the capacity information interface control means 10 selects successively the memory cards 2-4, and executes read- out control of the capacity information of the respective memory cards. Each capacity information of the selected memory cards 2-4 is read out of the common signal line 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling a memory card having capacity information. The capacity (hereinafter abbreviated as capacity) of a memory card on which a plurality of memory elements are mounted is various, such as 4 MB and 16 MB. Therefore, it is necessary for the memory control device to recognize the size of the memory card mounted in the device.

The present invention provides a memory control device capable of judging various kinds of capacity information without increasing the number of lead lines for judging the capacity of a memory card.

[0003]

2. Description of the Related Art FIG. 14 shows a conventional memory card controller. In the figure, 300 is a memory card 0,
It is a substrate on which a memory element is mounted. Reference numeral 301 is a memory card 1, 302 is a memory card 2, 303 is a memory card 3. 304 is a memory card control device (for example, D
RAM controller (DRAMC)).

In the figure, ADR is an address signal, DA
TA is a data signal, strobe is a strobe signal, CL
K is a clock signal, * RST is a reset signal, PRDY
Is a power-on signal.

RPLY00, 01 is a memory card 0 (3
00) capacity information (2-bit signal). RPLY
10 and 11 are the capacity information of the memory card 1 (301) (2
Bit signal). RPLY 20 and 21 are capacity information (2-bit signal) of the memory card 2 (302). RPLY 30 and 31 are capacity information (2-bit signal) of the memory card 3 (303).

MA00 to 11 are memory addresses, * RA
S is a RAS signal, * CAS is a CAS signal, * WE is a write enable signal, * OE is an output enable signal, and MDxx is memory data.

FIG. 15 shows an example of conventional memory capacity information. The memory capacity of the memory card is RPLYn1, RPL
It is represented by a combination of each L or H of Yn0 (n = 0 to 3).

For example, RPLYn1 = L, RPLYn0
= L, 16MB, RPLYn1 = L, RPLYn
If 0 = H, 8MB, RPLYn1 = H, RPLYn
If 0 = L, it means that the memory card has a capacity of 4 MB. Further, if RPLYn1 = H and RPLYn0 = H, it means that it is not mounted.

In FIG. 14, a memory card controller (DRAMC) 304 is supplied with capacity information of each slot into which a memory card is inserted after power is turned on. Then, for example, capacity information RPLY00, 01 of slot 0
Is (L, L) (RPLY00 = L, RPLY01 = L)
If so, it is recognized that the memory card 0 in that slot has a capacity of 16 MB.

Similarly, capacity information RPLY1 of slot 1
0 and 11 are (L, H) (RPLY10 = L, RPLY1
If 1 = H), it is recognized that the capacity of the memory card 1 in that slot is 8 MB. The capacity information RPLY20, 21 of the slot 2 is (H, L) (RPLY20 = H,
If RPLY21 = L), it is recognized that the capacity of the memory card 2 in that slot is 4 MB. Further, the capacity information RPLY30, 31 of the slot 3 is (H, L).
If (RPLY30 = H, RPLY31 = L), it is recognized that the capacity of the memory card 3 in that slot is 4 MB.

If the capacity information RPLYn1, n0 is (H, H) (RPLYn1 = H, RPLYn0 = H), the memory card controller (DRAMC) 304 recognizes that the slot is not installed ( The output line of the capacitance information (the signal lines of RPLYn0 and n1) is pulled up, so H is detected if it is not mounted).

FIG. 16 shows a conventional DRAMC (memory card controller). In the figure, 304 is a DRAMC. A decoder (DEC) 310 is an RPLY
00 and 01 are input and converted into address information (maximum address M0 of memory card 0). Reference numeral 311 denotes a decoder (DEC), which inputs RPLY10 and 11 to receive address information (maximum address M of the memory card 1).
It is converted to 1). 312 is a decoder (DE
In C), the RPLYs 20 and 21 are input and converted into address information (maximum address M2 of the memory card 2). 313 is a decoder (DEC)
The PLYs 30 and 31 are input and converted into address information (maximum address M3 of the memory card 3).

Reference numeral 320 denotes an adder (ADD) for adding "0" to the address information of the decoder 310. The adder 320 calculates the maximum address of the memory card 0. Reference numeral 321 denotes an adder (ADD) which inputs the address information of the decoder 311 and the addition result of the adder 320 and adds them. The adder 321 obtains the sum of the maximum address M0 of the memory card 0 and the maximum address M1 of the memory card 1. 322 is an adder (ADD)
And the address information of the decoder 312 and the adder 32
The addition result of 1 is input and added. Adder 3
The sum of the maximum address M0 of the memory card 0, the maximum address M1 of the memory card 1 and the maximum address M2 of the memory card 2 is calculated by 22. 323 is an adder (A
DD), which is to input and add the address information of the decoder 313 and the addition result of the adder 322. By the adder 323, the maximum address M0 of the memory card 0,
The sum of the maximum address M1 of the memory card 1, the maximum address M2 of the memory card 2 and the maximum address M3 of the memory card 3 is obtained.

A comparator (CMP) 330 compares the output of the adder 320 with the address signal (ADR). Reference numeral 331 is a comparator (CMP), which outputs the output of the adder 320, the output of the adder 321, and the address signal (A
DR) as input, ADR and output of adder 320 and A
The output of the adder 321 is compared with DR. 33
Reference numeral 2 denotes a comparator (CMP) which inputs the output of the adder 321 and the output of the adder 322 and the address signal (ADR) and compares the output of the adder 321 with ADR and the output of the adder 322 with ADR. It is a thing. Reference numeral 333 is a comparator (CMP), which is the output of the adder 322 and the adder 32.
3 and the address signal (ADR) are input, and the adder 3
22 output and ADR and adder 323 output and ADR
To compare.

Reference numeral 334 denotes a RAS control unit, which outputs a RAS signal (* RAS0 to the memory card 0, the memory card 1, the memory card 2 and the memory card 3 according to the comparison result of each comparator (330, 331, 332, 333). , * RA
S1, * RAS2, * RAS3) are output. * RAS0 is the RAS signal for memory card 0,
* RAS1 is the RAS signal for memory card 1, * R
AS2 is a RAS signal for the memory card 2, * RAS
Reference numeral 3 is a RAS signal for the memory card 3.

Reference numeral 335 is a comparator, which is an address signal A
This is to compare the DR and the addition result of the adder 323.
Reference numeral 336 is a response control unit, and the comparison result of the comparator 335 and the addition result (M0 + M1 + M) of the adder 323 are ADR.
If it is smaller than 2 + M3), a response is returned.

The operation of the configuration shown in FIG. 16 will be described. In the configuration of FIG. 16, M0 is input to the input B of the comparator 330. M0 is input to the input C of the comparator 331, and M0 + M1 is input to the input B. Input C of comparator 332
Is input to M0 + M1 and input B is M0 + M1 + M
2 is input. The input C of the comparator 333 has M0 + M1
+ M2 is input, and input B is M0 + M1 + M2 + M3
Is entered.

As a result, if ADR is smaller than M0 (A <B), the comparator 330 notifies the RAS control unit 334 to output * RAS0 to the memory card 0 (slot 0). Upon receiving the notification from the comparator 330, the RAS control unit 334 sets the memory card 0 (slot 0).
Is output as * RAS0.

Further, ADR is larger than M0 and M0 + M1
If smaller (C ≦ A <B), the comparator 331 outputs R
The AS control unit 334 is notified that * RAS1 is output to the memory card 1 (slot 1). Upon receiving the notification, the RAS control unit 334 outputs * RAS1 to the memory card 1 (slot 1).

Similarly, ADR is larger than M0 + M1 and M
If it is smaller than 0 + M1 + M2 (C ≦ A <B), the comparator 332 informs the RAS control unit 334 of the memory card 2
Notify that (RAS2) will output * RAS2. As a result, the RAS control unit 334 outputs * RAS2 to the memory card 2 (slot 2). AD
R is greater than M0 + M1 + M2 and M0 + M1 + M2 + M
If it is smaller than 3 (C ≦ A <B), the comparator 333 outputs RA
The S control unit 334 is notified that * RAS3 is output to the memory card 3 (slot 3). As a result, the RAS control unit 334 outputs * RAS3 to the memory card 3 (slot 3).

Further, the comparator 335 compares the addition result (M0 + M1 + M2 + M3) of the adder 323 with ADR,
When ADR is smaller than the addition result (M0 + M1 + M2 + M3) (A <B), the response is notified to the response control unit 336.
The response control unit 336 returns a response.

[0022]

In the conventional memory control device, as the type of capacity of the memory card increases, the number of bits of capacity information increases, and the number of signal lines for that purpose also increases.

It is an object of the present invention to provide a memory controller capable of recognizing the capacity without increasing the number of signal lines even if the number of capacity information of the memory card increases.

[0024]

According to the present invention, the capacity information of each memory card is read out through a common signal line, and the number of lead lines for reading does not increase even if the number of types of capacity information increases. I did it. Then, the read-out control of the capacity information is made to be sequentially read out from each memory card by a control signal for selecting the memory card.

FIG. 1 shows a basic configuration (1) of the present invention. In the figure, 1 is a memory card controller, 2 is a memory card 0, 3 is a memory card 1, 4 is a memory card m.

In the memory card control device 1, 10 is a capacity information interface control means, which operates the memory card 0 (2), the memory card 1 (3) and the memory card m (4) according to a power-on signal (PRDY). Capacity information read signal (*) that sequentially selects and reads each capacity information
(RPLYSL0 to m) is output to each memory card to control the reading of the capacity information of the memory card 0 (2), the memory card 1 (3), and the memory card m (4). Then, the capacity information of the memory cards is held in the capacity information holding units (13, 14, 15) of the respective memory cards.

Reference numeral 12 is a capacity information holding means for holding capacity information of each memory card. Reference numeral 13 is a capacity information holding unit of the memory card 0 (2). Reference numeral 14 is a capacity information holding unit of the memory card 1 (3). Reference numeral 15 is a capacity information holding unit of the memory card m (4). Reference numeral 16 is an address information conversion means for obtaining the maximum address of each memory card based on the capacity information of each memory card. Reference numeral 17 is an address comparison means for comparing the input address with the maximum address based on each memory card. Reference numeral 18 denotes a control signal generating means for generating a control signal (* RAS signal or the like) to the memory card selected by the comparison result of the address comparing means.

Reference numeral 20 denotes a common signal line for holding the capacity information read from each memory card (2, 3, 4) in the corresponding capacity information holding section (13, 14, 15). Is.

The operation of the configuration of FIG. 1 will be described later. FIG. 2 shows the basic configuration (2) of the present invention. In the figure, the common signal line (20) is controlled by both sides as the address line (20 '). Then, the capacity information is divided into high-order bits and low-order bits, and the high-order bits are read by the signal lines (25,25 ', 25 ") provided individually in each memory card, and the low-order bits are read by the low-order bit read control signal. According to the address line (2
0 ') shows the basic configuration to output.

The numbers indicating the respective components in FIG. 2 are common to those in FIG. The operation of the configuration of FIG. 2 will be described later.

[0031]

The operation of the basic configuration (1) of the present invention shown in FIG. 1 will be described. When the power-on signal (PRDY) is generated, the capacity information interface control means 10 causes the capacity information read signals * RPLYSL0 to * RPLY for each memory card.
SLm (* RPLYSL0 is the capacity information read signal for the memory card 0 (2), * RPLYSL1 is the capacity information read signal for the memory card 1 (3), * RPLY
SLm generates a capacity information read signal) for the memory card m (4).

The capacity information interface control means 10 is
First, a capacity information read signal (* RPLYSL0) for the memory card 0 (2) is generated, and the memory card 0 (2)
Send to. Memory card 0 (2) has capacity information (RPLY
0 to RPLYn and RPLYn are H or L of capacity information
1-bit information) is output. Then, the capacity information interface control means 10 transfers the capacity information (RPLY0 to RPLYn) read from the memory card 0 (2) via the common signal line 20 to the capacity information holding unit 13 of the memory card 0.
To hold.

Similarly, the capacity information interface control unit 1
0 generates a capacity information read signal (* RPLYSL1) for the memory card 1 (3), and the memory card 1 (3)
Send to. The memory card 1 (3) has capacity information (RPLY
0 to RPLYn) are output to the common signal line 20. Then, the capacity information interface control means 10 holds the capacity information (RPLY0 to RPLYn) of the memory card 1 (3) in the capacity information holding unit 14 of the memory card 1.

Further, the capacity information interface control means 10 generates a capacity information read signal (* RPLYSLm) to the memory card m (4), and the memory card m (4).
Send to (4). Memory card m (4) has capacity information (RP
LY0 to RPLYn) are output to the common signal line 20.
Then, the capacity information interface control means 10 holds the capacity information (RPLY0 to RPLYn) of the memory card m (4) in the capacity information holding unit 15 of the memory card m.

The address information conversion means 16 obtains the maximum address based on the capacity information of each memory card (2, 3, 4). Then, the address comparison means 17 compares the input address and obtains the memory card to be accessed. Then, the control signal generating means 18 controls the control signal (* RAS) for accessing the selected memory card.
(Memory control signal such as signal) is output.

According to the present invention, since the capacity information of each memory card is read out to the common signal line and held in the capacity information holding means, the capacity information is read out even if the types of capacity information increase. Without increasing the lead line of
The capacity information can be read.

The operation of the basic configuration (2) in FIG. 2 will be described. In the figure, among the capacity information held in the memory cards (2,3,4), the upper bits (RPLYn0, n1) are read from the memory card and the signal lines (25, 25 ', 25 ") to the address information conversion means 16. Upper bit (RPLY)
0 to n) are controlled by the capacity information interface control means 10 and are held in the capacity information holding means 12 via the address line 20 '. That is, the capacity information (RPLY0 to n) of the memory card 0 (2) is stored in the capacity information holding unit 13 of the memory card 0, and the capacity information (RPLY0 to n) of the memory card 1 (3) is stored in the memory card 1. The capacity information (RP) of the memory card m (4) held by the information holding unit 14
LY0 to n) are held in the capacity information holding unit 15 of the memory card m. Then, each capacity information holding unit (1
The lower bits of the capacity information held in 3, 14, 15) are input to the address information conversion means 16. The address information conversion means 16 obtains the maximum address of each memory card from the upper bit and the lower bit of the capacity information of each memory card.

[0038]

EXAMPLE FIG. 3 shows an example (1) of the present invention. In the figure, 1 is a DRAMC (memory card controller).
2 is a memory card 0, 3 is a memory card 1, 4 is a memory card 2, 5 is a memory card 3. 20 is a common signal line.

In the figure, RPLY0 to RPLYn are capacity information (described later). * RPLYSL0 is a capacity information read signal for the memory card 0 (2). *
RPLYSL1 is a capacity information read signal for the memory card 1 (3). * RPLYSL2 is a capacity information read signal for the memory card 2 (4). * RPL
YSL3 is a capacity information read signal for the memory card 3 (5). The other signals are the same as those in the conventional technique, and the description thereof will be omitted.

The operation of the configuration of FIG. 3 will be described later. FIG. 4 shows an example of memory capacity information according to the embodiment (1) of the present invention. The figure shows a case where the capacity information is composed of 4 bits.

In the figure, RPLY0 = L, RPLY1
= L, RPLY2 = L, RPLY3 = L indicates that the capacity is 64 MB. RPLY0 = H, RPLY
If 1 = H, RPLY2 = L, and RPLY3 = H, it means that the capacity is 16 MB. RPLY0 = H, RPL
If Y1 = L, RPLY2 = H, and RPLY3 = H, it means that the capacity is 8 MB. RPLY0 = L, RPL
If Y1 = H, RPLY2 = H, and RPLY3 = H, it means that the capacity is 4 MB. RPLY0 = H, RPL
If Y1 = H, RPLY2 = H, and RPLY3 = H, it means that the memory card is not mounted.

The operation of the configuration shown in FIG. 3 will be described. DRAMC
(1) outputs the capacity information read signal (* RPLYSL0) to the memory card 0 (2), and the memory card 0 (2)
Of the capacity information (RPLY0 to RPLYn) is read out to the common signal line 20. Then, it is held in the capacity information holding unit (not shown, see FIG. 1) of the memory card 0 (2).

Next, the DRAMC (1) is the memory card 1
Capacity information read signal for (3) (* RPLYSL
1) is output and the capacity information (RPL) of the memory card 1 (3) is output.
Y0 to RPLYn) are read out to the common signal line 20. Then, it is held in the capacity information holding unit (not shown, see FIG. 1) of the memory card 1 (3).

Further, the DRAMC (1) is the memory card 2
Capacity information read signal for (4) (* RPLYSL
2) is output and the capacity information (RPL) of the memory card 2 (4) is output.
Y0 to RPLYn) are read out to the common signal line 20. Then, it is held in the capacity information holding unit (not shown, see FIG. 1) of the memory card 2 (4).

Further, the DRAMC (1) is a memory card 3
Memory information read signal for (5) (* RPLYSL
3) is output, and the capacity information (RPL) of the memory card 3 (5) is output.
Y0 to RPLYn) are read. The memory card 3 (5) is held in a capacity information holding unit (not shown, see FIG. 1).

FIG. 5 is a diagram showing the DRAMC of the embodiment (1) of the present invention. In the figure, 1 is a DRAMC (memory card controller). Reference numeral 40 denotes a capacity information holding unit of the memory card 0, which is a register (REG0). 41
Is a capacity information holding unit of the memory card 1, and is a register (REG1). Reference numeral 42 denotes a capacity information holding unit of the memory card 2, which is a register (REG2). Reference numeral 43 denotes a capacity information holding unit of the memory card 3, which is a register (REG3).

A decoder (DEC) 50 converts the capacity information held in the register (REG0) 40 into the maximum address (M0) of the memory card 0.
A decoder (DEC) 51 includes a register (REG)
1) The capacity information held in 41 is converted into the maximum address (M1) of the memory card 1. Reference numeral 52 is a decoder (DEC), which uses the capacity information held in the register (REG2) 42 as the maximum address (M
It is converted to 2). 53 is a decoder (DEC)
In addition, the capacity information held in the register (REG3) 43 is converted into the maximum address (M3) of the memory card 3.

An adder (ADD) 60 adds "0" to the maximum address (M0) converted by the decoder 50. The adder 60 calculates the maximum address (M0) of the memory card 0.

Reference numeral 61 is an adder (ADD), which is the maximum address (M
1) and the addition result of the adder 60 are input and added. The adder 61 obtains the sum of the maximum address M0 of the memory card 0 and the maximum address M1 of the memory card 1.

Reference numeral 62 denotes an adder (ADD) which inputs and adds the maximum address (M2) converted by the decoder 52 and the addition result of the adder 61. The adder 62 obtains the sum of the maximum address M0 of the memory card 0, the maximum address M1 of the memory card 1 and the maximum address M2 of the memory card 2.

Reference numeral 63 is an adder (ADD) for inputting and adding the maximum address M3 converted by the decoder 53 and the addition result of the adder 62. The maximum address M0 of the memory card 0, the maximum address M1 of the memory card 1, the maximum address M2 of the memory card 2 are added by the adder 63.
And the sum of the maximum addresses M3 of the memory card 3 is obtained.

A comparator (CMP) 70 compares the output of the adder 60 with the address signal (ADR). Reference numeral 71 denotes a comparator (CMP) which inputs the output of the adder 60, the output of the adder 61 and the address signal (ADR), and compares the output of ADR and the adder 60 and the output of ADR and the adder 61. It is a thing.

Reference numeral 72 denotes a comparator (CMP), which outputs the output of the adder 61, the output of the adder 62 and the address signal (AD).
R) is input and the output of the adder 61 is compared with ADR and the output of the adder 72 is compared with ADR.

Reference numeral 73 is a comparator (CMP), which outputs the output of the adder 62, the output of the adder 63, and the address signal (AD).
R) is input and the output of the adder 62 is compared with ADR and the output of the adder 63 is compared with ADR.

Reference numeral 74 is a comparator, which is an address signal AD.
R is to compare the addition result of the adder 63. 81
Is a response control unit, the comparison result of the comparator 74, ADR
Is smaller than the addition result (M0 + M1 + M2 + M3) of the adder 63, a response is returned. 80 is RAS
Control unit, each comparator (70, 71, 72, 73)
According to the result of the comparison, the RAS signal (*
RAS0, * RAS1, * RAS2, * RAS3) are output. * RAS0 is the RAS signal for memory card 0, * RAS1 is the R signal for memory card 1
AS signal, * RAS2 is RAS for memory card 2
The signal * RAS3 is a RAS signal for the memory card 3.

FIG. 6 shows a time chart 1 of the DRAMC of the embodiment (1) of FIG. FIG. 7 shows the DR of the embodiment (1) of FIG.
The time chart 2 of AMC is shown. Each signal is the same as described above.

In FIG. 6, the power is turned on at time t0 and a power-on signal (PRDY) is generated. When the capacity information interface control unit 45 inputs PRDY,
PRDY1 and PRDY2 are generated in synchronization with the subsequent clock. Then, PRDY23 is generated in synchronization with PRDY1 and PRDY2. Then, in response to the fall of PRDY23, * RPLYSL0 is generated at time t2. Then, at time t3, * RPLYSL
1 is generated. * RPLYSL2 is generated at time t4. * RPLYSL3 is generated at time t5.

In FIG. 7, times t2, t3, t4, t
5 is common with FIG. 6 at time t2, at time t2 *
When RPLYSL0 is generated, at time t2 ′,
The capacity information of the memory card 0 (slot 0) is read. Then, at time t2 ″, the capacity information RPL read at the rising timing of * RPLYSL0
Y0 to n are written and held in the register (REG0).

Next, when * RPLYSL1 is generated at time t3, the capacity information of the memory card 1 (slot 1) is read at time t3 '. And time t
3 ″, the read capacity information RPLY0 to n is written and held in the register (REG1) at the rising timing of * RPLYSL1.

Further, when * RPLYSL2 is generated at time t4, the capacity information of the memory card 2 (slot 2) is read at time t4 '. And time t
4 ″, the capacitance information RPLY0 to n read at the rising timing of * RPLYSL2 is written and held in the register (REG2).

Similarly, when * RPLYSL3 is generated at time t5, the capacity information of the memory card 3 (slot 3) is read at time t5 '. And time t
5 ", the capacity information RPLY0 to n read at the rising timing of * RPLYSL3 is written and held in the register (REG3).

In the configuration of FIG. 5, each adder 60, 6
1, 62, 63, 64, comparators 70, 71, 72, 7
3, the operations of the RAS control unit 80 and the response control unit 81 are the same as those of the conventional one, and the description thereof will be omitted.

FIG. 8 shows an embodiment (2) of the present invention. In the present embodiment, the upper 2 bits of the capacity information are read by a connecting line connecting each memory card and DRAMC (memory card control device) as in the conventional manner, and the lower bits are stored by a capacity information read control signal. The card was selected and the capacity information was read using the address line.

In the figure, the capacity information is composed of 5 bits, of which the upper 2 bits (RPLY00, 01; RPLY10,
11; RPLY20, 21; RPLY30, 31) are read by a conventional method, and the lower 3 bits (RPLY0 to
RPLYn) indicates a configuration in which the address lines (addresses MA00 to 11) are bidirectionally controlled by a read control signal and read.

In the figure, 100 is a memory card 0 having a capacity of 64 MB, for example. 101
Is a memory card 1 having a capacity of 32 MB, for example. A memory card 2 has a capacity of 8 MB, for example. The memory card 3 has a capacity of, for example, 4 MB.
Reference numeral 105 is an address line.

The meaning of each signal in the figure is the same as that described above. The operation of the configuration of FIG. 8 will be described later. Figure 9
It is an example of the memory capacity information of the embodiment (2).

The figure shows a case where the capacity information is represented by 5 bits. Upper 2 bits RPLYm1, RPLYm0 (m = 0
~ 3) and lower 3 bits (RPLY2, RPLY1, RP
The capacity was represented by LY0).

As shown in the figure, RPLYm1 and RPLYm0
RPLYm1 = L, RPLYm0 = L
Is 16 MB, RPLYm1 = L, and RPLYm0 = H is 8 MB, RPLYm1 = H, and RPLYm0 = L is 4 MB. Also, the upper 2 bits RPLYm1 = H,
RPLYm0 = H is reserved, 64MB, 32MB,
It shall be either unimplemented, and each identification shall be represented by the lower 3 bits.

That is, the lower 3 bits RPLY2 = L, RP
If LY1 = L and RPLY0 = L, reserve, RPL
6 if Y2 = H, RPLY1 = L, RPLY0 = H
4MB, RPLY2 = H, RPLY1 = H, RPLY0
= L, 32MB, RPLY2 = H, RPLY1 =
If H and RPLY0 = H, it is not mounted.

The operation of the configuration of the embodiment (2) of the present invention of FIG. 8 will be described (capacity information is according to FIG. 9). For example, memory card 0 (100) is 64 MB, memory card 1 (10
1) is 32MB, memory card 2 (102) is 8MB,
It is assumed that the memory card 3 (103) has 4 MB.

From memory card 0 (100) to RPLY
00 = H and RPLY01 = H are read, and the DRAMC
Is input to a decoder (not shown, see FIG. 10). From memory card 1 (101), RPLY10 = H, RP
LY11 = H is read and input to the decoder (not shown, see FIG. 10) of the DRAMC.

From the memory card 2 (102), select RPLY
20 = H, RPLY21 = L are read out, and DRAMC
Is input to a decoder (not shown, see FIG. 10). From memory card 3 (103), RPLY30 = L, RP
LY31 = H is read and input to the decoder (not shown, see FIG. 10) of the DRAMC.

After the power is turned on, * RAS signal, * WE
Signal, * OE signal is set to L, and * CAS signal is set to H (at this time, the memory card does not perform writing and reading operations). This signal is used as a read control signal for the lower bits of each memory card.

Then, the * WE signal and the * OE signal are set to L and *, respectively.
With the CAS signal set to H, * RAS00 (* RAS signal for the memory card 0 (100)) is set to L and the capacity information (RPLY) of the memory card 0 (100) is set.
2 = H, RPLY1 = L, RPLY0 = H) is read and held in the lower bit of the capacity register (not shown, see FIG. 10) of the memory card 0 (100) of the DRAMC 104 via the address line 105.

Next, the * WE signal and the * OE signal are set to L and * C, respectively.
When the AS signal is H, * RAS10 (* RAS signal for the memory card 1 (101)) is L, and the capacity information (RPLY2) of the memory card 1 (101) is set.
= H, RPLY1 = H, RPLY0 = L),
Through the address line 105, a capacity register (not shown in FIG. 10) of the memory card 1 (101) of the DRAMC 104.
(See the lower bit).

Similarly, the capacity information read control signal is output to the memory card 2 (102) and the memory card 3 (103), respectively.
Since the memory card 3 (103) does not have memory information in the lower bits, no data will be read out.

The lower bit read control may be such that the lower bit read control is not performed if there is an L signal based on the result of reading the upper bit (the lower bit has all the upper bits H). Only if).
That is, the memory card (slot) whose upper bits are all H
May be recognized and the read control signal of the lower bit may be output only to that slot.

FIG. 10 shows a DRAM according to the embodiment (2) of the present invention.
C is shown. In the figure, 104 is a DRAMC. 1
Reference numeral 05 denotes an address line, which transmits an address signal to the memory card, reads the lower bit of the capacity information from the memory card, and stores the capacity information holding unit (register) (1
40, 141, 142, 143).

140 (REG0), 141 (REG
1), 142 (REG2) and 143 (REG3) are capacity information holding units, each of which is composed of a register and holds the lower bits of the capacity information of the memory card 0, the memory card 1, the memory card 2 and the memory card 3. To do.

Reference numeral 145 is a capacity information interface control unit. 150 (DEC), 151 (DEC), 152
Decoders (DEC) and 153 (DEC) are capacity information holding units 140, 141, 142 and 143, respectively.
It converts the capacity information stored in the maximum address. Each of the decoders stores the upper 2 bits of the memory information of the corresponding memory card and the capacity information holding unit (1
40, 141, 142, 143) are input and converted into the maximum address of each memory card.

160 (ADD), 161 (ADD), 1
Reference numerals 62 (ADD) and 163 (ADD) are adders. 1
70 (CMP), 171 (CMP), 172 (CM
P), 173 (CMP) and 174 (CMP) are comparators.

Reference numeral 180 denotes a RAS control unit, which is a control signal (* RAS0, * RAS1, * R for the memory card.
AS2, * RAS3, * CAS, * WE, * OE). Reference numeral 181 is a response control unit. 190
Is a multiplexer (MPX) and has a low address,
The column address is selected. Reference numeral 191 is an address buffer.

The adder (ADD) (16
0, 161, 162, 163), comparators (170, 17)
1, 172, 173, 174), and the operation of the response control unit 181 is similar to that of FIG.

In the configuration shown in the figure, the address signal (AD
R) is input to each memory as usual through the address line 105. Capacity information interface control unit 145
Detects the power-on signal PRDY, instructs the RAS control unit 180 to send the * RAS signals (* RAS0, * RA
S1, * RAS2, * RAS3) L, * WE L, *
L of OE and H of * CAS are generated. And * RA
S signal (* RAS0, * RAS1, * RAS2, * RA
When L of S3), L of * WE, L of * OE, and H of * CAS are input to the memory card selected by the RAS signal, the selected memory card outputs the lower bit of the capacity information. Then, the capacity information is transferred to the capacity information holding units 140, 141, 142, 14 via the address line 105.
3 is input to the register and the capacity information holding unit (140, 14) selected by the capacity information interface control unit 145.
1, 142, 143) and held.

The upper bits of the capacity information are the same as before.
From each memory card to each decoder (150, 151, 1
52, 153). FIG. 11 shows an embodiment of the present invention
The configuration of the memory card of (2) is shown.

In the figure, 189 is a memory card, and 19
Reference numeral 0 is a capacity information holding unit, which holds capacity information. 191 is an AND circuit, * RASm0,
It is the logical product of * WE and * OE. Reference numeral 192 denotes an AND circuit, which takes the logical product of the output of the capacity information holding unit 190 and the output of the AND circuit 191. 193
Is a buffer whose output is controlled by gate-inputting the output of the buffer 194. 195 is a memory bank 0, 196 is a memory bank 1, 197 is a memory bank 2, and 198 is a memory bank 3.

In the configuration shown in the figure, H is output only when the inputs of the AND circuit 191 are * RAS = L, * WE = L, * OE = L. AND circuit 19 to AND circuit 192
When H of 1 is input, the capacity information of the capacity information holding unit 190 is read.

FIG. 12 shows the DRAMC of the embodiment (2) of the present invention.
13 is a time chart 1 of the present invention, and FIG.
It is a time chart 2 of RAMC. In FIG.
The power is turned on at time t0, and the power-on signal (PRDY)
Is generated. When the capacity information interface control unit 145 receives PRDY, it synchronizes with the subsequent clock and outputs P
RDY1 and PRDY2 are generated. And PRDY
1 and PRDY2 generate PRDY23. Then, at time t1 when PRDY falls to L, * OE, * WE,
* RAS00 becomes L. At this time, * CAS is H,
Make sure that the memory card does not perform operations such as writing to or reading from the memory. Then, at time t1 ", * OE,
* WE and * RAS00 are set to H.

At time t2, * OE, * WE, * RAS10
Becomes L. At this time, * CAS is set to H. And
At time t2 ″, * OE, * WE, and * RAS10 are set to H. At time t3, * OE, * WE, and * RAS20 are set to L. At this time, * CAS is set to H. And time t
At 3 ", * OE, * WE, and * RAS20 are set to H.

At time t4, * OE, * WE, * RAS30
Becomes L. At this time, * CAS is set to H. And
At time t4 ", * OE, * WE, and * RAS30 are set to H. In FIG. 13, time t1, t1", time t2, t.
2 ", time t3, t3", and time t4, t4 "are common to FIG.

At time t1, * OE, * WE, * RAS0
When 0 becomes L, the capacity information of the memory card 0 is read at time t1 ′, and RPLY0 to RPLYn are set to the address line 1
05 to the register (REG0). Then, RPLY0 to RPLYn are written in the register (REG0) at the timing when * RAS00 becomes H at time t1 ″.

At time t2, * OE, * WE, * RAS1
When 0 becomes L, the capacity information of the memory card 1 is read at time t2 ′, and RPLY0 to RPLYn are set to the address line 1
05 to the register (REG1). Then, RPLY0 to RPLYn are written in the register (REG1) at the timing when * RAS10 becomes H at time t2 ″. At time t3, * OE, * WE, * RAS20.
Becomes L, the capacity information of the memory card 2 is read at time t3 ′, and RPLY0 to RPLYn become the address line 10
5 to the register (REG2). Then, RPLY0 to RPLYn are written in the register (REG2) at the timing when * RAS20 becomes H at time t3 ″.

At time t4, * OE, * WE, * RAS3
When 0 becomes L, the capacity information of the memory card 3 is read at time t4 ′, and RPLY0 to RPLYn are set to the address line 1
05 to the register (REG3). Then, RPLY0 to RPLYn are written in the register (REG3) at the timing when * RAS30 becomes H at time t4 ".

[0094]

According to the present invention, the capacity can be recognized without increasing the number of signal lines even if the number of capacity information of the memory card increases. Therefore, various types of memory cards can be used without increasing the size of the memory control device.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration (1) of the present invention.

FIG. 2 is a diagram showing a basic configuration (2) of the present invention.

FIG. 3 is a diagram showing an embodiment (1) of the present invention.

FIG. 4 is a diagram showing memory capacity information according to the embodiment (1) of the present invention.

FIG. 5 is a diagram showing a DRAMC according to an embodiment (1) of the present invention.

FIG. 6 is a diagram showing a time chart 1 of the DRAM C according to the embodiment (1) of the present invention.

FIG. 7 is a diagram showing a time chart 2 of the DRAM C according to the embodiment (1) of the present invention.

FIG. 8 is a diagram showing an embodiment (2) of the present invention.

FIG. 9 is a diagram showing memory capacity information according to the embodiment (2) of the present invention.

FIG. 10 is a diagram showing a DRAMC according to an embodiment (2) of the present invention.

FIG. 11 is a diagram showing a configuration of a memory card according to an embodiment (2) of the present invention.

FIG. 12 is a diagram showing a time chart 1 of the DRAM C according to the embodiment (2) of the present invention.

FIG. 13 is a diagram showing a time chart 2 of the DRAM C according to the embodiment (2) of the present invention.

FIG. 14 is a diagram showing a conventional memory card control device.

FIG. 15 is a diagram showing an example of conventional memory capacity information.

FIG. 16: Conventional DRAMC (memory card control device)
FIG.

[Explanation of symbols]

 1: Memory card control device 2: Memory card 0 3: Memory card 1 4: Memory card m 10: Capacity information interface control means 12: Capacity information holding means 13: Capacity information holding unit of memory card 0 14: Memory card 1 Capacity information storage unit 15: Capacity information storage unit of memory card m 16: Address information conversion unit 17: Address comparison unit 18: Control signal generation unit

Claims (3)

[Claims] 1. A memory card (2, 3, 3) having capacity information.
In the memory card control device (1) for controlling 4), the capacity information interface control means (10) for controlling the reading of the capacity information of the memory card and the memory card (2, 3, 3)
4) capacity information holding means (12) for holding the capacity information read out, address information conversion means (16) for calculating the maximum memory address from the held capacity information, and memory card (2, 3, 4) ) And an address comparison means (17) for comparing the address information calculated by the address information conversion means (16) and a control signal for generating a control signal for accessing the memory card according to the comparison result of the address comparison means (17). And a memory means (2).
3, 4) are connected to a common signal line (20) for reading out the respective capacity information, and the capacity information interface control means (10) sequentially selects the memory cards (2, 3, 4) and respective memories. The capacity information of the selected memory card (2, 3, 4) is output to the common signal line (20) by controlling the reading of the capacity information of the card, and the capacity information holding means is provided.
A memory control device characterized by being held in (12). 2. The common signal line (20) according to claim 1, wherein the common signal line (20) is an address line, and each memory card (2, 3, 4) is provided with a signal line for reading an upper bit of each capacity information, The upper bit is read by the signal line provided individually in each memory card, the lower bit read control signal is generated immediately after power-on, and the lower bit is output to the address line according to the read control signal to hold the capacity information. A memory controller, characterized in that it is held by means (12). 3. The low-order bit read control signal according to claim 2, which is generated based on a write enable signal, an output enable signal, a RAS signal and a CAS control signal for each memory card, as a condition that a memory element of the memory card does not operate. A memory control device characterized by: