JPH06274364A - Computer system diagnostic system - Google Patents

Abstract

PURPOSE:To improve the quality of a product by efficiently testing the product and preventing test omission in the test of data transfer between input/output devices and a main storage device in testing a computer system. CONSTITUTION:The execution control parts 32 of a test program 30 operating under CPU 1 in the computer system equally and randomly gives the starting address and the data transfer quantity of a tested area 31 to be the diagnostic object of the main storage device 3 to test packages 33a to 33n testing the respective input/output devices 2a to 2n. Data transfer between the respective input/output devices and the main storage device is tested by parallely executing the test packages by the processings of each table of a ready table/busy table/ execution table controlled by an execution control part at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic method in a computer system, and more specifically, to efficiently test various input / output devices, control devices, and main storage devices connected to a computer main unit. The present invention relates to a computer system diagnostic method intended to be performed.

[0002]

2. Description of the Related Art A conventional diagnosis method in a computer system will be described with reference to FIGS. FIG. 9 is a block diagram showing the configuration of the system at the time of executing the system diagnosis of the computer system. In the figure, 1 is a central processing unit, 2a to 2n are input / output devices and control devices to be tested, and 3 is a main Storage device, 30 is a test program,
Reference numeral 31 is a tested area to be tested by the main memory. The peripheral devices (2a to 2n) to be tested are controlled by the test program 30 via the central processing unit 1. FIG. 10 is a diagram showing in detail the configuration of the main storage device 3 described in FIG. 9, in which the test program resides in the low-address area from the address 0 of the main storage device, and the subsequent area is All of the area to be tested 31 is provided. FIG. 11 shows
It is the flowchart which showed the procedure of the test method of the input / output device, the control device, and the main memory by the conventional method,
FIG. 12 illustrates an example of an access method in the area under test.

Next, the operation will be described with reference to FIGS. 11 and 12. FIG. 11 is a flowchart outlining steps of a test method in a conventional computer system. In FIG. 11, step (110) shows a preparatory procedure before starting the test. The test program is
A test area as an input / output buffer of the main memory is provided to each device under test. This method is fixed, and the areas used in the test package are assigned in a fixed manner. In step (111), the number of devices under test is set to'DEVNO '. In step (112), the device index counter (DEVCNT) is cleared. Step (113)
Then, input / output is started for each input / output device and control device for the device under test. This starts data transfer between the main storage device and the input / output device. In step (114), the generation of an input / output interrupt is waited for. That is, it waits until the input / output operation is completed. When an input / output interrupt occurs, the process proceeds to step (115) to test whether the data in the test area is correct. That is, in the case of data transfer from the input / output device to the test area of the main storage device, the test area of the main storage device is compared with the data of the input / output device, and if the data match, it is determined that the test is successful. If an error such as data compare occurs, error processing is performed. Step (1
16), the device index counter (DEV
CNT) is incremented by "1". Step (11
In 7), it is checked whether or not the test is completed for all the devices under test, and if not completed, step (113).
Then, the next device under test is similarly diagnosed. When all devices under test have been diagnosed, proceed to step (11
Proceed to 8). In step (118), the test items are counted up to perform the next test, and it is checked whether all specified tests have been executed. If all the specified tests have not been completed, step (11
Return to 1) and repeat the same test.

FIG. 12 is a diagram showing how the tested area is accessed and tested in the test result by the conventional method described with reference to FIG. 11, and the areas used by the respective tested devices are different. However, it can be seen that the fixed area is always used. For example, a test program for testing the input / output device (2a) always uses the test areas A1, A2, A3. Here, the number A1 indicates the order of input / output activation, and it can be seen that the same area is accessed no matter how many times it is executed.

[0005]

In the conventional diagnosis system,
As shown in FIG. 12, since the test area is always fixed for each input / output device, the method of data transfer between the main storage device and the input / output device is also uniform, and it may vary depending on the address of the main storage device. However, there is a problem that the data transfer test of different parts is not sufficiently performed. Further, since the test area of the allocated main storage device is always fixed, an untested free area occurs, and the test is insufficient. In addition, in the conventional diagnostic method, as shown in FIG. 11, the diagnosis for the device under test is activated in a serial manner, so that the I / O devices are not activated at the same time, and therefore the efficiency of the test is poor. In addition, there is a problem that it is not easy to ensure the quality of the product because the contents of the test considering the race condition between the main storage device and the input / output control device including the main body device are insufficient.

The present invention has been made to solve such a problem, and in the data transfer between the main storage device and the input / output device, the method of controlling the data transfer is delicately controlled by each address of the main storage device. Create different combinations,
By pointing out the defects in the elements, I / O devices, and I / O control devices in the main memory, and by creating a race condition that matches the actual operating conditions between the devices under test, it is easy to create intermittent problems. By discovering, the purpose is to improve design verification and product quality.

[0007]

SUMMARY OF THE INVENTION A diagnostic method in a computer system according to the present invention uses a main memory device in order to randomly access an area under test of the main memory device and to access the area on average. Start area to give,
Also, a means for irregularly giving the area length at the time of execution is provided. Further, the diagnostic method in the computer system according to the present invention is provided with an execution control unit and a test package, and the execution control unit performs the test
By controlling the package, I / O is started in parallel.

[0008]

The diagnosis method of the computer system according to the present invention is
In the data transfer control between the main memory and the input / output device to be tested, a combination of randomly generated and slightly different data can be created, so that the main memory area can be uniformly accessed. Further, in the data transfer between the main memory device and the input / output device, the race condition between the devices can be generated, so that the intermittent problem can be easily detected.

[0009]

【Example】

Example 1. Embodiment 1 of the invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a system when a computer system is diagnosed, in which 1 is a central processing unit, 2a to 2n are input / output devices and control units to be tested, and 3 is a main unit. Storage device, 30 is a test program, 31 is a test target area of the main storage device to be tested, 32 is an execution control unit in the test program, and 33a to 33n are test target devices 2a to 2
Various test packages for n.

FIG. 2 is a block diagram of the schematic operation in order to facilitate understanding of the entire processing contents according to the present invention. The relationship between the execution control unit 32 and each test, package 33a, 33b, 33n. Is clear. The execution control unit 32 controls the overall execution of the test package and performs common processing, and is composed of three functions: an input / output interrupt processing routine, an execution control routine, and various subroutines. Here, in the I / O interrupt processing routine, when an I / O interrupt occurs, a test package search from the interrupt device address, a device status test, etc.
Also, processing such as setting to the ready table processed by the execution control routine is performed. On the other hand, the test package prepares a test, requests to secure a test area, requests input / output activation, and checks data in the test area for a specific test of the input / output device. That is, direct and package-specific instructions are given by the test package, and the execution control unit executes the control of the entire diagnostic program according to the instructions. The execution control right of the test package is managed by the execution control unit. ing.

FIG. 3 is a flow chart showing an outline of execution of each test package. 4 is a flow chart showing in detail the test area search method for giving the test area 31 to each test package in FIG. 3, and FIG. 5 illustrates the test area search method according to the flow chart of FIG. FIG. In Figure 5,
Reference numeral 90 is a memory management table, 91 is one entry information of the memory management table, and 92 is a memory management table search pointer. FIG. 6 is a diagram showing an example of the access result of the tested area 31 by the area search method of this embodiment.

The operation of the embodiment of the first invention will be described with reference to the flow charts of FIGS. 3 and 4. The flow chart of the test package of FIG. 3 corresponds to 33a to 33n of FIG. 2, and control is transferred from step (43) of FIG. 7 described later to step (70).
In step (70), a random number or random data is generated. In step (71), the size of the test area 31 to be used, that is, the buffer size is determined from the random data. In step (72), an empty area of the area under test is searched. Specifically, the start address of the test area is determined. This test area is determined by the execution control unit, and the test package calls this function by a subroutine call. FIG. 4 illustrates the details. FIG. 4 will be described later.
In step (73), the test area and the buffer size are set and the input / output is started. In step (74),
Place the test package in the busy table and wait for an I / O interrupt. After that, the process returns to the execution control routine of the execution control unit shown in FIG. 2 to prepare for the processing of the next test package. In step (75),
I / O interrupt processing is performed, and when control is transferred to this test package again by the execution control unit, it is tested whether the data in the test area is correct. If the test is successful, proceed to step (76) to free the test area used in this test. Steps (70) to (76) are the operations of the series of test programs.

Next, regarding the search method of the test area,
4 and 5 will be described. First, when a request for determining a test area is received from the test package, the process branches to step (80), and the memory management table search pointer (92 in FIG. 5) to the memory management table 90.
Take out the contents of. In this memory management table, used flags (unused, in use), used test package names, and other information are stored. Step (81)
At, the table is tested according to the flag information whether it is unused, that is, whether the target test area is unused. If it is not used, the process proceeds to step (82), and then it is tested whether or not it is unused by the continuous buffer size. If the buffer size cannot be secured, the process proceeds to step (84).
If secured, the process proceeds to step (83) to set the use flag in the memory management table, set the test package name and various information, and give the called test package a test area. Then, the process returns to step (73) in FIG. On the other hand, in step (81) and step (82), if the table is in use, step (8
Branch to 4) and increment the memory management table search pointer 92 by "1". That is, preparations are made for the next memory management table search. Step (8
In 5), it is tested whether it becomes the last pointer.
If not, the process returns to step (80) and the same is performed thereafter. If the last pointer is reached in step (85), the flow advances to step (86) to return the memory management table search pointer 92 to "0". The area under test is returned to the initial position by setting it to "0". By thus controlling the memory management table search pointer in ascending order, the test areas are accessed on average.

As described above, the diagnosis is performed between the test area of the main memory and the input / output device. An example of the access result of the test area by each test package at this time is shown. It is FIG. In FIG. 6A, the addresses are initially allocated from the lowest address. The area A1 indicates that the test package a accessed first. Similarly, the area of B1 is 1 for the test package b.
Indicates that the second access was made. In the execution of each test package, access is A1 → B1 → C1 → D1 → N1
→ B2 → A2 → C2 → A3, and so on.
When the last area C48 is accessed, the lower address is returned again, and the following D42 → C48 → A52 are accessed. With the passage of time, it is carried out in the phases 1, 2, and 3. As a result, each area of the main storage device is used at random in the input / output device. FIG. 6B is a diagram more specifically showing used addresses and sizes. For example, the area A1 is an area of 1000 bytes from the memory address 20000, and exactly one page is used. C
Area 38 is 62 from memory address 22130
This is an 8-byte area. Before and after this, there is a vacant part, but this vacancy is also an important point. By changing the memory address in this empty portion, the processing environment condition between the input / output device and the main storage device can be changed. As you can see, the test package used, the address of the area, and the size of the area change variously over time, and in this way the area under test used by each test package is assigned at random. Accessed on average.

Example 2. A second embodiment of the present invention will be described based on FIGS. 2, 7 and 8.
FIG. 7 is a flow chart showing a detailed block diagram of the execution control unit and the input / output interrupt processing unit in the overall process outline according to the present invention shown in FIG. Figure 8
Shows how the test package is processed by the execution control unit and its state transits. 60
Shows how each test package is queued for execution and chained to the ready table.
61 indicates that each test package is waiting for an input / output interrupt and is chained to the busy table, and 62 indicates that the test package is connected to the execution table and is currently being executed. ing. Lady
Multiple test packages are chained to the table and the busy table, and after processing, they are stuffed to the left as shown in the figure and the priority is increased by one.

Next, the operation will be described. (1) Execution Control Unit First, the execution control routine of FIG. 7 will be described. In step (40), the table of the test package to be executed next is fetched from the ready table 60. A test (41) is made as to whether the information retrieved here is empty. If it is free, it means that there is no test package to be executed next, so the state becomes Wait because it is waiting for an I / O interrupt. If it is not empty, go to step (42) to perform the operation of closing the ready table 60 to the left for the next operation. In step (43), the test
Set the package in the run table 62 and start running the test package. The operation of the test package is as described in FIG. (2) Input / Output Interrupt Processing Unit Next, as a function of the execution control unit 32, there is an input / output interrupt processing routine, and its operation will be described. In step (50), when an input / output interrupt occurs, the busy table 61 is searched for a test package based on the interrupt device address. Next, in step (51), a test of input / output interrupt status and the like is performed. In step (52), the test package is set in the ready table 60. Now that the I / O interrupt process is completed, the process branches to the execution control routine, and the process for executing the next test package is performed in the same manner. The execution control routine executes each test package in parallel and processes the tests of the I / O devices in parallel.

[0017]

As described above, according to the present invention, design failure is pointed out and efficiency is improved by sequentially changing the memory area start address and the memory area size in the diagnosis of the main memory device and the peripheral device in the computer system. It is possible to provide a good diagnostic method. Also, we have made it possible to run test packages for various peripheral devices in parallel by executing any combination. This makes it easy to find out problems that occur intermittently, and makes it possible to efficiently test computer systems.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of a diagnostic system in an embodiment of the present invention.

FIG. 3 is a flowchart showing an outline of execution of each test package showing an embodiment of the present invention.

FIG. 4 is a flow chart showing in detail a test area search method for giving a test area to each test package according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a test area search method of giving a test area to each test package according to the present invention.

FIG. 6 is a diagram showing an example of an access result of an area under test according to an embodiment of the present invention.

FIG. 7 is a diagram showing an execution control routine and an input / output interrupt processing routine according to the embodiment of the present invention.

FIG. 8 is a block diagram of an execution control unit according to the embodiment of the present invention.
It is the figure which made a block and explained how the execution state of the test package transits.

FIG. 9 is a conventional system configuration diagram.

FIG. 10 is a diagram showing a configuration of a conventional main storage device.

FIG. 11 is a flowchart showing a procedure of a method of testing a peripheral device and a main memory device by a conventional test program.

FIG. 12 is a diagram showing an example of access to an area under test according to a conventional example.

[Explanation of symbols]

1 Central Processing Units 2a to 2n I / O Devices and Control Units 3 Main Storage Device 30 Test Program 31 Test Area 32 Execution Control Unit 33a to 33n Test Package for I / O Devices and Control Units 90 Memory Management Table 91 Memory Management Table Content 92 Memory management table search pointer 60a, 60b, 60c Test package execution wait table 61b, 61n Test package I / O interrupt wait table 62 Test package execution table

Claims (2)

[Claims] 1. A diagnostic system for a computer system including a peripheral device, wherein in the allocation of a memory area to a test package related to a diagnostic process, a start address of the memory area and a memory area size are related to the start of the test package. A computer system diagnostic method comprising means for arbitrarily determining when a data transfer request occurs and allocating a memory area based on the content of the determination. 2. A diagnostic system for a computer system including a peripheral device, wherein the execution control unit controls and manages the execution of individual test packages corresponding to the diagnostic contents of the peripheral device, wherein the execution control unit comprises: A computer system diagnostic method characterized in that the test packages are provided with means for controlling and managing a plurality of execution states transiting at the time of execution so that the test packages can be executed in parallel.