JPH06274123A - Interface for display - Google Patents

Abstract

PURPOSE:To generate a reference clock with which video data can stably be sampled by a circuit that need not be adjusted by an interface which converts a display signal for the CRT of a personal computer into a signal for a thin display. CONSTITUTION:The personal computer outputs the video data VID, a horizontal synchronizing signal, and a vertical synchronizing signal VS which are generated with its internal clock. This interface inputs the signal HS as a trigger to the PLL circuit composed of means 21-24, and the frequency of the signal HS is divided by N to generate a reference clock VCLKO which has the same period and is in phase with the internal clock of the personal computer. At the rear stage, the clock VCLK0 is counted up to 80 through a counter 25 to detect a back-porch period and then an image valid display period is detected similarly through a counter 29. A horizontal synchronizing signal HS1 for display which indicating only the valid display period and a reference clock VCLK1 for display which makes the reference clock VCLK0 valid only in the period of the signal HS1 are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video signal data VID as a digital RGB video signal output from a personal computer for a CRT, and horizontal and vertical synchronizing signals H.
The present invention relates to an interface for inputting S and VS and converting them into signals for display on a display such as a liquid crystal or EL panel called a so-called thin display.

In the following figures, the same reference numerals indicate the same or corresponding parts.

[0003]

2. Description of the Related Art FIG. 4 shows a configuration example of a conventional display interface of this type (the interface is also abbreviated as I / F). The role of the display I / F 11 is that the personal computer 10 receives a display signal output on the premise of CRT display for the thin display 12 to perform a display operation, converts it to a signal for the display 12, and transmits the signal. is there. The signals output from the personal computer 10 for displaying images are the following three types.

Video signal data VID: display data, horizontal synchronizing signal HS: signal for giving horizontal / sequential scanning timing, vertical synchronizing signal VS: signal for giving one field period. A particular problem here is that each pixel data in the video signal data VID output from the personal computer 10 is sampled and received in proper synchronization. That is, the video signal data VID as a digital RGB signal output from the personal computer 10 is output based on the timing of the transfer clock VCLK in the personal computer 10. However, the signals output from the personal computer 10 are the above-mentioned three types, and the transfer clock VCLK serving as a driving reference is not output.

Therefore, in order to reliably receive (sample) the video signal data VID, the interface 11 takes the following measures. That is, in the display I / F 11, the oscillator 1 of the reference clock VCLK0 for sampling having the same cycle as the transfer clock VCLK in the personal computer 10, which is driven asynchronously with the video signal data VID and the horizontal synchronizing signal HS from the personal computer, is installed. As shown in FIG. 5A, the phase of the reference clock VCLK0 is adjusted so that the rising edge of the reference clock VCLK0 falls within the sampling effective range 51 of each pixel data in the video signal data VID. Video signal data V
Each pixel data in the ID is sampled. Note that FIG. 5B shows a phase state in which the reference clock VCLK0 cannot be sampled.

As a method of adjusting the phase of the reference clock VCLK0, a fixed delay circuit 2 having several kinds of fixed delay elements is used so that the display disorder is eliminated while observing the display screen of the display 12 artificially (that is, surely). Fixed delay circuit 2 so that pixel data can be sampled
The adjustment tap of is selected. The horizontal synchronizing signal HS and the vertical synchronizing signal VS output from the personal computer 10 have portions called a back porch BP and a front porch FP before and after the respective signals HS and VS for CRT display. However, since this part is unnecessary for the thin display 12, the horizontal sync signal HS1 and the vertical sync signal V1 with this part removed in the I / F 11 are used.
S1 is created and given to the thin display 12 from the display transfer timing controllers 8 and 9, respectively. The video signal data sampled and stored in the VID processing unit 5 is synchronized with the reference clock VCLK1 of the separately provided sampling clock oscillator 7 for display, and the video signal data VID1 of the effective portion excluding the back porch BP and the front porch FP. Is given to the display 12.

[0007]

As a matter of course, the display screen of the display 12 is required to display a clear image. In response to the demand, the conventional technique has the following problems. That is, as described above, the sending personal computer 10
And the display-side I / F 11 on the receiving side are driven at their own clock timings. Video signal data VID and I /
In order to adjust the timing deviation of the sampling clock VCLK0 of F11, the reference clock VCLK0 is passed through several kinds of fixed delay elements inside the I / F11, and the display is adjusted while observing the display screen of the display 12 so as not to disturb the display. However, the timing of the video signal data VID and the reference clock VCLK0 change due to the fluctuation of the driving power supply and the change of the environment surrounding the device, and the display is disturbed.

An object of the present invention is to provide a display interface capable of sampling a video signal without being affected by changes in the environment.

[0009]

In order to solve the above-mentioned problems, the display interface according to claim 1 is synchronized with a first reference clock therein from a personal computer or the like,
Video signal data (VID) generated and output for a CRT, a first horizontal synchronizing signal (HS), and a first
The vertical synchronizing signal (VS) of (1) is input to generate a signal for displaying the effective portion of the video signal data on the display (12, etc.) that does not require the back porch and front porch in the two synchronizing signals. In the interface for display to be given as a result, at least the first horizontal synchronizing signal is used as a trigger to divide the period of the horizontal synchronizing signal into a predetermined value, and the second period having the same period and the same phase as the first reference clock is generated. Frequency dividing means (21 to 24, etc.) for generating a reference clock (VCLK0, etc.), a back porch period in the first horizontal synchronizing signal, and a valid period of the video signal data following the back porch are set as a second reference clock. Of the predetermined horizontal values (80 pulses, 640 pulses, etc.) corresponding to these two periods, respectively, to detect the second horizontal horizontal period indicating the valid period of the video signal data. Means for generating a signal (HS1) (2
5 to 31) and the like.

According to a second aspect of the present invention, there is provided a display interface according to the first aspect, wherein the frequency dividing means is a PLL circuit. In the display interface according to claim 3, in the display interface according to claim 1 or 2, the display is a thin display.

[0011]

Function: The rising edge of the horizontal synchronizing signal HS output from the personal computer is triggered by an edge, and the period of the horizontal synchronizing signal HS is divided by dividing the period of the horizontal synchronizing signal HS while the trigger time is set to 0 °, and the video signal data output from the personal computer. A reference clock VCLK0 for sampling VID is generated.

As described above, the video signal data VID and the horizontal synchronizing signal HS output at a predetermined timing are used as a trigger to generate the reference clock VCLK0 for sampling the video data VID. There is no need to artificially adjust the clock.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block circuit diagram showing a main structure of a display interface as an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. Next, the configuration and operation of FIG. 1 will be described with reference to FIG. FIG. 1 is roughly divided into the following two block circuit groups.

Horizontal sync signal H output from a personal computer
A block circuit group that generates a reference clock VCLK0 by using S as a trigger, and a block circuit group that deletes the back porch and front porch periods from the horizontal synchronizing signal HS for display. Next, the block circuit group for generating the reference clock VCLK0 will be described. This block circuit group includes the phase comparator 21, the low-pass filter 22, the voltage controlled oscillator (abbreviated as VCO) 23, and the 1 / N frequency divider 24 of FIG. 1, and constitutes a PLL circuit as a whole. Now the horizontal sync signal H from the personal computer for this interface
When there is no S input, the voltage controlled oscillator (VCO) 23
Oscillates at the free-running frequency fo. Next, when the horizontal synchronizing signal HS of the frequency fs output from the personal computer is input to the phase comparator 21, the output of the phase comparator 21 compares the input frequency fs with the 1 / N frequency of the oscillation frequency fo of the VCO 23, A voltage Ve proportional to the phase difference is generated, and this voltage becomes the control voltage Vd via the low pass filter 22 and becomes VCO.
Guided to 23. The control voltage Vd operates so that the oscillation frequency fo of the VCO 23 is exactly N times the frequency fs of the input signal HS, and as a result, the reference clock VCL of the frequency fo = fs · N triggered by the horizontal synchronization signal HS.
K0 is generated. Note that N indicates the frequency division ratio, but is 1
In the / N frequency divider 24, frequency division ratio data for dividing the frequency of the reference clock VCLK of the personal computer (that is, the sampling frequency of the video signal data VID) into the horizontal synchronizing signal HS of the personal computer is input in advance.

Next, a block circuit group for deleting the back porch period and the front porch period from the horizontal synchronizing signal HS will be described. This block circuit group is shown in FIG.
It consists of 31 block circuits. As shown in FIG. 2, the video signal output from the personal computer includes a back porch (BP) and a front porch (F) before and after the horizontal synchronizing signal HS.
There is a period called P), and this portion is an unnecessary portion for the thin display device (display) 12. Therefore, in order to set the effective display period of the video signal by counting the time of each of BP and FP with the clock using the reference clock VCLK0, the circuit is configured as follows. That is, in order to delete the BP period in FIG. 1, the reference clock VCLK0 (synchronized with the horizontal synchronizing signal HS) generated by the block circuit group of the preceding stage described above is counted by the counter 25.
To enter. This counter number is: counter number = (back porch period) / (reference clock V
CLK0 cycle). In this example, 3.8 μs (backbouch period) /47.5 ns (reference clock period) = 80 (counter number), and the counter 25 is an 80-ary counter.

Further, the counter 25 is stopped once after the specified number (that is, 80 clocks) has been counted (thus, after the back porch period ends), and the driving is restarted at the next rising edge of the horizontal synchronizing signal HS. A control signal generated from a D flip-flop (abbreviated as D / FF) 27 having a carry (counting completion) output CY1 of 25 as a clock input is input to a clear terminal (inversion CLR) of the counter 25. Here, the D / FF 27 uses the fall of the carry signal CY1 of the output of the counter 25 as a trigger (clock input), and stops the counter 25 during the "L" of the horizontal synchronizing signal HS (at the rising signal of the signal HS). The signal HS is input to its own clear terminal (inversion CLR) so that it is driven.

On the other hand, the carry signal CY1 is sent to the D / FF2.
6 is input as a clock CLK. This D / FF26
Has a signal HS input to its clear terminal (inversion CLR) so that it is reset every "L" period of the horizontal synchronization signal HS. The signal CLKENB1 output from the D / FF 26 upon input of the carry signal CY1 is
Back porch BP from the rise of the horizontal synchronizing signal HS
After a period of (80 clocks of the reference clock VCLK0), it becomes H level, and this state is the next "L" of the signal HS.
It is kept until the beginning of the period. This H level signal CL
KENB1 is input to the AND gate 28 to open the gate 28, and the AND gate 28 starts outputting the reference clock VCLK0 to the 640-base counter 29. As a result, the 640-base counter 29 has the reference clock V
CLK0 is counted for 640 clocks (this period corresponds to the effective period (video signal display period of FIG. 2) necessary for displaying on the thin display 12 in the video signal data VID of the personal computer), and the carry signal CY2 is used for the JK flip-flop. A clear signal CLR is given to the control unit (abbreviated as JK / FF) 31.

On the other hand, the output signal CLKENB1 of the D / FF 26 is given to the JK / FF 31 as the clock signal CLK, and the JK / FF 31 displays the horizontal synchronizing signal HS1 for display which becomes H level only during the video signal display period. Output to 12. The display horizontal synchronizing signal HS1 is input to the AND gate 32 together with the reference clock VCLK0, and the AND gate 32
Displays the reference clock VCLK0 as the display reference clock VCLK1 only during the video signal display period excluding the back porch BP and the front porch FP.
Output to 2.

The display 12 is supplied with the video signal data VID directly from the personal computer in addition to the above-mentioned horizontal synchronizing signal HS1 for display and the reference clock VCLK1 for display, and from the vertical synchronizing signal VS from the personal computer to BP.FP. A vertical synchronizing signal V for a display in which the back porch BP and the front porch FP are deleted by the conventional method described in FIG.
S1 is given. In this way, the thin display 1
On the second side, each pixel data in the video signal data VID can be accurately sampled using the reference clock VCLK1.

FIG. 3 compares the sampling accuracy of the image signal data VID between the present invention (a in the figure) and the prior art (b) in the figure). That is, in the present invention, since the sampling position is located substantially in the center of the effective sampling range 51 (shaded area) of the video signal data, the conventional margin 53 is provided as in the margin 52 for the phase shift of the sampling position due to environmental changes. Larger than the effective range 51
Never comes off.

[0021]

The video signal data VID output from the personal computer at the transfer timing based on the internal reference clock.
In the interface for the display which displays the sample on the thin display etc. during the effective display period, the video signal data VID
The reference clock for sampling is generated by dividing the cycle by a predetermined value by using the horizontal synchronization signal HS output from the personal computer as a trigger to generate a clock whose frequency and phase match the reference clock in the personal computer. The following effects can be obtained.

The display is not disturbed even if the timing of the video signal data and the reference clock of the personal computer changes due to the fluctuation of the driving power source and the change of the environment surrounding the equipment, and the display reliability is improved. Since it is not necessary to have a manual synchronization adjustment function like the conventional fixed delay circuit, the adjustment man-hours can be eliminated, which contributes to cost reduction.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration as an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a comparison diagram of sampling accuracy of video signal data between the present invention and the related art.

FIG. 4 is a conventional circuit diagram for FIG. 1.

5 is a time chart for explaining an operation of main parts of FIG.

[Explanation of symbols]

 12 Thin Display 21 Phase Comparator 22 Low Pass Filter 23 Voltage Controlled Oscillator 24 1 / N Frequency Divider 25 80-ary Counter 26 D Flip-Flop (D / FF) 27 D Flip-Flop (D / FF) 28 AND Gate 29 640-ary Counter 30 D flip-flop (D / FF) 31 JK flip-flop (JK / FF) 32 AND gate 35 BP / FP deletion circuit HS PC horizontal sync signal VS PC vertical sync signal VID PC video signal data VCLK PC reference clock VCLK0 interface reference clock VCLK1 Reference clock for display HS1 Horizontal sync signal for display VS1 Vertical sync signal for display

Claims (3)

[Claims] 1. A video signal data, a first horizontal synchronizing signal, and a first vertical synchronizing signal which are generated and output for a CRT in synchronization with a first reference clock inside the personal computer and the like are input. A display interface that generates and supplies a signal for displaying an effective portion of the video signal data to a display that does not require a back porch and a front porch in the two synchronization signals, at least the first The horizontal synchronizing signal is used as a trigger to divide the period of the horizontal synchronizing signal into a predetermined value, and a frequency dividing means for generating a second reference clock having the same period and the same phase as the first reference clock; The back porch period in the synchronizing signal and the effective period of the video signal data following the back porch are counted to a predetermined value corresponding to these two periods of the second reference clock. Detecting I, second indicating the valid period of the video signal data
And a means for generating a horizontal synchronizing signal of the display interface. 2. The display interface according to claim 1, wherein the frequency dividing means comprises a PLL circuit. 3. The display interface according to claim 1 or 2, wherein the display is a thin display.