JPH06268633A - Method and circuit for protecting data multiplicity - Google Patents

Abstract

PURPOSE:To unnecessitate a large capacity RAM for storing data showing the number of all the objective steps by storing the numbers of continuous errors and non-errors up to the preceding step and adding '1' to the stored value in the case of the next error or non-error input. CONSTITUTION:As augend values, input data Din and the continuously generated errors/non-errors from a storage means 20 up to the preceding step are inputted to an adding means 10. Corresponding to whether the new input is the error or the non-error, the means adds '1' to the continuous number in both of cases. These continuous numbers are stored in the storage means 20 and at the same time, the added value up to the preceding step on the same time base as these input data is read from the means 20 and inputted to the means 10. Concerning the output of the means 10, set values (n) and (m) at the time of the error and non-error are compared by a comparing means 30. In the case of error continuous number >=n, an error signal is outputted from a set/reset means 40 and in the case of non-error continuous number 2 m, an error cancel signal is outputted. The number of errors/non-errors is the number of times of continuous generation and when the continuity is cut even once in the middle, the value of the means 10 is turned to '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiple protection method and circuit.

[0002]

2. Description of the Related Art If an error occurs even once in the data received during data transmission, the error frequency increases and maintenance becomes complicated. Further, it is dangerous to immediately judge that the normal state is reached even if the error state is recovered to the non-error state.

Therefore, when an error occurs in a bit on the same time axis in the front n stages (n frames), it is regarded as an error,
A so-called multiple protection system is adopted in which the error is canceled if no error occurs in the bits on the same time axis in the rear m stages.

FIG. 3 shows a conventional circuit for implementing the above-mentioned multiple protection method when n = 8 and m = 4. RAM1
A multi-terminal RAM 00 includes at least the n + m input terminals P and output terminals Q, and at least 1
It has a depth of a frame (for example, 1024 bits). Input data is sequentially written to the RAM 100 from terminals P ₁ and P ₁₀ . The data thus written is read from the terminal Q ₁ (or Q ₁₀ ) in order from the first bit, and the read data is written again from the terminal P ₂ (or P ₁₁ ). Also, terminal Q ₂
(Or Q ₁₁ ) outputs the data from terminal P ₃ (or P
₁₂ ) Further, the data inputted to the terminal Q ₃ (or Q ₁₂ ) is inputted to the terminal P ₄ (or P ₁₃ ).

As described above, one piece of data is sequentially stored in the RAM 10
It circulates in 0, and is read sequentially from the first bit for 8 frames at the same time (bits of 8 frames on the same time axis are read at the same time), and the AND gate 201 takes the logical sum. As a result, when an error occurs in bits on the same time axis in eight consecutive stages, if the error is "1" and the non-error is "0", the AND gate 20
The output of 1 becomes "1", that is, an error signal is output from the OR gate 202.

This output is also input to the input terminal P ₉ of the RAM 100, and is input to the AND gate 203 from the output terminal Q _{9 of the} RAM 100. On the other hand, the input data of the 4-stage input from the terminal P ₁₀ to P ₁₃ is read out bit 4 frames on the same time axis from an output terminal Q ₁₀ to Q ₁₃ are simultaneously inputted to the OR gate 204, the OR gate 204
The logical sum is taken with. The output of the OR gate 204 is input to the AND gate 203, whereby four stages of non-errors (“0”) are continuously output (after the terminal Q ₉ becomes “1”) after the error signal is output. Continues, the output of the OR gate 204 becomes “0”, and the AND gate 20
The output of 3 becomes "0". At this time, Q _{1 of} RAM 100
The output of the to Q ₄ are the same "0" and the output of Q ₁₀ to Q _13, the output of the AND gate 201 is also "0", the output becomes "0" error status of the OR gate 202 is released .

On the other hand, when the normal state "0" is not continued four times in succession, the output of the OR gate 204 becomes "1", the output of the AND gate 203 also becomes "1", and the output of the OR gate 202 becomes "1". It becomes 1 "and the error state is maintained.

[0008]

According to the above-mentioned conventional configuration, it is necessary to use at least n + m input terminals and a RAM having a depth of the number of bits of one frame, which is a great cost demerit and a space demerit. In addition, since the parallel processing including a plurality of RAMs is required when the frequency is increased, the cost and space disadvantages described above are further promoted.

The present invention has been proposed in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a method and a circuit capable of multiple protection of data without using a large capacity RAM.

[0010]

The present invention employs the following means in order to achieve the above object. That is, when bits on the same time axis in the front n stages are in an error state,
In the data multiplex protection method that outputs an error signal and outputs an error release signal when the bits on the same time axis in the rear m stages are in the non-error state, a continuous error of bits on the same time axis of each stage When the number is calculated and an error signal is output when the number becomes n or more, the number of consecutive non-errors of bits on the same time axis of each stage is calculated, and the number becomes m or more. At this time, an error release signal is output.

To implement the above method, the following circuit is used in the present invention. That is, as shown in FIG.
When bits on the same time axis of each stage continuously generate an error or a non-error, an addition unit that adds 1 every time the error or the non-error occurs to calculate the number of consecutive errors or non-errors (10) and the added value of the adding means (10) are stored, and the added value is used as the augend when the bits on the same time axis of the next stage are input to the adding means (10). Storage means (20) for outputting to the addition means (10), comparison means (30) for determining whether the added value of the addition means (10) is greater than n or m, and the comparison means (30) And a resetting means (40) for outputting an error signal when the number of consecutive errors is n or larger and a error canceling signal when the number of consecutive non-errors is m or larger. It will be provided.

The adding means (10) comprises an adding circuit (10a) for calculating the number of consecutive errors and an adding circuit (10b) for calculating the number of consecutive non-errors. The above comparison means (3
0) is composed of a comparator (30a) that determines whether the number of consecutive errors is greater than n and a comparator (30b) that determines whether the number of consecutive non-errors is greater than m. .

[0013]

[Operation] In addition to the input data being input to the adding means 10, the consecutive number of errors (or non-errors) that have continuously occurred up to the preceding stage is input as the augend value from the storage means 20 described later.

Thus, when the newly input data is in error, the adding means 10 increases the number of consecutive errors by one, and when it is not in error, the number of consecutive non-errors is increased by one.

The continuous number of errors or the continuous number of non-errors thus obtained is written and stored in the storage means 20, and the addition means 1 is stored in the storage means 20.
The added value up to the preceding stage on the same time axis as the data input to 0 is read out and input to the adding means 10.

The output of the adding means 10 is the storage means 2
0, and also to the comparison means 30,
The comparison means 30 compares with a predetermined set value, that is, n in the case of a continuous number of errors and m in the case of a non-error continuous number.

As a result, when the number of consecutive errors ≧ n, the set / reset means 40 is set and an error signal is output. When the number of consecutive non-errors ≧ m, the set / reset means 40 is reset and the error is released.

However, the number of errors and the number of non-errors are the numbers of times errors or non-errors occur successively. Therefore, the number of errors of the adding means 10 becomes zero if there are no errors even if the errors are continuous or even once. On the contrary, even if the non-errors are continuous, if the error occurs even once in the middle, the non-error number of the adding means 10 becomes zero.

[0019]

FIG. 2 is a block diagram showing an embodiment of the present invention. Here, an error signal is generated when a continuous error in the front 8 stages (n = 8) is detected, and a rear 4 stages (m = 4)
When a continuous non-error of is detected, the error cancellation signal is output.

The input data Din is the terminal B _{1 of the} adder 10a.
Entered in. On the other hand, the adder _{1 is connected to} the input terminals A ₁ , A ₂ and A ₃ of the adder 10a from the storage means 20 described later.
The number of consecutive errors up to the previous time corresponding to the bit on the same time axis as that input to 0a is input. Therefore, when the input data Din has an error (“1”), the adder 10
The value a is output by adding 1 to the value from the storage means 20.

However, the above-mentioned addition needs to be performed only when errors occur continuously. Therefore, the adder 1
The output of 0a is further processed by AND gates 111, 112, 113.
When a non-error (“0”) is input, the AND gates 111, 112,
113 is masked. As a result, even if errors are continuously input, if a non-error is input before the added value reaches n, the AND gate 111,
The outputs of 112 and 113 are all "0", and the storage means 2
Zero will be stored in 0. Also, in this example, n
= 8, 3 bits are sufficient for the output of the adder 10a.

Similarly, the input data Din is converted into the inverter 9
And the inverted signal (“1” when no error occurs) is input to the terminal B ₁ of the adder 10b. On the other hand, from the storage means 20, the input terminals A _{1 of} the adder 10b,
The number of consecutive non-errors up to the previous time corresponding to the same bit on the time axis as that input to the adder 10b is input to A ₂ . Therefore, when the input data Din is non-error, the adder 10b adds 1 to the output from the storage means 20 and outputs the result.

However, in this case as well, since the addition is required only when non-errors occur continuously, the output of the adder 10b is further output through the AND gates 114 and 115, and the AND gate 114 is output. , 115 are masked by the output of the inverter 9 when the input data has an error (the output of the inverter 9 is “0”).
Since m = 4 in this example, the adder 1
2 bits is enough for the output of 0b.

In the storage means 20, the depth corresponds to the number of bits of one frame, and the number of input and output terminals in this example is at least three output bits of the adder 10a,
A total of 5 output bits 2 from the adder 10b is sufficient.

The output of the adder 10a is the storage means 2
It is written from the input terminals P ₂ , P ₃ and P _{4 of} 0 in units of bits constituting a frame. On the other hand, this storage means 20
From the output terminals Q ₂ , Q ₃ , and Q _{4 of the} above, the error addition value up to the preceding stage is read from the address corresponding to the bit on the same time axis as the data input to the adder 10a, and as described above. It is input to the input terminals A ₁ , A ₂ and A ₃ of the adder 10a. This enables the adder 10a to count the number of consecutive errors. The output of the adder 10b is also the storage means 2
Data is written from the input terminals P ₅ and P _{6 of} 0 in units of bits constituting a frame. Further, from the output terminals Q ₅ and Q _{6 of} the storage means 20, from the address corresponding to the bit on the same time axis as the data input to the adder 10b,
The non-error addition values up to the preceding stage are read out and input to the input terminals A ₁ and A ₂ of the adder 10b. This enables the adder 10b to count the number of consecutive non-error states.

The output of the adder 10a is input to the comparator 30a. The comparator 30a has a setting unit 31a
When (= 8) is set and the input of the adder 10a is larger than 8, the selector 32a is opened to set / reset means 4
"1" is set to the J terminal of the flip-flop 40 _JK that configures 0.
Enter.

On the other hand, the output of the adder 10b is the comparator 3
It is input to 0b. The comparator 30b includes a setting unit 31b.
Therefore, when m (= 4) is set and the input of the adder 10b is larger than 4, the selector 32b is opened and "1" is input to the K terminal of the flip-flop 40 _JK . by this,
When the error occurs eight times in a row, the flip-flop 40 _JK set by the output of the comparator 30a is reset by the non-error occurring four times in a row.

The output of the flip-flop 40 _JK is input to the input terminal P ₁ of the storage means 20, and the output terminal Q ₁
Will be output. However, the above flip-flop 40 _JK
It is also possible to directly use the output of. When the error or non-error for each bit is found in this way, the line in which the error has occurred and the type of error are known, and thereafter necessary processing is performed.

[0029]

As described above, according to the present invention, the number of consecutive error or non-error up to the preceding stage is stored in the storage means,
Next, when an error or non-error is input, 1 is added to the stored value, so that there is an effect that a large-capacity RAM for storing the data of all target stages is not required. Therefore, there is an effect that the price merit and the space merit are increased.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional example.

[Explanation of symbols]

 10 (10a, 10b) adding means 20 storage means 30 (30a, 30b) comparing means 40 set resetting means

Claims (4)

[Claims] 1. An error signal is output when bits on the same time axis in the front n stages are in an error state, and an error release signal is output when bits on the same time axis in the rear m stages are in an error state. In the output data multiple protection method, the number of consecutive errors of bits on the same time axis of each stage is calculated, and when the number becomes n, an error signal is output,
A data multiplex protection method in which the number of consecutive non-errors of bits on the same time axis of each stage is calculated, and an error cancellation signal is output when the number reaches m. 2. An error signal is output when bits on the same time axis in the front n stages are in an error state, and an error release signal is output when bits on the same time axis in the rear m stages are in a normal state. In the output data protection circuit, when bits on the same time axis of each stage continuously generate an error or non-error, add 1 each time the error or non-error occurs to generate an error or non-error. The addition means (10) for calculating the number of consecutive times and the addition value of the addition means (10) are stored, and the addition value is input to the addition means (10) as a bit on the same time axis of the next stage. Storage means (20) for outputting to the addition means (10) as an augend when the addition is made, and comparison means (30) for judging whether the addition value of the addition means (10) is larger than n or m. As a result of the comparison by the comparison means (30), the number of consecutive errors is n or A data multiplex protection circuit comprising a set / reset means (40) which outputs an error signal when it is larger and outputs an error cancellation signal when the number of consecutive non-errors is m or larger. 3. The data multiplex according to claim 2, wherein said adding means (10) comprises an adding circuit (10a) for calculating the number of consecutive errors and an adding circuit (10b) for calculating the number of consecutive non-errors. Protection circuit. 4. The comparison means (30) has an error count of n consecutive times.
Comparator (30a) that determines whether it is greater than or equal to, and comparator (30b) that determines whether the number of consecutive non-errors is greater than m
The data multiplex protection circuit according to claim 2, further comprising: